History

Jacob Lifshay 393f78a14d All checks were successful / deps (push) Successful in 18s Details / test (push) Successful in 5m16s Details / deps (pull_request) Successful in 14s Details / test (pull_request) Successful in 5m19s Details sim: add WIP memory test		2024-12-11 23:28:15 -08:00
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examples	change register names to end in `_reg` by convention	2024-10-06 18:50:09 -07:00
src	sim: add WIP memory test	2024-12-11 23:28:15 -08:00
tests	sim: add WIP memory test	2024-12-11 23:28:15 -08:00
build.rs	WIP: use HdlOption[the_type_var] or UInt[123 + n] for creating types	2024-08-21 22:27:21 -07:00
Cargo.toml	simulator WIP: use petgraph for topological sort over assignments	2024-11-20 22:53:54 -08:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	make ClockDomain and Reg generic over reset type	2024-11-26 20:47:03 -08:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.