This website requires JavaScript.
Explore
Help
Register
Sign in
libre-chip
/
fayalite
Watch
3
Star
0
Fork
You've already forked fayalite
3
Code
Issues
1
Pull requests
1
Projects
Releases
Packages
Wiki
Activity
Actions
change vcd output to have module contents under instance's name, more closely matching how it works in verilog
#68
Merged
programmerjake
merged 1 commit from
programmerjake/fayalite:make_vcd_modules_use_instance_names
into
master
2026-03-27 02:19:16 +00:00
Conversation
0
Commits
1
Files changed
4
+120
-394
1 commit
Author
SHA1
Message
Date
Jacob Lifshay
80b92c7dd3
change vcd output to have module contents under instance's name, more closely matching how it works in verilog
All checks were successful
/ test (pull_request)
Successful in 4m18s
Details
/ test (push)
Successful in 4m54s
Details
2026-03-26 18:21:14 -07:00