crates/fayalite-proc-macros-impl/src/fold.rs

@@ -257,6 +257,5 @@ no_op_fold!(syn::Token![let]);
 no_op_fold!(syn::Token![mut]);
 no_op_fold!(syn::Token![static]);
 no_op_fold!(syn::Token![struct]);
-no_op_fold!(syn::Token![type]);
 no_op_fold!(syn::Token![where]);
 no_op_fold!(usize);

crates/fayalite-proc-macros-impl/src/hdl_bundle.rs

@@ -3,9 +3,8 @@
 use crate::{
     Errors, HdlAttr, PairsIterExt,
     hdl_type_common::{
-        CustomDebugOptions, CustomDebugTrait, ItemOptions, MakeHdlTypeExpr, MaybeParsed,
+        ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedField, ParsedFieldsNamed, ParsedGenerics,
-        ParsedField, ParsedFieldsNamed, ParsedGenerics, SplitForImpl, TypesParser, WrappedInConst,
+        SplitForImpl, TypesParser, WrappedInConst, common_derives, get_target,
-        common_derives, create_struct_debug_impl, get_target,
     },
     kw,
 };
@@ -31,7 +30,6 @@ pub(crate) struct ParsedBundle {
     pub(crate) fields: MaybeParsed<ParsedFieldsNamed, FieldsNamed>,
     pub(crate) field_flips: Vec<Option<HdlAttr<kw::flip, kw::hdl>>>,
     pub(crate) mask_type_ident: Ident,
-    pub(crate) mask_type_name: String,
     pub(crate) mask_type_match_variant_ident: Ident,
     pub(crate) mask_type_sim_value_ident: Ident,
     pub(crate) match_variant_ident: Ident,
@@ -90,8 +88,6 @@ impl ParsedBundle {
             no_runtime_generics: _,
             cmp_eq: _,
             ref get,
-            custom_debug: _,
-            custom_sim_display: _,
         } = options.body;
         if let Some((get, ..)) = get {
             errors.error(get, "#[hdl(get(...))] is not allowed on structs");
@@ -135,7 +131,6 @@ impl ParsedBundle {
             fields,
             field_flips,
             mask_type_ident: format_ident!("__{}__MaskType", ident),
-            mask_type_name: format!("MaskType<{}>", ident),
             mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident),
             mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident),
             match_variant_ident: format_ident!("__{}__MatchVariant", ident),
@@ -453,7 +448,6 @@ impl ToTokens for ParsedBundle {
             fields,
             field_flips,
             mask_type_ident,
-            mask_type_name,
             mask_type_match_variant_ident,
             mask_type_sim_value_ident,
             match_variant_ident,
@@ -470,20 +464,11 @@ impl ToTokens for ParsedBundle {
             no_runtime_generics,
             cmp_eq,
             get: _,
-            custom_debug: _,
-            custom_sim_display,
         } = &options.body;
-        let CustomDebugOptions {
-            type_: custom_debug_type,
-            sim: custom_debug_sim,
-            mask_type: custom_debug_mask_type,
-            mask_sim: custom_debug_mask_sim,
-        } = options.body.custom_debug();
         let target = get_target(target, ident);
-        let struct_name = ident.to_string();
         let mut item_attrs = attrs.clone();
-        item_attrs.push(common_derives(span, false));
+        item_attrs.push(common_derives(span));
-        let type_struct = ItemStruct {
+        ItemStruct {
             attrs: item_attrs,
             vis: vis.clone(),
             struct_token: *struct_token,
@@ -491,8 +476,8 @@ impl ToTokens for ParsedBundle {
             generics: generics.into(),
             fields: Fields::Named(fields.clone().into()),
             semi_token: None,
-        };
+        }
-        type_struct.to_tokens(tokens);
+        .to_tokens(tokens);
         let (impl_generics, type_generics, where_clause) = generics.split_for_impl();
         if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(fields), None) =
             (generics, fields, no_runtime_generics)
@@ -518,9 +503,6 @@ impl ToTokens for ParsedBundle {
         }
         let mut wrapped_in_const = WrappedInConst::new(tokens, span);
         let tokens = wrapped_in_const.inner();
-        if custom_debug_type.is_none() {
-            create_struct_debug_impl(&type_struct, &struct_name, None).to_tokens(tokens);
-        }
         let builder = Builder {
             vis: vis.clone(),
             struct_token: *struct_token,
@@ -548,9 +530,9 @@ impl ToTokens for ParsedBundle {
         mask_type_builder.to_tokens(tokens);
         let unfilled_mask_type_builder_ty =
             mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled);
-        let mask_type_struct = ItemStruct {
+        ItemStruct {
             attrs: vec![
-                common_derives(span, false),
+                common_derives(span),
                 parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types, dead_code)]
                 },
@@ -561,20 +543,17 @@ impl ToTokens for ParsedBundle {
             generics: generics.into(),
             fields: Fields::Named(mask_type_fields.clone()),
             semi_token: None,
-        };
-        mask_type_struct.to_tokens(tokens);
-        if custom_debug_mask_type.is_none() {
-            create_struct_debug_impl(&mask_type_struct, mask_type_name, None).to_tokens(tokens);
         }
+        .to_tokens(tokens);
         let mut mask_type_match_variant_fields = mask_type_fields.clone();
         for Field { ty, .. } in &mut mask_type_match_variant_fields.named {
             *ty = parse_quote_spanned! {span=>
                 ::fayalite::expr::Expr<#ty>
             };
         }
-        let mask_type_match_variant_struct = ItemStruct {
+        ItemStruct {
             attrs: vec![
-                common_derives(span, false),
+                common_derives(span),
                 parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types, dead_code)]
                 },
@@ -585,19 +564,17 @@ impl ToTokens for ParsedBundle {
             generics: generics.into(),
             fields: Fields::Named(mask_type_match_variant_fields),
             semi_token: None,
-        };
+        }
-        mask_type_match_variant_struct.to_tokens(tokens);
+        .to_tokens(tokens);
-        create_struct_debug_impl(&mask_type_match_variant_struct, mask_type_name, None)
-            .to_tokens(tokens);
         let mut match_variant_fields = FieldsNamed::from(fields.clone());
         for Field { ty, .. } in &mut match_variant_fields.named {
             *ty = parse_quote_spanned! {span=>
                 ::fayalite::expr::Expr<#ty>
             };
         }
-        let match_variant_struct = ItemStruct {
+        ItemStruct {
             attrs: vec![
-                common_derives(span, false),
+                common_derives(span),
                 parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types, dead_code)]
                 },
@@ -608,19 +585,19 @@ impl ToTokens for ParsedBundle {
             generics: generics.into(),
             fields: Fields::Named(match_variant_fields),
             semi_token: None,
-        };
+        }
-        match_variant_struct.to_tokens(tokens);
+        .to_tokens(tokens);
-        create_struct_debug_impl(&match_variant_struct, &struct_name, None).to_tokens(tokens);
         let mut mask_type_sim_value_fields = mask_type_fields;
         for Field { ty, .. } in &mut mask_type_sim_value_fields.named {
             *ty = parse_quote_spanned! {span=>
                 ::fayalite::sim::value::SimValue<#ty>
             };
         }
-        let mask_type_sim_value_struct = ItemStruct {
+        ItemStruct {
             attrs: vec![
                 parse_quote_spanned! {span=>
                     #[::fayalite::__std::prelude::v1::derive(
+                        ::fayalite::__std::fmt::Debug,
                         ::fayalite::__std::clone::Clone,
                     )]
                 },
@@ -634,34 +611,19 @@ impl ToTokens for ParsedBundle {
             generics: generics.into(),
             fields: Fields::Named(mask_type_sim_value_fields),
             semi_token: None,
-        };
-        mask_type_sim_value_struct.to_tokens(tokens);
-        if custom_debug_mask_sim.is_none() {
-            create_struct_debug_impl(
-                &mask_type_struct,
-                mask_type_name,
-                Some(CustomDebugTrait {
-                    trait_path: &parse_quote_spanned! {span=>
-                        ::fayalite::ty::SimValueDebug
-                    },
-                    fn_name: &format_ident!("sim_value_debug", span = span),
-                    this_arg: &parse_quote_spanned! {span=>
-                        value: &<Self as ::fayalite::ty::Type>::SimValue
-                    },
-                }),
-            )
-            .to_tokens(tokens);
         }
+        .to_tokens(tokens);
         let mut sim_value_fields = FieldsNamed::from(fields.clone());
         for Field { ty, .. } in &mut sim_value_fields.named {
             *ty = parse_quote_spanned! {span=>
                 ::fayalite::sim::value::SimValue<#ty>
             };
         }
-        let sim_value_struct = ItemStruct {
+        ItemStruct {
             attrs: vec![
                 parse_quote_spanned! {span=>
                     #[::fayalite::__std::prelude::v1::derive(
+                        ::fayalite::__std::fmt::Debug,
                         ::fayalite::__std::clone::Clone,
                     )]
                 },
@@ -675,36 +637,8 @@ impl ToTokens for ParsedBundle {
             generics: generics.into(),
             fields: Fields::Named(sim_value_fields),
             semi_token: None,
-        };
-        sim_value_struct.to_tokens(tokens);
-        if custom_debug_sim.is_none() {
-            create_struct_debug_impl(
-                &type_struct,
-                &struct_name,
-                Some(CustomDebugTrait {
-                    trait_path: &parse_quote_spanned! {span=>
-                        ::fayalite::ty::SimValueDebug
-                    },
-                    fn_name: &format_ident!("sim_value_debug", span = span),
-                    this_arg: &parse_quote_spanned! {span=>
-                        value: &<Self as ::fayalite::ty::Type>::SimValue
-                    },
-                }),
-            )
-            .to_tokens(tokens);
-        }
-        if custom_sim_display.is_some() {
-            quote_spanned! {span=>
-                #[automatically_derived]
-                impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics
-                #where_clause
-                {
-                    fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                        <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f)
-                    }
-                }
-            }.to_tokens(tokens);
         }
+        .to_tokens(tokens);
         let this_token = Ident::new("__this", span);
         let fields_token = Ident::new("__fields", span);
         let self_token = Token![self](span);
@@ -886,14 +820,6 @@ impl ToTokens for ParsedBundle {
                 }
             }
             #[automatically_derived]
-            impl #impl_generics ::fayalite::__std::fmt::Debug for #mask_type_sim_value_ident #type_generics
-            #where_clause
-            {
-                fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                    <#mask_type_ident #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f)
-                }
-            }
-            #[automatically_derived]
             impl #impl_generics ::fayalite::expr::ValueType for #mask_type_sim_value_ident #type_generics
             #where_clause
             {
@@ -1054,14 +980,6 @@ impl ToTokens for ParsedBundle {
                 }
             }
             #[automatically_derived]
-            impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics
-            #where_clause
-            {
-                fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                    <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f)
-                }
-            }
-            #[automatically_derived]
             impl #impl_generics ::fayalite::expr::ValueType for #sim_value_ident #type_generics
             #where_clause
             {
@@ -1223,7 +1141,7 @@ impl ToTokens for ParsedBundle {
                 valueless_eq_body = quote_spanned! {span=>
                     let __lhs = ::fayalite::expr::ValueType::ty(&__lhs);
                     let __rhs = ::fayalite::expr::ValueType::ty(&__rhs);
-                    #(#fields_valueless_eq)&*
+                    #(#fields_valueless_eq)|*
                 };
                 valueless_ne_body = quote_spanned! {span=>
                     let __lhs = ::fayalite::expr::ValueType::ty(&__lhs);

crates/fayalite-proc-macros-impl/src/hdl_enum.rs

@@ -3,9 +3,8 @@
 use crate::{
     Errors, HdlAttr, PairsIterExt,
     hdl_type_common::{
-        CustomDebugOptions, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType,
+        ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, SplitForImpl,
-        SplitForImpl, TypesParser, WrappedInConst, common_derives, create_struct_debug_impl,
+        TypesParser, WrappedInConst, common_derives, get_target,
-        get_target,
     },
     kw,
 };
@@ -159,32 +158,15 @@ impl ParsedEnum {
             custom_bounds,
             no_static: _,
             no_runtime_generics: _,
-            cmp_eq: _,
+            cmp_eq,
             ref get,
-            custom_debug: _,
-            custom_sim_display: _,
         } = options.body;
+        if let Some((cmp_eq,)) = cmp_eq {
+            errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums");
+        }
         if let Some((get, ..)) = get {
             errors.error(get, "#[hdl(get(...))] is not allowed on enums");
         }
-        let CustomDebugOptions {
-            type_: _,
-            sim: _,
-            mask_type,
-            mask_sim,
-        } = options.body.custom_debug();
-        if let Some((mask_type,)) = mask_type {
-            errors.error(
-                mask_type,
-                "#[hdl(custom_debug(mask_type)] is not allowed on enums",
-            );
-        }
-        if let Some((mask_sim,)) = mask_sim {
-            errors.error(
-                mask_sim,
-                "#[hdl(custom_debug(mask_sim)] is not allowed on enums",
-            );
-        }
         attrs.retain(|attr| {
             if attr.path().is_ident("repr") {
                 errors.error(attr, "#[repr] is not supported on #[hdl] enums");
@@ -246,21 +228,12 @@ impl ToTokens for ParsedEnum {
             custom_bounds: _,
             no_static,
             no_runtime_generics,
-            cmp_eq,
+            cmp_eq: _, // TODO: implement cmp_eq for enums
             get: _,
-            custom_debug: _,
-            custom_sim_display,
         } = &options.body;
-        let CustomDebugOptions {
-            type_: custom_debug_type,
-            sim: custom_debug_sim,
-            mask_type: _,
-            mask_sim: _,
-        } = options.body.custom_debug();
         let target = get_target(target, ident);
-        let enum_name = ident.to_string();
         let mut struct_attrs = attrs.clone();
-        struct_attrs.push(common_derives(span, false));
+        struct_attrs.push(common_derives(span));
         struct_attrs.push(parse_quote_spanned! {span=>
             #[allow(non_snake_case)]
         });
@@ -300,7 +273,7 @@ impl ToTokens for ParsedEnum {
                 }
             },
         ));
-        let type_struct = ItemStruct {
+        ItemStruct {
             attrs: struct_attrs,
             vis: vis.clone(),
             struct_token: Token![struct](enum_token.span),
@@ -315,8 +288,8 @@ impl ToTokens for ParsedEnum {
                 })
             },
             semi_token: None,
-        };
+        }
-        type_struct.to_tokens(tokens);
+        .to_tokens(tokens);
         let (impl_generics, type_generics, where_clause) = generics.split_for_impl();
         if let (MaybeParsed::Parsed(generics), None) = (generics, no_runtime_generics) {
             generics.make_runtime_generics(tokens, vis, ident, &target, |context| {
@@ -400,9 +373,6 @@ impl ToTokens for ParsedEnum {
             }
             .to_tokens(tokens);
         }
-        if custom_debug_type.is_none() {
-            create_struct_debug_impl(&type_struct, &enum_name, None).to_tokens(tokens);
-        }
         let mut enum_attrs = attrs.clone();
         enum_attrs.push(parse_quote_spanned! {span=>
             #[allow(dead_code, non_camel_case_types)]
@@ -483,6 +453,7 @@ impl ToTokens for ParsedEnum {
         let mut enum_attrs = attrs.clone();
         enum_attrs.push(parse_quote_spanned! {span=>
             #[::fayalite::__std::prelude::v1::derive(
+                ::fayalite::__std::fmt::Debug,
                 ::fayalite::__std::clone::Clone,
             )]
         });
@@ -867,240 +838,6 @@ impl ToTokens for ParsedEnum {
                     },
                 )),
         );
-        if custom_debug_sim.is_none() {
-            let debug_match_arms = Vec::from_iter(
-                variants
-                    .iter()
-                    .map(
-                        |ParsedVariant {
-                             attrs: _,
-                             options: _,
-                             ident,
-                             field,
-                         }| {
-                            let variant_name = ident.to_string();
-                            if let Some(_) = field {
-                                quote_spanned! {span=>
-                                    #sim_value_ident::#ident(field, _) => {
-                                        f.debug_tuple(#variant_name).field(field).finish()
-                                    }
-                                }
-                            } else {
-                                quote_spanned! {span=>
-                                    #sim_value_ident::#ident(_) => {
-                                        f.write_str(#variant_name)
-                                    }
-                                }
-                            }
-                        },
-                    )
-                    .chain(sim_value_unknown_variant_name.as_ref().map(
-                        |sim_value_unknown_variant_name| {
-                            let sim_value_unknown_variant_name_str =
-                                sim_value_unknown_variant_name.to_string();
-                            quote_spanned! {span=>
-                                #sim_value_ident::#sim_value_unknown_variant_name(_) => {
-                                    f.write_str(#sim_value_unknown_variant_name_str)
-                                }
-                            }
-                        },
-                    )),
-            );
-            quote_spanned! {span=>
-                #[automatically_derived]
-                impl #impl_generics ::fayalite::ty::SimValueDebug for #target #type_generics
-                #where_clause
-                {
-                    fn sim_value_debug(
-                        value: &<Self as ::fayalite::ty::Type>::SimValue,
-                        f: &mut ::fayalite::__std::fmt::Formatter<'_>,
-                    ) -> ::fayalite::__std::fmt::Result {
-                        match value {
-                            #(#debug_match_arms)*
-                        }
-                    }
-                }
-            }
-            .to_tokens(tokens);
-        }
-        if custom_sim_display.is_some() {
-            quote_spanned! {span=>
-                #[automatically_derived]
-                impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics
-                #where_clause
-                {
-                    fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                        <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f)
-                    }
-                }
-            }.to_tokens(tokens);
-        }
-        if let Some((cmp_eq,)) = cmp_eq {
-            let mut cmp_eq_where_clause =
-                Generics::from(generics)
-                    .where_clause
-                    .unwrap_or_else(|| syn::WhereClause {
-                        where_token: Token![where](span),
-                        predicates: Punctuated::new(),
-                    });
-            let mut variants_value_eq = vec![];
-            let mut variants_expr_eq = vec![];
-            let mut fields_valueless_eq = vec![];
-            for (
-                variant_index,
-                ParsedVariant {
-                    attrs: _,
-                    options: variant_options,
-                    ident: variant_ident,
-                    field,
-                },
-            ) in variants.iter().enumerate()
-            {
-                let VariantOptions {} = variant_options.body;
-                if let Some(ParsedVariantField {
-                    paren_token: _,
-                    attrs: _,
-                    options: field_options,
-                    ty: field_ty,
-                    comma_token: _,
-                }) = field
-                {
-                    let FieldOptions {} = field_options.body;
-                    cmp_eq_where_clause
-                        .predicates
-                        .push(parse_quote_spanned! {cmp_eq.span=>
-                            #field_ty: ::fayalite::expr::HdlPartialEqImpl<#field_ty>
-                        });
-                    variants_value_eq.push(quote_spanned! {span=>
-                        (#sim_value_ident::#variant_ident(__lhs_field, _), #sim_value_ident::#variant_ident(__rhs_field, _)) => {
-                            ::fayalite::expr::HdlPartialEqImpl::cmp_value_eq(
-                                __lhs.#variant_ident,
-                                ::fayalite::__std::borrow::Cow::Borrowed(__lhs_field),
-                                __rhs.#variant_ident,
-                                ::fayalite::__std::borrow::Cow::Borrowed(__rhs_field),
-                            )
-                        }
-                    });
-                    variants_expr_eq.push(quote_spanned! {span=>
-                        {
-                            let (#match_variant_ident::#variant_ident(__lhs), __scope) =
-                                ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                                    ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter)
-                                        .expect("known to have enough variants"),
-                                )
-                            else {
-                                ::fayalite::__std::unreachable!();
-                            };
-                            let (#match_variant_ident::#variant_ident(__rhs), __scope) =
-                                ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                                    ::fayalite::__std::iter::Iterator::nth(
-                                        &mut ::fayalite::module::match_(__rhs),
-                                        #variant_index,
-                                    )
-                                        .expect("known to have variant"),
-                                )
-                            else {
-                                ::fayalite::__std::unreachable!();
-                            };
-                            ::fayalite::module::connect(__retval, ::fayalite::expr::HdlPartialEqImpl::cmp_expr_eq(__lhs, __rhs));
-                        }
-                    });
-                    fields_valueless_eq.push(quote_spanned! {span=>
-                        ::fayalite::expr::HdlPartialEqImpl::cmp_valueless_eq(
-                            ::fayalite::expr::Valueless::new(__lhs.#variant_ident),
-                            ::fayalite::expr::Valueless::new(__rhs.#variant_ident),
-                        )
-                    });
-                } else {
-                    variants_value_eq.push(quote_spanned! {span=>
-                        (#sim_value_ident::#variant_ident(_), #sim_value_ident::#variant_ident(_)) => true,
-                    });
-                    variants_expr_eq.push(quote_spanned! {span=>
-                        {
-                            let (#match_variant_ident::#variant_ident, __scope) =
-                                ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                                    ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter)
-                                        .expect("known to have enough variants"),
-                                )
-                            else {
-                                ::fayalite::__std::unreachable!();
-                            };
-                            let (#match_variant_ident::#variant_ident, __scope) =
-                                ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                                    ::fayalite::__std::iter::Iterator::nth(
-                                        &mut ::fayalite::module::match_(__rhs),
-                                        #variant_index,
-                                    )
-                                        .expect("known to have variant"),
-                                )
-                            else {
-                                ::fayalite::__std::unreachable!();
-                            };
-                            ::fayalite::module::connect(__retval, true);
-                        }
-                    });
-                }
-            }
-            if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name {
-                variants_value_eq.push(quote_spanned! {span=>
-                    (#sim_value_ident::#sim_value_unknown_variant_name(__lhs_unknown), #sim_value_ident::#sim_value_unknown_variant_name(__rhs_unknown)) => {
-                        __lhs_unknown == __rhs_unknown
-                    }
-                });
-            }
-            let valueless_eq_body = if fields_valueless_eq.is_empty() {
-                quote_spanned! {span=>
-                    ::fayalite::expr::Valueless::new(::fayalite::int::Bool)
-                }
-            } else {
-                quote_spanned! {span=>
-                    let __lhs = ::fayalite::expr::ValueType::ty(&__lhs);
-                    let __rhs = ::fayalite::expr::ValueType::ty(&__rhs);
-                    #(#fields_valueless_eq)&*
-                }
-            };
-            let cmp_expr_eq_wire_name = format!("{ident}_cmp_eq");
-            quote_spanned! {span=>
-                #[automatically_derived]
-                impl #impl_generics ::fayalite::expr::HdlPartialEqImpl<Self> for #target #type_generics
-                #cmp_eq_where_clause
-                {
-                    #[track_caller]
-                    fn cmp_value_eq(
-                        __lhs: Self,
-                        __lhs_value: ::fayalite::__std::borrow::Cow<'_, <Self as ::fayalite::ty::Type>::SimValue>,
-                        __rhs: Self,
-                        __rhs_value: ::fayalite::__std::borrow::Cow<'_, <Self as ::fayalite::ty::Type>::SimValue>,
-                    ) -> ::fayalite::__std::primitive::bool {
-                        match (&*__lhs_value, &*__rhs_value) {
-                            #(#variants_value_eq)*
-                            _ => false,
-                        }
-                    }
-
-                    #[track_caller]
-                    fn cmp_expr_eq(
-                        __lhs: ::fayalite::expr::Expr<Self>,
-                        __rhs: ::fayalite::expr::Expr<Self>,
-                    ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> {
-                        let __retval = ::fayalite::module::wire(::fayalite::module::ImplicitName(#cmp_expr_eq_wire_name), ::fayalite::int::Bool);
-                        ::fayalite::module::connect(__retval, false);
-                        let mut __lhs_match_variant_iter = ::fayalite::module::match_(__lhs);
-                        #(#variants_expr_eq)*
-                        __retval
-                    }
-
-                    #[track_caller]
-                    fn cmp_valueless_eq(
-                        __lhs: ::fayalite::expr::Valueless<Self>,
-                        __rhs: ::fayalite::expr::Valueless<Self>,
-                    ) -> ::fayalite::expr::Valueless<::fayalite::int::Bool> {
-                        #valueless_eq_body
-                    }
-                }
-            }
-            .to_tokens(tokens);
-        }
         let variants_len = variants.len();
         quote_spanned! {span=>
             #[automatically_derived]
@@ -1197,14 +934,6 @@ impl ToTokens for ParsedEnum {
                 }
             }
             #[automatically_derived]
-            impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics
-            #where_clause
-            {
-                fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                    <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f)
-                }
-            }
-            #[automatically_derived]
             impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics>
             for #sim_value_ident #type_generics
             #where_clause

crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs

@@ -215,8 +215,6 @@ impl ParsedTypeAlias {
             no_runtime_generics,
             cmp_eq,
             get: _,
-            ref custom_debug,
-            custom_sim_display,
         } = options.body;
         if let Some((no_static,)) = no_static {
             errors.error(no_static, "no_static is not valid on type aliases");
@@ -236,15 +234,6 @@ impl ParsedTypeAlias {
         if let Some((cmp_eq,)) = cmp_eq {
             errors.error(cmp_eq, "cmp_eq is not valid on type aliases");
         }
-        if let Some((custom_debug, _, _)) = custom_debug {
-            errors.error(custom_debug, "custom_debug is not valid on type aliases");
-        }
-        if let Some((custom_sim_display,)) = custom_sim_display {
-            errors.error(
-                custom_sim_display,
-                "custom_sim_display is not valid on type aliases",
-            );
-        }
         if let Some((custom_bounds,)) = custom_bounds {
             errors.error(
                 custom_bounds,
@@ -298,8 +287,6 @@ impl ParsedTypeAlias {
             no_runtime_generics: _,
             cmp_eq,
             ref mut get,
-            ref custom_debug,
-            custom_sim_display,
         } = options.body;
         if let Some(get) = get.take() {
             return Self::parse_phantom_const_accessor(
@@ -324,15 +311,6 @@ impl ParsedTypeAlias {
         if let Some((cmp_eq,)) = cmp_eq {
             errors.error(cmp_eq, "cmp_eq is not valid on type aliases");
         }
-        if let Some((custom_debug, _, _)) = custom_debug {
-            errors.error(custom_debug, "custom_debug is not valid on type aliases");
-        }
-        if let Some((custom_sim_display,)) = custom_sim_display {
-            errors.error(
-                custom_sim_display,
-                "custom_sim_display is not valid on type aliases",
-            );
-        }
         let generics = if custom_bounds.is_some() {
             MaybeParsed::Unrecognized(generics)
         } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) {
@@ -378,8 +356,6 @@ impl ToTokens for ParsedTypeAlias {
                     no_runtime_generics,
                     cmp_eq: _,
                     get: _,
-                    custom_debug: _,
-                    custom_sim_display: _,
                 } = &options.body;
                 let target = get_target(target, ident);
                 let mut type_attrs = attrs.clone();
@@ -426,8 +402,6 @@ impl ToTokens for ParsedTypeAlias {
                     no_runtime_generics: _,
                     cmp_eq: _,
                     get: _,
-                    custom_debug: _,
-                    custom_sim_display: _,
                 } = &options.body;
                 let span = ident.span();
                 let mut type_attrs = attrs.clone();
@@ -453,7 +427,7 @@ impl ToTokens for ParsedTypeAlias {
                     format_ident!("__{}__GenericsAccumulation", ident);
                 ItemStruct {
                     attrs: vec![
-                        common_derives(span, true),
+                        common_derives(span),
                         parse_quote_spanned! {span=>
                             #[allow(non_camel_case_types)]
                         },

crates/fayalite-proc-macros-impl/src/hdl_type_common.rs

@@ -7,10 +7,10 @@ use std::{collections::HashMap, fmt, mem};
 use syn::{
     AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup,
     ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed,
-    FieldsUnnamed, FnArg, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index,
+    FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct,
-    ItemStruct, Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound,
+    Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish,
-    Turbofish, Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath,
+    Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple,
-    TypeTuple, Visibility, WhereClause, WherePredicate,
+    Visibility, WhereClause, WherePredicate,
     parse::{Parse, ParseStream},
     parse_quote, parse_quote_spanned,
     punctuated::{Pair, Punctuated},
@@ -18,17 +18,6 @@ use syn::{
     token::{Brace, Bracket, Paren},
 };
 
-crate::options! {
-    #[options = CustomDebugOptions]
-    #[no_ident_fragment]
-    pub(crate) enum CustomDebugOption {
-        Type(type_),
-        Sim(sim),
-        MaskType(mask_type),
-        MaskSim(mask_sim),
-    }
-}
-
 crate::options! {
     #[options = ItemOptions]
     pub(crate) enum ItemOption {
@@ -39,8 +28,6 @@ crate::options! {
         NoRuntimeGenerics(no_runtime_generics),
         CmpEq(cmp_eq),
         Get(get, Expr),
-        CustomDebug(custom_debug, CustomDebugOptions),
-        CustomSimDisplay(custom_sim_display),
     }
 }
 
@@ -54,36 +41,8 @@ impl ItemOptions {
         {
             self.no_static = Some((kw::no_static(custom_bounds.span),));
         }
-        if let Some((kw, _, custom_debug)) = &mut self.custom_debug {
-            if let CustomDebugOptions {
-                type_: None,
-                sim: None,
-                mask_type: None,
-                mask_sim: None,
-            } = custom_debug
-            {
-                *custom_debug = CustomDebugOptions {
-                    type_: Some((kw::type_(kw.span),)),
-                    sim: Some((kw::sim(kw.span),)),
-                    mask_type: None,
-                    mask_sim: None,
-                };
-            }
-        }
         Ok(())
     }
-    pub(crate) fn custom_debug(&self) -> &CustomDebugOptions {
-        self.custom_debug.as_ref().map(|v| &v.2).unwrap_or(
-            const {
-                &CustomDebugOptions {
-                    type_: None,
-                    sim: None,
-                    mask_type: None,
-                    mask_sim: None,
-                }
-            },
-        )
-    }
 }
 
 pub(crate) struct WrappedInConst<'a> {
@@ -125,17 +84,10 @@ pub(crate) fn get_target(target: &Option<(kw::target, Paren, Path)>, item_ident:
     }
 }
 
-pub(crate) fn common_derives(span: Span, include_debug: bool) -> Attribute {
+pub(crate) fn common_derives(span: Span) -> Attribute {
-    let debug = include_debug
-        .then(|| {
-            quote_spanned! {span=>
-                ::fayalite::__std::fmt::Debug
-            }
-        })
-        .into_iter();
     parse_quote_spanned! {span=>
         #[::fayalite::__std::prelude::v1::derive(
-            #(#debug,)*
+            ::fayalite::__std::fmt::Debug,
             ::fayalite::__std::cmp::Eq,
             ::fayalite::__std::cmp::PartialEq,
             ::fayalite::__std::hash::Hash,
@@ -3023,7 +2975,7 @@ impl ParsedGenerics {
         let span = ident.span();
         ItemStruct {
             attrs: vec![
-                common_derives(span, true),
+                common_derives(span),
                 parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types)]
                 },
@@ -4781,109 +4733,3 @@ impl ParsedVisibility {
             .map(|ord| if ord.is_lt() { self } else { other })
     }
 }
-
-pub(crate) struct CustomDebugTrait<'a> {
-    pub(crate) trait_path: &'a Path,
-    pub(crate) fn_name: &'a Ident,
-    pub(crate) this_arg: &'a FnArg,
-}
-
-#[must_use]
-pub(crate) fn create_struct_debug_impl(
-    item_struct: &ItemStruct,
-    debug_struct_name: &str,
-    custom_debug_trait: Option<CustomDebugTrait<'_>>,
-) -> TokenStream {
-    let ident = &item_struct.ident;
-    let span = ident.span();
-    let (impl_generics, type_generics, where_clause) = item_struct.generics.split_for_impl();
-    let trait_path;
-    let fn_name;
-    let this_arg;
-    let CustomDebugTrait {
-        trait_path,
-        fn_name,
-        this_arg,
-    } = match custom_debug_trait {
-        Some(v) => v,
-        None => {
-            trait_path = parse_quote_spanned! {span=>
-                ::fayalite::__std::fmt::Debug
-            };
-            fn_name = parse_quote_spanned! {span=>
-                fmt
-            };
-            this_arg = parse_quote_spanned! {span=>
-                &self
-            };
-            CustomDebugTrait {
-                trait_path: &trait_path,
-                fn_name: &fn_name,
-                this_arg: &this_arg,
-            }
-        }
-    };
-    let this_arg_name = match this_arg {
-        FnArg::Receiver(this_arg) => this_arg.self_token.to_token_stream(),
-        FnArg::Typed(this_arg) => match &*this_arg.pat {
-            syn::Pat::Ident(pat_ident) => pat_ident.ident.to_token_stream(),
-            _ => unreachable!(),
-        },
-    };
-    match &item_struct.fields {
-        Fields::Named(fields) => {
-            let field_idents = fields
-                .named
-                .iter()
-                .map(|v| v.ident.as_ref().expect("known to have field name"));
-            let field_names = field_idents.clone().map(|v| v.to_string());
-            quote_spanned! {span=>
-                #[automatically_derived]
-                impl #impl_generics #trait_path for #ident #type_generics
-                #where_clause
-                {
-                    fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                        let _ = #this_arg_name;
-                        f.debug_struct(#debug_struct_name)
-                            #(.field(#field_names, &#this_arg_name.#field_idents))*
-                            .finish()
-                    }
-                }
-            }
-        }
-        Fields::Unnamed(fields) => {
-            let field_members = fields
-                .unnamed
-                .iter()
-                .enumerate()
-                .map(|(index, _)| syn::Index {
-                    index: index as _,
-                    span,
-                });
-            quote_spanned! {span=>
-                #[automatically_derived]
-                impl #impl_generics #trait_path for #ident #type_generics
-                #where_clause
-                {
-                    fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                        let _ = #this_arg_name;
-                        f.debug_tuple(#debug_struct_name)
-                            #(.field(&#this_arg_name.#field_members))*
-                            .finish()
-                    }
-                }
-            }
-        }
-        Fields::Unit => quote_spanned! {ident.span()=>
-            #[automatically_derived]
-            impl #impl_generics #trait_path for #ident #type_generics
-            #where_clause
-            {
-                fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
-                    let _ = #this_arg_name;
-                    f.write_str(#debug_struct_name)
-                }
-            }
-        },
-    }
-}

crates/fayalite-proc-macros-impl/src/lib.rs

@@ -42,7 +42,6 @@ pub(crate) trait CustomToken:
 
 mod kw {
     pub(crate) use syn::token::Extern as extern_;
-    pub(crate) use syn::token::Type as type_;
 
     macro_rules! custom_keyword {
         ($kw:ident) => {
@@ -76,8 +75,6 @@ mod kw {
     custom_keyword!(cmp_eq);
     custom_keyword!(connect_inexact);
     custom_keyword!(custom_bounds);
-    custom_keyword!(custom_debug);
-    custom_keyword!(custom_sim_display);
     custom_keyword!(flip);
     custom_keyword!(get);
     custom_keyword!(hdl);
@@ -86,8 +83,6 @@ mod kw {
     custom_keyword!(input);
     custom_keyword!(instance);
     custom_keyword!(m);
-    custom_keyword!(mask_sim);
-    custom_keyword!(mask_type);
     custom_keyword!(memory);
     custom_keyword!(memory_array);
     custom_keyword!(memory_with_init);

crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs

@@ -1096,9 +1096,11 @@ impl Visitor<'_> {
                 let (#(#bindings,)*) = {
                     type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
                     let __match_value = #expr;
-                    // use method syntax to deduce what type to convert to
+                    let __match_value = {
-                    let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value)
+                        use ::fayalite::sim::value::match_sim_value::*;
-                        .__fayalite_match_sim_value();
+                        // use method syntax to deduce the correct trait to call
+                        ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value()
+                    };
                     #let_token #pat #eq_token __match_value #semi_token
                     (#(#bindings_idents,)*)
                 };
@@ -1170,9 +1172,11 @@ impl Visitor<'_> {
                 {
                     type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
                     let __match_value = #expr;
-                    // use method syntax to deduce what type to convert to
+                    let __match_value = {
-                    let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value)
+                        use ::fayalite::sim::value::match_sim_value::*;
-                        .__fayalite_match_sim_value();
+                        // use method syntax to deduce the correct trait to call
+                        ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value()
+                    };
                     #match_token __match_value {
                         #(#arms)*
                     }

crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs

@@ -95,11 +95,11 @@
 //! }
 //!
 //! #[hdl]
-//! fn destructure_inner<T: Type>(v: <MyStruct<T> as Type>::SimValue) {
+//! fn destructure_to_sim_value<'a, T: Type>(v: impl ToSimValue<Type = MyStruct<T>>) {
 //!     #[hdl(sim)]
 //!     let MyStruct::<T> {
 //!         a,
-//!         mut b,
+//!         b,
 //!         c,
 //!     } = v;
 //!
@@ -107,38 +107,5 @@
 //!     let _: SimValue<UInt<8>> = a;
 //!     let _: SimValue<Bool> = b;
 //!     let _: SimValue<T> = c;
-//!     *b = false; // can modify b since mut was used
-//! }
-//!
-//! #[hdl]
-//! fn destructure_inner_ref<'a, T: Type>(v: &'a <MyStruct<T> as Type>::SimValue) {
-//!     #[hdl(sim)]
-//!     let MyStruct::<T> {
-//!         a,
-//!         b,
-//!         c,
-//!     } = v;
-//!
-//!     // that gives these types:
-//!     let _: &'a SimValue<UInt<8>> = a;
-//!     let _: &'a SimValue<Bool> = b;
-//!     let _: &'a SimValue<T> = c;
-//! }
-//!
-//! #[hdl]
-//! fn destructure_inner_mut<'a, T: Type>(v: &'a mut <MyStruct<T> as Type>::SimValue) {
-//!     #[hdl(sim)]
-//!     let MyStruct::<T> {
-//!         a,
-//!         b,
-//!         c,
-//!     } = v;
-//!
-//!     **b = true; // you can modify v by modifying b which borrows from it
-//!
-//!     // that gives these types:
-//!     let _: &'a mut SimValue<UInt<8>> = a;
-//!     let _: &'a mut SimValue<Bool> = b;
-//!     let _: &'a mut SimValue<T> = c;
 //! }
 //! ```

crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs

@@ -72,47 +72,15 @@
 //! }
 //!
 //! #[hdl]
-//! fn match_inner_move<T: Type>(v: <MyEnum<T> as Type>::SimValue) -> String {
+//! fn match_to_sim_value<'a, T: Type>(v: impl ToSimValue<Type = MyEnum<T>>) {
 //!     #[hdl(sim)]
 //!     match v {
-//!         MyEnum::<T>::A => String::from("got A"),
+//!         MyEnum::<T>::A => println!("got A"),
-//!         MyEnum::<T>::B(mut b) => {
+//!         MyEnum::<T>::B(b) => {
 //!             let _: SimValue<Bool> = b; // b has this type
-//!             let text = format!("got B({b})");
-//!             *b = true; // can modify b since mut was used
-//!             text
-//!         }
-//!         _ => String::from("something else"),
-//!     }
-//! }
-//!
-//! #[hdl]
-//! fn match_inner_ref<'a, T: Type>(v: &'a <MyEnum<T> as Type>::SimValue) -> u32 {
-//!     #[hdl(sim)]
-//!     match v {
-//!         MyEnum::<T>::A => 1,
-//!         MyEnum::<T>::B(b) => {
-//!             let _: &'a SimValue<Bool> = b; // b has this type
 //!             println!("got B({b})");
-//!             5
 //!         }
-//!         _ => 42,
+//!         _ => println!("something else"),
-//!     }
-//! }
-//!
-//! #[hdl]
-//! fn match_inner_mut<'a, T: Type>(v: &'a mut <MyEnum<T> as Type>::SimValue) -> Option<&'a mut SimValue<T>> {
-//!     #[hdl(sim)]
-//!     match v {
-//!         MyEnum::<T>::A => None,
-//!         MyEnum::<T>::B(b) => {
-//!             println!("got B({b})");
-//!             **b = true; // you can modify v by modifying b which borrows from it
-//!             let _: &'a mut SimValue<Bool> = b; // b has this type
-//!             None
-//!         }
-//!         MyEnum::<T>::C(v) => Some(v), // you can return matched values
-//!         _ => None, // HDL enums can have invalid discriminants, so we need this extra match arm
 //!     }
 //! }
 //! ```

crates/fayalite/src/annotations.rs

@@ -238,10 +238,7 @@ impl TargetedAnnotation {
     }
     #[track_caller]
     pub fn assert_valid_target(target: Interned<Target>) {
-        assert!(
+        assert!(target.is_static(), "can't annotate non-static targets");
-            target.is_valid_annotation_target(),
-            "not a valid annotation target: {target:?}",
-        );
     }
     pub fn target(&self) -> Interned<Target> {
         self.target

crates/fayalite/src/array.rs

@@ -13,13 +13,13 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, MatchVariantWithoutScope, OpaqueSimValueSlice, OpaqueSimValueWriter,
-        OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, TypeWithDeref,
+        OpaqueSimValueWritten, StaticType, Type, TypeProperties, TypeWithDeref,
         serde_impls::SerdeCanonicalType,
     },
     util::ConstUsize,
 };
 use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error};
-use std::{borrow::Cow, fmt, iter::FusedIterator, ops::Index};
+use std::{borrow::Cow, iter::FusedIterator, ops::Index};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct ArrayType<T: Type = CanonicalType, Len: Size = DynSize> {
@@ -28,8 +28,8 @@ pub struct ArrayType<T: Type = CanonicalType, Len: Size = DynSize> {
     type_properties: TypeProperties,
 }
 
-impl<T: Type, Len: Size> fmt::Debug for ArrayType<T, Len> {
+impl<T: Type, Len: Size> std::fmt::Debug for ArrayType<T, Len> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
         write!(f, "Array<{:?}, {}>", self.element, self.len())
     }
 }
@@ -182,15 +182,6 @@ impl<T: Type + Visit<State>, Len: Size, State: Visitor + ?Sized> Visit<State>
     }
 }
 
-impl<T: Type, Len: Size> SimValueDebug for ArrayType<T, Len> {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
     type BaseType = Array;
     type MaskType = ArrayType<T::MaskType, Len>;

crates/fayalite/src/bundle.rs

@@ -14,8 +14,8 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, MatchVariantWithoutScope, OpaqueSimValue, OpaqueSimValueSize,
-        OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug,
+        OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type,
-        StaticType, Type, TypeProperties, TypeWithDeref, impl_match_variant_as_self,
+        TypeProperties, TypeWithDeref, impl_match_variant_as_self,
     },
     util::HashMap,
 };
@@ -271,15 +271,6 @@ impl Type for Bundle {
     }
 }
 
-impl SimValueDebug for Bundle {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 pub trait BundleType: Type<BaseType = Bundle> {
     type Builder: Default;
     fn fields(&self) -> Interned<[BundleField]>;
@@ -480,14 +471,6 @@ macro_rules! impl_tuples {
                 #[var($var)]
             })*]
         }
-        impl<$($T: Type,)*> SimValueDebug for ($($T,)*) {
-            fn sim_value_debug(
-                value: &<Self as Type>::SimValue,
-                f: &mut fmt::Formatter<'_>,
-            ) -> fmt::Result {
-                fmt::Debug::fmt(value, f)
-            }
-        }
         impl<$($T: Type,)*> Type for ($($T,)*) {
             type BaseType = Bundle;
             type MaskType = ($($T::MaskType,)*);
@@ -790,15 +773,6 @@ impl_tuples! {
     ]
 }
 
-impl<T: ?Sized + Send + Sync + 'static> SimValueDebug for PhantomData<T> {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     type BaseType = Bundle;
     type MaskType = ();

crates/fayalite/src/clock.rs

@@ -1,6 +1,5 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-
 use crate::{
     expr::{Expr, ValueType},
     hdl,
@@ -10,12 +9,10 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter,
-        OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties,
+        OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self,
-        impl_match_variant_as_self,
     },
 };
 use bitvec::{bits, order::Lsb0};
-use std::fmt;
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
 pub struct Clock;
@@ -72,15 +69,6 @@ impl Type for Clock {
     }
 }
 
-impl SimValueDebug for Clock {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl Clock {
     pub fn type_properties(self) -> TypeProperties {
         Self::TYPE_PROPERTIES

crates/fayalite/src/enum_.rs

@@ -2,7 +2,7 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{Expr, ToExpr, ValueType, ops::VariantAccess},
+    expr::{Expr, HdlPartialEq, HdlPartialEqImpl, ToExpr, ValueType, ops::VariantAccess},
     hdl,
     int::{Bool, UIntValue},
     intern::{Intern, Interned},
@@ -10,18 +10,18 @@ use crate::{
         EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope, connect,
         enum_match_variants_helper, incomplete_wire, wire,
     },
-    sim::value::{SimValue, ToSimValue, ToSimValueWithType},
+    sim::value::SimValue,
     source_location::SourceLocation,
     ty::{
         CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, OpaqueSimValueSize,
-        OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug,
+        OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type,
-        StaticType, Type, TypeProperties,
+        TypeProperties,
     },
     util::HashMap,
 };
 use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
 use serde::{Deserialize, Serialize};
-use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
+use std::{borrow::Cow, convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
 pub struct EnumVariant {
@@ -410,15 +410,6 @@ impl Type for Enum {
     }
 }
 
-impl SimValueDebug for Enum {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 #[derive(Clone, PartialEq, Eq, Hash, Debug, Default)]
 pub struct EnumPaddingSimValue {
     bits: Option<UIntValue>,
@@ -732,12 +723,95 @@ pub fn enum_type_to_sim_builder<T: EnumType>(v: T) -> T::SimBuilder {
     v.into()
 }
 
-#[hdl(cmp_eq)]
+#[hdl]
 pub enum HdlOption<T: Type> {
     HdlNone,
     HdlSome(T),
 }
 
+impl<Lhs: Type + HdlPartialEqImpl<Rhs>, Rhs: Type> HdlPartialEqImpl<HdlOption<Rhs>>
+    for HdlOption<Lhs>
+{
+    fn cmp_value_eq(
+        lhs: Self,
+        lhs_value: Cow<'_, Self::SimValue>,
+        rhs: HdlOption<Rhs>,
+        rhs_value: Cow<'_, <HdlOption<Rhs> as Type>::SimValue>,
+    ) -> bool {
+        type SimValueMatch<T> = <T as Type>::SimValue;
+        match (&*lhs_value, &*rhs_value) {
+            (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_)) => {
+                true
+            }
+            (SimValueMatch::<Self>::HdlSome(..), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_))
+            | (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlSome(..)) => {
+                false
+            }
+            (
+                SimValueMatch::<Self>::HdlSome(l, _),
+                SimValueMatch::<HdlOption<Rhs>>::HdlSome(r, _),
+            ) => HdlPartialEqImpl::cmp_value_eq(
+                lhs.HdlSome,
+                Cow::Borrowed(&**l),
+                rhs.HdlSome,
+                Cow::Borrowed(&**r),
+            ),
+        }
+    }
+
+    #[hdl]
+    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
+        #[hdl]
+        let cmp_eq = wire();
+        #[hdl]
+        match lhs {
+            HdlSome(lhs) =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(rhs) => connect(cmp_eq, lhs.cmp_eq(rhs)),
+                    HdlNone => connect(cmp_eq, false),
+                }
+            }
+            HdlNone =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(_) => connect(cmp_eq, false),
+                    HdlNone => connect(cmp_eq, true),
+                }
+            }
+        }
+        cmp_eq
+    }
+
+    #[hdl]
+    fn cmp_expr_ne(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
+        #[hdl]
+        let cmp_ne = wire();
+        #[hdl]
+        match lhs {
+            HdlSome(lhs) =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(rhs) => connect(cmp_ne, lhs.cmp_ne(rhs)),
+                    HdlNone => connect(cmp_ne, true),
+                }
+            }
+            HdlNone =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(_) => connect(cmp_ne, true),
+                    HdlNone => connect(cmp_ne, false),
+                }
+            }
+        }
+        cmp_ne
+    }
+}
+
 #[allow(non_snake_case)]
 pub fn HdlNone<T: StaticType>() -> Expr<HdlOption<T>> {
     HdlOption[T::TYPE].HdlNone()
@@ -749,123 +823,6 @@ pub fn HdlSome<T: Type>(value: impl ToExpr<Type = T>) -> Expr<HdlOption<T>> {
     HdlOption[value.ty()].HdlSome(value)
 }
 
-impl<T: Type> From<SimValue<HdlOption<T>>> for Option<SimValue<T>> {
-    #[hdl]
-    fn from(value: SimValue<HdlOption<T>>) -> Self {
-        #[hdl(sim)]
-        match value {
-            HdlSome(v) => Some(v),
-            HdlNone => None,
-        }
-    }
-}
-
-impl<'a, T: Type> From<&'a SimValue<HdlOption<T>>> for Option<&'a SimValue<T>> {
-    #[hdl]
-    fn from(value: &'a SimValue<HdlOption<T>>) -> Self {
-        #[hdl(sim)]
-        match value {
-            HdlSome(v) => Some(v),
-            HdlNone => None,
-        }
-    }
-}
-
-impl<'a, T: Type> From<&'a mut SimValue<HdlOption<T>>> for Option<&'a mut SimValue<T>> {
-    #[hdl]
-    fn from(value: &'a mut SimValue<HdlOption<T>>) -> Self {
-        #[hdl(sim)]
-        match value {
-            HdlSome(v) => Some(v),
-            HdlNone => None,
-        }
-    }
-}
-
-impl<T: ValueType<Type: StaticType<MaskType: StaticType>>> ValueType for Option<T> {
-    type Type = HdlOption<T::Type>;
-    type ValueCategory = T::ValueCategory;
-
-    fn ty(&self) -> Self::Type {
-        StaticType::TYPE
-    }
-}
-
-impl<T: Type, V: ToSimValueWithType<T>> ToSimValueWithType<HdlOption<T>> for Option<V> {
-    #[hdl]
-    fn to_sim_value_with_type(&self, ty: HdlOption<T>) -> SimValue<HdlOption<T>> {
-        match self {
-            Some(v) =>
-            {
-                #[hdl(sim)]
-                ty.HdlSome(v)
-            }
-            None =>
-            {
-                #[hdl(sim)]
-                ty.HdlNone()
-            }
-        }
-    }
-    #[hdl]
-    fn into_sim_value_with_type(self, ty: HdlOption<T>) -> SimValue<HdlOption<T>> {
-        match self {
-            Some(v) =>
-            {
-                #[hdl(sim)]
-                ty.HdlSome(v)
-            }
-            None =>
-            {
-                #[hdl(sim)]
-                ty.HdlNone()
-            }
-        }
-    }
-}
-
-impl<T: ToSimValue<Type: StaticType<MaskType: StaticType>>> ToSimValue for Option<T> {
-    #[hdl]
-    fn to_sim_value(&self) -> SimValue<Self::Type> {
-        match self {
-            Some(v) =>
-            {
-                #[hdl(sim)]
-                HdlSome(v)
-            }
-            None =>
-            {
-                #[hdl(sim)]
-                HdlNone()
-            }
-        }
-    }
-    #[hdl]
-    fn into_sim_value(self) -> SimValue<Self::Type> {
-        match self {
-            Some(v) =>
-            {
-                #[hdl(sim)]
-                HdlSome(v)
-            }
-            None =>
-            {
-                #[hdl(sim)]
-                HdlNone()
-            }
-        }
-    }
-}
-
-impl<T: ToExpr<Type: StaticType<MaskType: StaticType>>> ToExpr for Option<T> {
-    fn to_expr(&self) -> Expr<Self::Type> {
-        match self {
-            Some(v) => HdlSome(v),
-            None => HdlNone(),
-        }
-    }
-}
-
 impl<T: Type> HdlOption<T> {
     #[track_caller]
     pub fn try_map<R: Type, E>(

crates/fayalite/src/expr.rs

@@ -6,7 +6,6 @@ use crate::{
     bundle::{Bundle, BundleType},
     enum_::{Enum, EnumType},
     expr::target::{GetTarget, Target},
-    formal::FormalInput,
     int::{Bool, DynSize, IntType, SIntValue, Size, SizeType, UInt, UIntType, UIntValue},
     intern::{Intern, Interned},
     memory::{DynPortType, MemPort, PortType},
@@ -18,7 +17,7 @@ use crate::{
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     sim::value::{SimValue, ToSimValue, ToSimValueWithType},
-    ty::{CanonicalType, OpaqueSimValue, StaticType, TraceAsString, Type, TypeWithDeref},
+    ty::{CanonicalType, OpaqueSimValue, StaticType, Type, TypeWithDeref},
     util::{ConstBool, ConstUsize},
     wire::Wire,
 };
@@ -219,8 +218,6 @@ expr_enum! {
         SliceSInt(ops::SliceSInt),
         CastToBits(ops::CastToBits),
         CastBitsTo(ops::CastBitsTo),
-        ToTraceAsString(ops::ToTraceAsString),
-        TraceAsStringAsInner(ops::TraceAsStringAsInner),
         ModuleIO(ModuleIO<CanonicalType>),
         Instance(Instance<Bundle>),
         Wire(Wire<CanonicalType>),
@@ -228,8 +225,6 @@ expr_enum! {
         RegSync(Reg<CanonicalType, SyncReset>),
         RegAsync(Reg<CanonicalType, AsyncReset>),
         MemPort(MemPort<DynPortType>),
-        FormalInput(FormalInput),
-        SimIoForGlobal(ops::SimIoForGlobal),
     }
 }
 
@@ -394,35 +389,6 @@ impl<T: Type> Expr<T> {
             __flow: this.__flow,
         }
     }
-    #[track_caller]
-    pub fn as_trace_as_string(this: Self, ty: TraceAsString<T>) -> Expr<TraceAsString<T>> {
-        assert_eq!(this.ty(), ty.inner_ty());
-        ops::ToTraceAsString::new(Expr::canonical(this), ty).to_expr()
-    }
-}
-
-impl Expr<CanonicalType> {
-    pub fn unwrap_transparent_types(mut this: Self) -> Expr<CanonicalType> {
-        loop {
-            match this.ty() {
-                CanonicalType::UInt(_)
-                | CanonicalType::SInt(_)
-                | CanonicalType::Bool(_)
-                | CanonicalType::Array(_)
-                | CanonicalType::Enum(_)
-                | CanonicalType::Bundle(_)
-                | CanonicalType::AsyncReset(_)
-                | CanonicalType::SyncReset(_)
-                | CanonicalType::Reset(_)
-                | CanonicalType::Clock(_)
-                | CanonicalType::PhantomConst(_)
-                | CanonicalType::DynSimOnly(_) => return this,
-                CanonicalType::TraceAsString(_) => {
-                    this = *Expr::<TraceAsString>::from_canonical(this);
-                }
-            }
-        }
-    }
 }
 
 impl<T: Type> ToLiteralBits for Expr<T> {
@@ -1726,204 +1692,3 @@ impl<'a, T: Type> ToSimValueInner<'a> for &'a SimValue<T> {
         Cow::Borrowed(&**this)
     }
 }
-
-pub trait ToTraceAsString: ValueType {
-    type Output: ValueType<Type = TraceAsString<Self::Type>, ValueCategory = Self::ValueCategory>;
-    fn to_trace_as_string_with_ty(&self, ty: TraceAsString<Self::Type>) -> Self::Output;
-    fn into_trace_as_string_with_ty(self, ty: TraceAsString<Self::Type>) -> Self::Output
-    where
-        Self: Sized;
-    fn to_trace_as_string(&self) -> Self::Output;
-    fn into_trace_as_string(self) -> Self::Output
-    where
-        Self: Sized;
-}
-
-impl<
-    T: ?Sized
-        + ValueType
-        + ToTraceAsStringImpl<<Self as ValueType>::Type, <Self as ValueType>::ValueCategory>,
-> ToTraceAsString for T
-{
-    type Output = T::ImplOutput;
-    fn to_trace_as_string_with_ty(&self, ty: TraceAsString<Self::Type>) -> Self::Output {
-        Self::to_trace_as_string_with_ty_impl(self, ty)
-    }
-    fn into_trace_as_string_with_ty(self, ty: TraceAsString<Self::Type>) -> Self::Output
-    where
-        Self: Sized,
-    {
-        Self::into_trace_as_string_with_ty_impl(self, ty)
-    }
-    fn to_trace_as_string(&self) -> Self::Output {
-        Self::to_trace_as_string_impl(self)
-    }
-    fn into_trace_as_string(self) -> Self::Output
-    where
-        Self: Sized,
-    {
-        Self::into_trace_as_string_impl(self)
-    }
-}
-
-pub trait ToTraceAsStringImpl<Ty: Type, C: value_category::ValueCategory> {
-    type ImplOutput: ValueType<Type = TraceAsString<Ty>, ValueCategory = C>;
-    fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput;
-    fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput
-    where
-        Self: Sized;
-    fn to_trace_as_string_with_ty_impl(this: &Self, ty: TraceAsString<Ty>) -> Self::ImplOutput;
-    fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString<Ty>) -> Self::ImplOutput
-    where
-        Self: Sized;
-}
-
-impl<T: ?Sized + crate::sim::value::ToSimValue>
-    ToTraceAsStringImpl<T::Type, value_category::ValueCategoryValue> for T
-{
-    type ImplOutput = crate::ty::TraceAsStringSimValue<T::Type>;
-
-    fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput {
-        crate::ty::TraceAsStringSimValue::new(this)
-    }
-
-    fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        crate::ty::TraceAsStringSimValue::new(this)
-    }
-
-    fn to_trace_as_string_with_ty_impl(
-        this: &Self,
-        ty: TraceAsString<T::Type>,
-    ) -> Self::ImplOutput {
-        crate::ty::TraceAsStringSimValue::new_with_ty(this, ty)
-    }
-
-    fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString<T::Type>) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        crate::ty::TraceAsStringSimValue::new_with_ty(this, ty)
-    }
-}
-
-impl<T: ?Sized + crate::sim::value::ToSimValue>
-    ToTraceAsStringImpl<T::Type, value_category::ValueCategorySimValue> for T
-{
-    type ImplOutput = SimValue<TraceAsString<T::Type>>;
-
-    fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput {
-        crate::ty::TraceAsStringSimValue::new(this).into_sim_value()
-    }
-
-    fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        crate::ty::TraceAsStringSimValue::new(this).into_sim_value()
-    }
-
-    fn to_trace_as_string_with_ty_impl(
-        this: &Self,
-        ty: TraceAsString<T::Type>,
-    ) -> Self::ImplOutput {
-        crate::ty::TraceAsStringSimValue::new_with_ty(this, ty).into_sim_value()
-    }
-
-    fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString<T::Type>) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        crate::ty::TraceAsStringSimValue::new_with_ty(this, ty).into_sim_value()
-    }
-}
-
-impl<T: ?Sized + ToExpr> ToTraceAsStringImpl<T::Type, value_category::ValueCategoryExpr> for T {
-    type ImplOutput = Expr<TraceAsString<T::Type>>;
-
-    fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput {
-        let this = this.to_expr();
-        ops::ToTraceAsString::new(Expr::canonical(this), TraceAsString::new(this.ty())).to_expr()
-    }
-
-    fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        let this = this.to_expr();
-        ops::ToTraceAsString::new(Expr::canonical(this), TraceAsString::new(this.ty())).to_expr()
-    }
-
-    fn to_trace_as_string_with_ty_impl(
-        this: &Self,
-        ty: TraceAsString<T::Type>,
-    ) -> Self::ImplOutput {
-        let this = this.to_expr();
-        ops::ToTraceAsString::new(
-            Expr::canonical(this),
-            ty.with_new_inner_ty(this.ty().intern_sized()),
-        )
-        .to_expr()
-    }
-
-    fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString<T::Type>) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        let this = this.to_expr();
-        ops::ToTraceAsString::new(
-            Expr::canonical(this),
-            ty.with_new_inner_ty(this.ty().intern_sized()),
-        )
-        .to_expr()
-    }
-}
-
-impl<T: ?Sized + ValueType> ToTraceAsStringImpl<T::Type, value_category::ValueCategoryValueless>
-    for T
-{
-    type ImplOutput = Valueless<TraceAsString<T::Type>>;
-
-    fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput {
-        Valueless::new(TraceAsString::new(this.ty()))
-    }
-
-    fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        Valueless::new(TraceAsString::new(this.ty()))
-    }
-
-    fn to_trace_as_string_with_ty_impl(
-        this: &Self,
-        ty: TraceAsString<T::Type>,
-    ) -> Self::ImplOutput {
-        Valueless::new(ty.with_new_inner_ty(this.ty().intern_sized()))
-    }
-
-    fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString<T::Type>) -> Self::ImplOutput
-    where
-        Self: Sized,
-    {
-        Valueless::new(ty.with_new_inner_ty(this.ty().intern_sized()))
-    }
-}
-
-impl ToLiteralBits for FormalInput {
-    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
-        Err(NotALiteralExpr)
-    }
-}
-
-impl ToExpr for FormalInput {
-    fn to_expr(&self) -> Expr<Self::Type> {
-        Expr {
-            __enum: ExprEnum::FormalInput(*self).intern_sized(),
-            __ty: self.ty(),
-            __flow: self.flow(),
-        }
-    }
-}

crates/fayalite/src/expr/ops.rs

@@ -12,12 +12,10 @@ use crate::{
         ToExpr, ToLiteralBits, ToSimValueInner, ToValueless, ValueType, Valueless,
         target::{
             GetTarget, Target, TargetPathArrayElement, TargetPathBundleField,
-            TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString,
+            TargetPathDynArrayElement, TargetPathElement,
-            TargetPathTraceAsStringInner,
         },
         value_category::ValueCategoryExpr,
     },
-    formal::FormalInput,
     int::{
         Bool, BoolOrIntType, DynSize, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt,
         UIntType, UIntValue,
@@ -29,7 +27,7 @@ use crate::{
         ToSyncReset,
     },
     sim::value::{SimValue, ToSimValue},
-    ty::{CanonicalType, StaticType, TraceAsString, Type},
+    ty::{CanonicalType, StaticType, Type},
     util::ConstUsize,
 };
 use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
@@ -46,9 +44,6 @@ use std::{
     },
 };
 
-#[cfg(test)]
-mod test_ops_impls;
-
 macro_rules! make_impls {
     (
         $([$($args:tt)*])?
@@ -588,6 +583,9 @@ macro_rules! make_impls {
 #[cfg(test)]
 pub(crate) use make_impls;
 
+#[cfg(test)]
+mod test_ops_impls;
+
 macro_rules! impl_simple_binary_op_trait {
     (
         [$($LLifetimes:tt)*][$($LBounds:tt)*] ($($L:tt)*),
@@ -4696,255 +4694,3 @@ impl<This: ExprFromIterator<A>, A> FromIterator<A> for Expr<This> {
         This::expr_from_iter(iter)
     }
 }
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-pub struct ToTraceAsString<T: Type = CanonicalType> {
-    inner: Expr<CanonicalType>,
-    ty: TraceAsString<T>,
-    literal_bits: Result<Interned<BitSlice>, NotALiteralExpr>,
-    target: Option<Interned<Target>>,
-}
-
-impl<T: Type> fmt::Debug for ToTraceAsString<T> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            inner,
-            ty: _,
-            literal_bits: _,
-            target: _,
-        } = self;
-        f.debug_struct("ToTraceAsString")
-            .field("inner", inner)
-            .finish_non_exhaustive()
-    }
-}
-
-impl<T: Type> ToTraceAsString<T> {
-    pub fn new(inner: Expr<CanonicalType>, ty: TraceAsString<T>) -> Self {
-        assert_eq!(inner.ty(), ty.inner_ty().canonical());
-        let literal_bits = inner.to_literal_bits();
-        let target = inner.target().map(|base| {
-            Intern::intern_sized(
-                base.join(TargetPathElement::intern_sized(
-                    TargetPathToTraceAsString {
-                        ty: ty.canonical_trace_as_string(),
-                    }
-                    .into(),
-                ))
-                .canonicalized(),
-            )
-        });
-        Self {
-            inner,
-            ty,
-            literal_bits,
-            target,
-        }
-    }
-    pub fn inner(self) -> Expr<CanonicalType> {
-        self.inner
-    }
-}
-
-impl<T: Type> GetTarget for ToTraceAsString<T> {
-    fn target(&self) -> Option<Interned<Target>> {
-        self.target
-    }
-}
-
-impl<T: Type> ToLiteralBits for ToTraceAsString<T> {
-    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
-        self.literal_bits
-    }
-}
-
-impl<T: Type> ValueType for ToTraceAsString<T> {
-    type Type = TraceAsString<T>;
-    type ValueCategory = ValueCategoryExpr;
-
-    fn ty(&self) -> Self::Type {
-        self.ty
-    }
-}
-
-impl<T: Type> ToExpr for ToTraceAsString<T> {
-    fn to_expr(&self) -> Expr<Self::Type> {
-        Expr {
-            __enum: ExprEnum::ToTraceAsString(ToTraceAsString {
-                inner: self.inner,
-                ty: self.ty.canonical_trace_as_string(),
-                literal_bits: self.literal_bits,
-                target: self.target,
-            })
-            .intern(),
-            __ty: self.ty,
-            __flow: Expr::flow(self.inner),
-        }
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-pub struct TraceAsStringAsInner<T: Type = CanonicalType> {
-    arg: Expr<TraceAsString<CanonicalType>>,
-    ty: T,
-    literal_bits: Result<Interned<BitSlice>, NotALiteralExpr>,
-    target: Option<Interned<Target>>,
-}
-
-impl<T: Type> fmt::Debug for TraceAsStringAsInner<T> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            arg,
-            ty: _,
-            literal_bits: _,
-            target: _,
-        } = self;
-        f.debug_struct("TraceAsStringAsInner")
-            .field("arg", arg)
-            .finish_non_exhaustive()
-    }
-}
-
-impl<T: Type> TraceAsStringAsInner<T> {
-    pub fn from_arg_and_ty(arg: Expr<TraceAsString<CanonicalType>>, ty: T) -> Self {
-        assert_eq!(arg.ty().inner_ty(), ty.canonical());
-        let literal_bits = arg.to_literal_bits();
-        let target = arg.target().map(|base| {
-            Intern::intern_sized(
-                base.join(TargetPathElement::intern_sized(
-                    TargetPathTraceAsStringInner {}.into(),
-                ))
-                .canonicalized(),
-            )
-        });
-        Self {
-            arg,
-            ty,
-            literal_bits,
-            target,
-        }
-    }
-    pub fn new(arg: Expr<TraceAsString<T>>) -> Self {
-        Self::from_arg_and_ty(
-            Expr {
-                __enum: arg.__enum,
-                __ty: arg.__ty.canonical_trace_as_string(),
-                __flow: arg.__flow,
-            },
-            arg.ty().inner_ty(),
-        )
-    }
-    pub fn arg(self) -> Expr<TraceAsString<CanonicalType>> {
-        self.arg
-    }
-    pub fn arg_typed(self) -> Expr<TraceAsString<T>> {
-        Expr {
-            __enum: self.arg.__enum,
-            __ty: TraceAsString::from_canonical_trace_as_string(self.arg.__ty),
-            __flow: self.arg.__flow,
-        }
-    }
-}
-
-impl<T: Type> GetTarget for TraceAsStringAsInner<T> {
-    fn target(&self) -> Option<Interned<Target>> {
-        self.target
-    }
-}
-
-impl<T: Type> ToLiteralBits for TraceAsStringAsInner<T> {
-    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
-        self.literal_bits
-    }
-}
-
-impl<T: Type> ValueType for TraceAsStringAsInner<T> {
-    type Type = T;
-    type ValueCategory = ValueCategoryExpr;
-
-    fn ty(&self) -> Self::Type {
-        self.ty
-    }
-}
-
-impl<T: Type> ToExpr for TraceAsStringAsInner<T> {
-    fn to_expr(&self) -> Expr<Self::Type> {
-        Expr {
-            __enum: ExprEnum::TraceAsStringAsInner(TraceAsStringAsInner {
-                arg: self.arg,
-                ty: self.ty.canonical(),
-                literal_bits: self.literal_bits,
-                target: self.target,
-            })
-            .intern(),
-            __ty: self.ty,
-            __flow: Expr::flow(self.arg),
-        }
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-/// The [`Simulation::io()`] equivalent for a global signal, this is a flipped version of a global signal
-/// that allows you to e.g. use [`Simulation::write()`] to write to [`formal_global_clock()`].
-///
-/// [`Simulation::io()`]: crate::sim::Simulation::io
-/// [`Simulation::write()`]: crate::sim::Simulation::write
-/// [`formal_global_clock()`]: crate::formal::formal_global_clock
-pub struct SimIoForGlobal {
-    global: FormalInput,
-}
-
-impl fmt::Debug for SimIoForGlobal {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_tuple("SimIoForGlobal").field(&self.global).finish()
-    }
-}
-
-impl SimIoForGlobal {
-    pub fn new(global: FormalInput) -> Self {
-        Self { global }
-    }
-    pub fn global(self) -> FormalInput {
-        self.global
-    }
-    pub(crate) fn must_connect_to(self) -> bool {
-        true
-    }
-    pub fn flow(self) -> Flow {
-        self.global.flow().flip()
-    }
-    pub(crate) fn source_location(self) -> crate::source_location::SourceLocation {
-        self.global.source_location()
-    }
-}
-
-impl GetTarget for SimIoForGlobal {
-    fn target(&self) -> Option<Interned<Target>> {
-        Some(Target::from(*self).intern_sized())
-    }
-}
-
-impl ToLiteralBits for SimIoForGlobal {
-    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
-        Err(NotALiteralExpr)
-    }
-}
-
-impl ValueType for SimIoForGlobal {
-    type Type = CanonicalType;
-    type ValueCategory = ValueCategoryExpr;
-
-    fn ty(&self) -> Self::Type {
-        self.global.ty()
-    }
-}
-
-impl ToExpr for SimIoForGlobal {
-    fn to_expr(&self) -> Expr<Self::Type> {
-        Expr {
-            __enum: ExprEnum::SimIoForGlobal(*self).intern(),
-            __ty: self.ty(),
-            __flow: self.flow(),
-        }
-    }
-}

crates/fayalite/src/expr/target.rs

@@ -4,14 +4,13 @@ use crate::{
     array::Array,
     bundle::{Bundle, BundleField},
     expr::{Expr, Flow, ToExpr, ValueType, value_category::ValueCategoryExpr},
-    formal::FormalInput,
     intern::{Intern, Interned},
     memory::{DynPortType, MemPort},
     module::{Instance, ModuleIO, TargetName},
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     source_location::SourceLocation,
-    ty::{CanonicalType, TraceAsString, Type},
+    ty::{CanonicalType, Type},
     wire::Wire,
 };
 use std::fmt;
@@ -47,33 +46,11 @@ impl fmt::Display for TargetPathDynArrayElement {
     }
 }
 
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
-pub struct TargetPathTraceAsStringInner {}
-
-impl fmt::Display for TargetPathTraceAsStringInner {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, ".<inner>")
-    }
-}
-
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
-pub struct TargetPathToTraceAsString {
-    pub ty: TraceAsString<CanonicalType>,
-}
-
-impl fmt::Display for TargetPathToTraceAsString {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, ".to_trace_as_string(...)")
-    }
-}
-
 #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub enum TargetPathElement {
     BundleField(TargetPathBundleField),
     ArrayElement(TargetPathArrayElement),
     DynArrayElement(TargetPathDynArrayElement),
-    TraceAsStringInner(TargetPathTraceAsStringInner),
-    ToTraceAsString(TargetPathToTraceAsString),
 }
 
 impl From<TargetPathBundleField> for TargetPathElement {
@@ -94,26 +71,12 @@ impl From<TargetPathDynArrayElement> for TargetPathElement {
     }
 }
 
-impl From<TargetPathTraceAsStringInner> for TargetPathElement {
-    fn from(value: TargetPathTraceAsStringInner) -> Self {
-        Self::TraceAsStringInner(value)
-    }
-}
-
-impl From<TargetPathToTraceAsString> for TargetPathElement {
-    fn from(value: TargetPathToTraceAsString) -> Self {
-        Self::ToTraceAsString(value)
-    }
-}
-
 impl fmt::Display for TargetPathElement {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         match self {
             Self::BundleField(v) => v.fmt(f),
             Self::ArrayElement(v) => v.fmt(f),
             Self::DynArrayElement(v) => v.fmt(f),
-            Self::TraceAsStringInner(v) => v.fmt(f),
-            Self::ToTraceAsString(v) => v.fmt(f),
         }
     }
 }
@@ -137,15 +100,6 @@ impl TargetPathElement {
                 let parent_ty = Array::<CanonicalType>::from_canonical(parent.canonical_ty());
                 parent_ty.element()
             }
-            Self::TraceAsStringInner(_) => {
-                let parent_ty =
-                    TraceAsString::<CanonicalType>::from_canonical(parent.canonical_ty());
-                parent_ty.inner_ty()
-            }
-            &Self::ToTraceAsString(TargetPathToTraceAsString { ty }) => {
-                assert_eq!(parent.canonical_ty(), ty.inner_ty());
-                ty.canonical()
-            }
         }
     }
     pub fn flow(&self, parent: Interned<Target>) -> Flow {
@@ -157,18 +111,13 @@ impl TargetPathElement {
                     .expect("field name is known to be a valid field of parent type");
                 parent.flow().flip_if(field.flipped)
             }
-            Self::ArrayElement(_)
+            Self::ArrayElement(_) => parent.flow(),
-            | Self::DynArrayElement(_)
+            Self::DynArrayElement(_) => parent.flow(),
-            | Self::TraceAsStringInner(_)
-            | Self::ToTraceAsString(_) => parent.flow(),
         }
     }
     pub fn is_static(&self) -> bool {
         match self {
-            Self::BundleField(_)
+            Self::BundleField(_) | Self::ArrayElement(_) => true,
-            | Self::ArrayElement(_)
-            | Self::TraceAsStringInner(_)
-            | Self::ToTraceAsString(_) => true,
             Self::DynArrayElement(_) => false,
         }
     }
@@ -296,14 +245,6 @@ impl_target_base! {
         #[is = is_instance]
         #[to = instance]
         Instance(Instance<Bundle>),
-        #[from = from]
-        #[is = is_formal_input]
-        #[to = formal_input]
-        FormalInput(FormalInput),
-        #[from = from]
-        #[is = is_sim_io_for_global]
-        #[to = sim_io_for_global]
-        SimIoForGlobal(crate::expr::ops::SimIoForGlobal),
     }
 }
 
@@ -352,8 +293,6 @@ impl TargetBase {
             TargetBase::RegAsync(v) => TargetName(v.scoped_name(), None),
             TargetBase::Wire(v) => TargetName(v.scoped_name(), None),
             TargetBase::Instance(v) => TargetName(v.scoped_name(), None),
-            TargetBase::FormalInput(v) => TargetName(v.scoped_name(), None),
-            TargetBase::SimIoForGlobal(v) => TargetName(v.global().scoped_name(), None),
         }
     }
     pub fn canonical_ty(&self) -> CanonicalType {
@@ -365,21 +304,6 @@ impl TargetBase {
             TargetBase::RegAsync(v) => v.ty(),
             TargetBase::Wire(v) => v.ty(),
             TargetBase::Instance(v) => v.ty().canonical(),
-            TargetBase::FormalInput(v) => v.ty(),
-            TargetBase::SimIoForGlobal(v) => v.ty(),
-        }
-    }
-    pub fn is_valid_annotation_target(&self) -> bool {
-        match self {
-            Self::ModuleIO(_) => true,
-            Self::MemPort(_) => true,
-            Self::Reg(_) => true,
-            Self::RegSync(_) => true,
-            Self::RegAsync(_) => true,
-            Self::Wire(_) => true,
-            Self::Instance(_) => true,
-            Self::FormalInput(_) => false,
-            Self::SimIoForGlobal(_) => false,
         }
     }
 }
@@ -390,7 +314,6 @@ pub struct TargetChild {
     path_element: Interned<TargetPathElement>,
     canonical_ty: CanonicalType,
     flow: Flow,
-    canonicalized_if_different: Option<Interned<Target>>,
 }
 
 impl fmt::Debug for TargetChild {
@@ -400,7 +323,6 @@ impl fmt::Debug for TargetChild {
             path_element,
             canonical_ty: _,
             flow: _,
-            canonicalized_if_different: _,
         } = self;
         parent.fmt(f)?;
         fmt::Display::fmt(path_element, f)
@@ -414,7 +336,6 @@ impl fmt::Display for TargetChild {
             path_element,
             canonical_ty: _,
             flow: _,
-            canonicalized_if_different: _,
         } = self;
         parent.fmt(f)?;
         path_element.fmt(f)
@@ -422,69 +343,14 @@ impl fmt::Display for TargetChild {
 }
 
 impl TargetChild {
-    fn new_helper(
+    pub fn new(parent: Interned<Target>, path_element: Interned<TargetPathElement>) -> Self {
-        parent: Interned<Target>,
-        path_element: Interned<TargetPathElement>,
-        canonicalized_if_different: Option<Interned<Target>>,
-    ) -> Self {
         Self {
             parent,
             path_element,
             canonical_ty: path_element.canonical_ty(parent),
             flow: path_element.flow(parent),
-            canonicalized_if_different,
         }
     }
-    fn make_canonicalized_if_different(
-        parent: Interned<Target>,
-        path_element: Interned<TargetPathElement>,
-    ) -> Option<Interned<Target>> {
-        use TargetPathElement::*;
-        match *path_element {
-            BundleField(_) => {}
-            ArrayElement(_) => {}
-            DynArrayElement(_) => {}
-            TraceAsStringInner(_) => {
-                if let Some(child) = parent.canonicalized().child() {
-                    match *child.path_element() {
-                        BundleField(_)
-                        | ArrayElement(_)
-                        | DynArrayElement(_)
-                        | TraceAsStringInner(_) => {}
-                        ToTraceAsString(_) => return Some(child.parent()),
-                    }
-                }
-            }
-            ToTraceAsString(TargetPathToTraceAsString { ty }) => {
-                if let Some(child) = parent.canonicalized().child() {
-                    match *child.path_element() {
-                        BundleField(_) | ArrayElement(_) | DynArrayElement(_)
-                        | ToTraceAsString(_) => {}
-                        TraceAsStringInner(_) => {
-                            if ty.canonical() == child.parent().canonical_ty() {
-                                return Some(child.parent());
-                            }
-                        }
-                    }
-                }
-            }
-        }
-        Some(
-            Target::Child(Self::new_helper(
-                parent.canonicalized_if_different()?,
-                path_element,
-                None,
-            ))
-            .intern_sized(),
-        )
-    }
-    pub fn new(parent: Interned<Target>, path_element: Interned<TargetPathElement>) -> Self {
-        Self::new_helper(
-            parent,
-            path_element,
-            Self::make_canonicalized_if_different(parent, path_element),
-        )
-    }
     pub fn parent(self) -> Interned<Target> {
         self.parent
     }
@@ -497,19 +363,6 @@ impl TargetChild {
     pub fn flow(self) -> Flow {
         self.flow
     }
-    pub fn is_canonicalized(self) -> bool {
-        self.canonicalized_if_different.is_none()
-    }
-    pub fn canonicalized_if_different(self) -> Option<Interned<Target>> {
-        self.canonicalized_if_different
-    }
-    #[must_use]
-    pub fn canonicalized(self) -> Target {
-        match self.canonicalized_if_different {
-            Some(v) => *v,
-            None => Target::Child(self),
-        }
-    }
     pub fn bundle_field(self) -> Option<BundleField> {
         if let TargetPathElement::BundleField(TargetPathBundleField { name }) = *self.path_element {
             let parent_ty = Bundle::from_canonical(self.parent.canonical_ty());
@@ -574,16 +427,6 @@ impl Target {
             }
         }
     }
-    pub fn is_valid_annotation_target(&self) -> bool {
-        let mut target = self;
-        loop {
-            match target {
-                Self::Base(target_base) => return target_base.is_valid_annotation_target(),
-                Self::Child(v) if !v.path_element().is_static() => return false,
-                Self::Child(v) => target = &v.parent,
-            }
-        }
-    }
     #[must_use]
     pub fn join(&self, path_element: Interned<TargetPathElement>) -> Self {
         TargetChild::new(self.intern(), path_element).into()
@@ -600,82 +443,6 @@ impl Target {
             Target::Child(v) => v.canonical_ty(),
         }
     }
-    pub fn is_canonicalized(self) -> bool {
-        match self {
-            Self::Base(_) => true,
-            Self::Child(child) => child.is_canonicalized(),
-        }
-    }
-    pub fn canonicalized_if_different(self) -> Option<Interned<Self>> {
-        match self {
-            Self::Base(_) => None,
-            Self::Child(child) => child.canonicalized_if_different(),
-        }
-    }
-    #[must_use]
-    pub fn canonicalized(self) -> Target {
-        match self.canonicalized_if_different() {
-            Some(v) => *v,
-            None => self,
-        }
-    }
-    #[must_use]
-    pub fn canonicalized_interned(this: Interned<Target>) -> Interned<Target> {
-        this.canonicalized_if_different().unwrap_or(this)
-    }
-    #[must_use]
-    pub fn unwrap_transparent_types(mut self) -> Target {
-        loop {
-            self = self.canonicalized();
-            match self.canonical_ty() {
-                CanonicalType::UInt(_)
-                | CanonicalType::SInt(_)
-                | CanonicalType::Bool(_)
-                | CanonicalType::Array(_)
-                | CanonicalType::Enum(_)
-                | CanonicalType::Bundle(_)
-                | CanonicalType::AsyncReset(_)
-                | CanonicalType::SyncReset(_)
-                | CanonicalType::Reset(_)
-                | CanonicalType::Clock(_)
-                | CanonicalType::PhantomConst(_)
-                | CanonicalType::DynSimOnly(_) => return self,
-                CanonicalType::TraceAsString(_) => {
-                    if let Self::Child(child) = self
-                        && let TargetPathElement::ToTraceAsString(_) = *child.path_element()
-                    {
-                        self = *child.parent();
-                    } else {
-                        self = self.join(TargetPathElement::intern_sized(
-                            TargetPathTraceAsStringInner {}.into(),
-                        ));
-                    }
-                }
-            }
-        }
-    }
-    #[must_use]
-    pub fn unwrap_transparent_types_interned(this: Interned<Target>) -> Interned<Target> {
-        let retval = this.unwrap_transparent_types();
-        if retval != *this {
-            retval.intern_sized()
-        } else {
-            this
-        }
-    }
-    #[must_use]
-    pub fn without_trailing_transparent_path_elements(mut self) -> Target {
-        use TargetPathElement::*;
-        loop {
-            match self {
-                Self::Base(_) => return self,
-                Self::Child(child) => match *child.path_element() {
-                    BundleField(_) | ArrayElement(_) | DynArrayElement(_) => return self,
-                    TraceAsStringInner(_) | ToTraceAsString(_) => self = *child.parent(),
-                },
-            }
-        }
-    }
 }
 
 impl fmt::Display for Target {
@@ -700,18 +467,6 @@ pub trait GetTarget {
     fn target(&self) -> Option<Interned<Target>>;
 }
 
-impl GetTarget for Target {
-    fn target(&self) -> Option<Interned<Target>> {
-        Some(self.intern())
-    }
-}
-
-impl GetTarget for TargetBase {
-    fn target(&self) -> Option<Interned<Target>> {
-        Some(Target::Base(self.intern()).intern_sized())
-    }
-}
-
 impl GetTarget for bool {
     fn target(&self) -> Option<Interned<Target>> {
         None

crates/fayalite/src/formal.rs

@@ -1,189 +1,11 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    expr::target::{GetTarget, Target},
     int::BoolOrIntType,
-    intern::{Intern, Interned},
+    intern::{Intern, Interned, Memoize},
-    module::{NameId, NameIdOrGlobal, ScopedNameId},
     prelude::*,
 };
-use std::{fmt, sync::OnceLock};
+use std::sync::OnceLock;
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
-pub enum FormalInputKind {
-    FormalGlobalClock,
-    FormalReset,
-    AnyConst,
-    AnySeq,
-    AllConst,
-    AllSeq,
-}
-
-impl FormalInputKind {
-    pub fn fixed_ty(self) -> Option<CanonicalType> {
-        match self {
-            Self::FormalGlobalClock => Some(Clock.into()),
-            Self::FormalReset => Some(SyncReset.into()),
-            Self::AnyConst => None,
-            Self::AnySeq => None,
-            Self::AllConst => None,
-            Self::AllSeq => None,
-        }
-    }
-    pub fn fixed_id(self) -> Option<crate::module::Id> {
-        struct Cache {
-            formal_global_clock: crate::module::Id,
-            formal_reset: crate::module::Id,
-        }
-        static CACHE: OnceLock<Cache> = OnceLock::new();
-        let cache = || {
-            CACHE.get_or_init(
-                #[cold]
-                || Cache {
-                    formal_global_clock: crate::module::Id::new(),
-                    formal_reset: crate::module::Id::new(),
-                },
-            )
-        };
-        match self {
-            Self::FormalGlobalClock => Some(cache().formal_global_clock),
-            Self::FormalReset => Some(cache().formal_reset),
-            Self::AnyConst => None,
-            Self::AnySeq => None,
-            Self::AllConst => None,
-            Self::AllSeq => None,
-        }
-    }
-    pub fn fixed_source_location(self) -> Option<SourceLocation> {
-        match self {
-            Self::FormalGlobalClock | Self::FormalReset => Some(SourceLocation::builtin()),
-            Self::AnyConst | Self::AnySeq | Self::AllConst | Self::AllSeq => None,
-        }
-    }
-    pub fn name(self) -> &'static str {
-        match self {
-            Self::FormalGlobalClock => "formal_global_clock",
-            Self::FormalReset => "formal_reset",
-            Self::AnyConst => "any_const",
-            Self::AnySeq => "any_seq",
-            Self::AllConst => "all_const",
-            Self::AllSeq => "all_seq",
-        }
-    }
-    pub fn interned_name(self) -> Interned<str> {
-        macro_rules! impl_interned_name {
-            ($($variant:ident,)*) => {
-                match self {
-                    $(Self::$variant => {
-                        static CACHE: OnceLock<Interned<str>> = OnceLock::new();
-                        *CACHE.get_or_init(|| Self::$variant.name().intern())
-                    })*
-                }
-            };
-        }
-        impl_interned_name! {
-            FormalGlobalClock,
-            FormalReset,
-            AnyConst,
-            AnySeq,
-            AllConst,
-            AllSeq,
-        }
-    }
-}
-
-#[derive(Clone, PartialEq, Eq, Hash)]
-struct FormalInputData {
-    kind: FormalInputKind,
-    name_id: NameId,
-    ty: CanonicalType,
-    source_location: SourceLocation,
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-pub struct FormalInput(Interned<FormalInputData>);
-
-impl fmt::Debug for FormalInput {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        if self.kind().fixed_ty().is_some() {
-            f.write_str(&self.name())
-        } else {
-            f.debug_tuple(&self.name()).field(&self.0.ty).finish()
-        }
-    }
-}
-
-impl FormalInput {
-    #[track_caller]
-    pub fn new(
-        kind: FormalInputKind,
-        name_id: NameId,
-        ty: CanonicalType,
-        source_location: SourceLocation,
-    ) -> Self {
-        let NameId(name, id) = name_id;
-        assert_eq!(kind.interned_name(), name);
-        if let Some(fixed_ty) = kind.fixed_ty() {
-            assert_eq!(ty, fixed_ty);
-        } else {
-            assert!(
-                ty.is_castable_from_bits(),
-                "{name} type must be castable from bits. got:\n{ty:#?}",
-            );
-        }
-        if let Some(fixed_source_location) = kind.fixed_source_location() {
-            assert_eq!(source_location, fixed_source_location);
-        }
-        if let Some(fixed_id) = kind.fixed_id() {
-            assert_eq!(id, fixed_id);
-        }
-        Self(
-            FormalInputData {
-                kind,
-                name_id,
-                ty,
-                source_location,
-            }
-            .intern_sized(),
-        )
-    }
-    pub fn kind(self) -> FormalInputKind {
-        self.0.kind
-    }
-    pub fn name(self) -> Interned<str> {
-        self.0.name_id.0
-    }
-    pub fn name_id(self) -> NameId {
-        self.0.name_id
-    }
-    pub fn scoped_name(self) -> ScopedNameId {
-        ScopedNameId(NameIdOrGlobal::Global, self.name_id())
-    }
-    pub fn source_location(self) -> SourceLocation {
-        self.0.source_location
-    }
-    pub(crate) fn must_connect_to(self) -> bool {
-        false
-    }
-    pub(crate) fn flow(self) -> crate::expr::Flow {
-        crate::expr::Flow::Source
-    }
-}
-
-impl ValueType for FormalInput {
-    type Type = CanonicalType;
-    type ValueCategory = crate::expr::value_category::ValueCategoryExpr;
-
-    fn ty(&self) -> Self::Type {
-        self.0.ty
-    }
-}
-
-impl GetTarget for FormalInput {
-    fn target(&self) -> Option<Interned<Target>> {
-        Some(Target::from(*self).intern_sized())
-    }
-}
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
 pub enum FormalKind {
@@ -316,76 +138,110 @@ make_formal!(
     hdl_cover
 );
 
+pub trait MakeFormalExpr: Type {}
+
+impl<T: Type> MakeFormalExpr for T {}
+
 #[hdl]
 pub fn formal_global_clock() -> Expr<Clock> {
-    static CACHE: OnceLock<Expr<Clock>> = OnceLock::new();
+    #[hdl_module(extern)]
-    *CACHE.get_or_init(|| {
+    fn formal_global_clock() {
-        let kind = FormalInputKind::FormalGlobalClock;
+        #[hdl]
-        Expr::from_canonical(
+        let clk: Clock = m.output();
-            FormalInput::new(
+        m.annotate_module(BlackBoxInlineAnnotation {
-                kind,
+            path: "fayalite_formal_global_clock.v".intern(),
-                NameId(
+            text: r"module __fayalite_formal_global_clock(output clk);
-                    kind.interned_name(),
+    (* gclk *)
-                    kind.fixed_id().expect("known to have a fixed Id"),
+    reg clk;
-                ),
+endmodule
-                Clock.into(),
+"
-                kind.fixed_source_location()
+            .intern(),
-                    .expect("known to have a fixed SourceLocation"),
+        });
-            )
+        m.verilog_name("__fayalite_formal_global_clock");
-            .to_expr(),
+    }
-        )
+    #[hdl]
-    })
+    let formal_global_clock = instance(formal_global_clock());
+    formal_global_clock.clk
 }
 
 #[hdl]
 pub fn formal_reset() -> Expr<SyncReset> {
-    static CACHE: OnceLock<Expr<SyncReset>> = OnceLock::new();
+    #[hdl_module(extern)]
-    *CACHE.get_or_init(|| {
+    fn formal_reset() {
-        let kind = FormalInputKind::FormalReset;
+        #[hdl]
-        Expr::from_canonical(
+        let rst: SyncReset = m.output();
-            FormalInput::new(
+        m.annotate_module(BlackBoxInlineAnnotation {
-                kind,
+            path: "fayalite_formal_reset.v".intern(),
-                NameId(
+            text: r"module __fayalite_formal_reset(output rst);
-                    kind.interned_name(),
+    assign rst = $initstate;
-                    kind.fixed_id().expect("known to have a fixed Id"),
+endmodule
-                ),
+"
-                SyncReset.into(),
+            .intern(),
-                kind.fixed_source_location()
+        });
-                    .expect("known to have a fixed SourceLocation"),
+        m.verilog_name("__fayalite_formal_reset");
-            )
+    }
-            .to_expr(),
+    static MOD: OnceLock<Interned<Module<formal_reset>>> = OnceLock::new();
-        )
+    #[hdl]
-    })
+    let formal_reset = instance(*MOD.get_or_init(formal_reset));
+    formal_reset.rst
 }
 
 macro_rules! make_any_const_fn {
-    ($ident:ident, $ident_with_loc:ident, $verilog_attribute:literal, $kind:ident) => {
+    ($ident:ident, $verilog_attribute:literal) => {
-        #[track_caller]
         #[hdl]
         pub fn $ident<T: BoolOrIntType>(ty: T) -> Expr<T> {
-            $ident_with_loc(ty, SourceLocation::caller())
+            #[hdl_module(extern)]
-        }
+            pub(super) fn $ident<T: BoolOrIntType>(ty: T) {
-        #[track_caller]
+                #[hdl]
-        #[hdl]
+                let out: T = m.output(ty);
-        pub fn $ident_with_loc<T: BoolOrIntType>(
+                let width = ty.width();
-            ty: T,
+                let verilog_bitslice = if width == 1 {
-            source_location: SourceLocation,
+                    String::new()
-        ) -> Expr<T> {
+                } else {
-            let kind = FormalInputKind::$kind;
+                    format!(" [{}:0]", width - 1)
-            Expr::from_canonical(
+                };
-                FormalInput::new(
+                m.annotate_module(BlackBoxInlineAnnotation {
-                    kind,
+                    path: Intern::intern_owned(format!(
-                    NameId(kind.interned_name(), crate::module::Id::new()),
+                        "fayalite_{}_{width}.v",
-                    ty.canonical(),
+                        stringify!($ident),
-                    source_location,
+                    )),
-                )
+                    text: Intern::intern_owned(format!(
-                .to_expr(),
+                        r"module __fayalite_{}_{width}(output{verilog_bitslice} out);
-            )
+    (* {} *)
+    reg{verilog_bitslice} out;
+endmodule
+",
+                        stringify!($ident),
+                        $verilog_attribute,
+                    )),
+                });
+                m.verilog_name(format!("__fayalite_{}_{width}", stringify!($ident)));
+            }
+            #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+            struct TheMemoize<T>(T);
+            impl<T: BoolOrIntType> Memoize for TheMemoize<T> {
+                type Input = ();
+                type InputOwned = ();
+                type Output = Option<Interned<Module<$ident<T>>>>;
+                fn inner(self, _input: &Self::Input) -> Self::Output {
+                    if self.0.width() == 0 {
+                        None
+                    } else {
+                        Some($ident(self.0))
+                    }
+                }
+            }
+            let Some(module) = TheMemoize(ty).get_owned(()) else {
+                return 0_hdl_u0.cast_bits_to(ty);
+            };
+            #[hdl]
+            let $ident = instance(module);
+            $ident.out
         }
     };
 }
 
-make_any_const_fn!(any_const, any_const_with_loc, "anyconst", AnyConst);
+make_any_const_fn!(any_const, "anyconst");
-make_any_const_fn!(any_seq, any_seq_with_loc, "anyseq", AnySeq);
+make_any_const_fn!(any_seq, "anyseq");
-make_any_const_fn!(all_const, all_const_with_loc, "allconst", AllConst);
+make_any_const_fn!(all_const, "allconst");
-make_any_const_fn!(all_seq, all_seq_with_loc, "allseq", AllSeq);
+make_any_const_fn!(all_seq, "allseq");

crates/fayalite/src/int.rs

@@ -15,8 +15,8 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, FillInDefaultedGenerics, OpaqueSimValueSize, OpaqueSimValueSlice,
-        OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, SimValueDisplay, StaticType,
+        OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, TypeProperties,
-        Type, TypeProperties, impl_match_variant_as_self,
+        impl_match_variant_as_self,
     },
     util::{ConstBool, ConstUsize, GenericConstBool, GenericConstUsize, interned_bit, slice_range},
 };
@@ -1019,24 +1019,6 @@ macro_rules! impl_int {
             }
         }
 
-        impl<Width: Size> SimValueDebug for $name<Width> {
-            fn sim_value_debug(
-                value: &<Self as Type>::SimValue,
-                f: &mut fmt::Formatter<'_>,
-            ) -> fmt::Result {
-                fmt::Debug::fmt(value, f)
-            }
-        }
-
-        impl<Width: Size> SimValueDisplay for $name<Width> {
-            fn sim_value_display(
-                value: &<Self as Type>::SimValue,
-                f: &mut fmt::Formatter<'_>,
-            ) -> fmt::Result {
-                fmt::Display::fmt(value, f)
-            }
-        }
-
         impl<Width: KnownSize> Default for $name<Width> {
             fn default() -> Self {
                 Self::TYPE
@@ -1277,9 +1259,6 @@ macro_rules! impl_int {
             pub fn bitvec_mut(&mut self) -> &mut BitVec {
                 Arc::make_mut(&mut self.bits)
             }
-            pub fn arc_bitvec_mut(&mut self) -> &mut Arc<BitVec> {
-                &mut self.bits
-            }
         }
     };
 }
@@ -1920,15 +1899,6 @@ impl Type for Bool {
     }
 }
 
-impl SimValueDebug for Bool {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl StaticType for Bool {
     const TYPE: Self = Bool;
     const MASK_TYPE: Self::MaskType = Bool;

crates/fayalite/src/int/uint_in_range.rs

@@ -14,7 +14,7 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten,
-        SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self,
+        StaticType, Type, TypeProperties, impl_match_variant_as_self,
     },
 };
 use bitvec::{order::Lsb0, view::BitView};
@@ -94,15 +94,6 @@ impl Type for UIntInRangeMaskType {
     }
 }
 
-impl SimValueDebug for UIntInRangeMaskType {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl BundleType for UIntInRangeMaskType {
     type Builder = NoBuilder;
 
@@ -348,15 +339,6 @@ macro_rules! define_uint_in_range_type {
             }
         }
 
-        impl<Start: Size, End: Size> SimValueDebug for $UIntInRangeType<Start, End> {
-            fn sim_value_debug(
-                value: &<Self as Type>::SimValue,
-                f: &mut fmt::Formatter<'_>,
-            ) -> fmt::Result {
-                fmt::Debug::fmt(value, f)
-            }
-        }
-
         impl<Start: Size, End: Size> fmt::Debug for $UIntInRangeType<Start, End> {
             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
                 let Self { value, range } = self;

crates/fayalite/src/intern.rs

@@ -682,62 +682,27 @@ impl<T: ?Sized + 'static + Send + Sync + AsRef<U>, U: ?Sized> AsRef<U> for Inter
 
 #[derive(Clone, Debug)]
 pub struct InternedSliceIter<T: Clone + 'static + Send + Sync> {
-    iter: std::iter::Cloned<std::slice::Iter<'static, T>>,
+    slice: Interned<[T]>,
-}
+    index: std::ops::Range<usize>,
-
-impl<T: Clone + 'static + Send + Sync> Default for InternedSliceIter<T> {
-    fn default() -> Self {
-        Self {
-            iter: [].iter().cloned(),
-        }
-    }
 }
 
 impl<T: Clone + 'static + Send + Sync> Iterator for InternedSliceIter<T> {
     type Item = T;
 
     fn next(&mut self) -> Option<Self::Item> {
-        self.iter.next()
+        self.index.next().map(|index| self.slice[index].clone())
     }
 
     fn size_hint(&self) -> (usize, Option<usize>) {
-        self.iter.size_hint()
+        self.index.size_hint()
-    }
-
-    fn count(self) -> usize {
-        self.iter.count()
-    }
-
-    fn last(mut self) -> Option<Self::Item> {
-        self.next_back()
-    }
-
-    fn nth(&mut self, n: usize) -> Option<Self::Item> {
-        self.iter.nth(n)
-    }
-
-    fn fold<B, F>(self, init: B, f: F) -> B
-    where
-        F: FnMut(B, Self::Item) -> B,
-    {
-        self.iter.fold(init, f)
     }
 }
 
 impl<T: Clone + 'static + Send + Sync> DoubleEndedIterator for InternedSliceIter<T> {
     fn next_back(&mut self) -> Option<Self::Item> {
-        self.iter.next_back()
+        self.index
-    }
+            .next_back()
-
+            .map(|index| self.slice[index].clone())
-    fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
-        self.iter.nth_back(n)
-    }
-
-    fn rfold<B, F>(self, init: B, f: F) -> B
-    where
-        F: FnMut(B, Self::Item) -> B,
-    {
-        self.iter.rfold(init, f)
     }
 }
 
@@ -751,7 +716,8 @@ impl<T: Clone + 'static + Send + Sync> IntoIterator for Interned<[T]> {
 
     fn into_iter(self) -> Self::IntoIter {
         InternedSliceIter {
-            iter: Interned::into_inner(self).iter().cloned(),
+            index: 0..self.len(),
+            slice: self,
         }
     }
 }

crates/fayalite/src/memory.rs

@@ -1093,7 +1093,6 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
             .to_expr(),
         )),
         CanonicalType::PhantomConst(_) => Expr::from_canonical(Expr::canonical(().to_expr())),
-        CanonicalType::TraceAsString(ty) => Expr::from_canonical(splat_mask(ty.inner_ty(), value)),
     }
 }
 

crates/fayalite/src/module.rs

@@ -8,7 +8,7 @@ use crate::{
     clock::{Clock, ClockDomain},
     enum_::{Enum, EnumMatchVariantsIter, EnumType},
     expr::{
-        Expr, ExprEnum, Flow, ToExpr, ValueType,
+        Expr, Flow, ToExpr, ValueType,
         ops::VariantAccess,
         target::{
             GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField,
@@ -20,7 +20,6 @@ use crate::{
     int::{Bool, DynSize, Size},
     intern::{Intern, Interned},
     memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
-    module::transform::visit::{Visit, Visitor},
     platform::PlatformIOBuilder,
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
@@ -727,57 +726,7 @@ impl fmt::Display for NameId {
 }
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub enum NameIdOrGlobal {
+pub struct ScopedNameId(pub NameId, pub NameId);
-    Global,
-    NameId(NameId),
-}
-
-impl NameIdOrGlobal {
-    pub fn name_id(self) -> Option<NameId> {
-        match self {
-            Self::Global => None,
-            Self::NameId(v) => Some(v),
-        }
-    }
-    #[track_caller]
-    pub fn assert_is_name_id(self) {
-        match self {
-            Self::Global => panic!("expected a NameId, got NameIdOrGlobal::Global"),
-            Self::NameId(_) => {}
-        }
-    }
-    #[track_caller]
-    pub fn unwrap_name_id(self) -> NameId {
-        match self {
-            Self::Global => panic!("expected a NameId, got NameIdOrGlobal::Global"),
-            Self::NameId(v) => v,
-        }
-    }
-}
-
-impl fmt::Debug for NameIdOrGlobal {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        fmt::Display::fmt(self, f)
-    }
-}
-
-impl fmt::Display for NameIdOrGlobal {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        match self {
-            Self::Global => f.write_str("<<Global>>"),
-            Self::NameId(name_id) => fmt::Display::fmt(name_id, f),
-        }
-    }
-}
-
-impl From<NameId> for NameIdOrGlobal {
-    fn from(value: NameId) -> Self {
-        Self::NameId(value)
-    }
-}
-
-#[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub struct ScopedNameId(pub NameIdOrGlobal, pub NameId);
 
 impl fmt::Debug for ScopedNameId {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
@@ -855,7 +804,7 @@ impl<T: BundleType> Instance<T> {
         self.containing_module_name_id().0
     }
     pub fn containing_module_name_id(self) -> NameId {
-        self.scoped_name.0.unwrap_name_id()
+        self.scoped_name.0
     }
     pub fn name(self) -> Interned<str> {
         self.name_id().0
@@ -872,13 +821,11 @@ impl<T: BundleType> Instance<T> {
     pub fn source_location(self) -> SourceLocation {
         self.source_location
     }
-    #[track_caller]
     pub fn new_unchecked(
         scoped_name: ScopedNameId,
         instantiated: Interned<Module<T>>,
         source_location: SourceLocation,
     ) -> Self {
-        scoped_name.0.assert_is_name_id();
         Self {
             scoped_name,
             instantiated,
@@ -1164,10 +1111,7 @@ fn validate_clock_for_past<S: ModuleBuildingStatus>(
             let mut target = clock_for_past;
             while let Target::Child(child) = target {
                 match *child.path_element() {
-                    TargetPathElement::BundleField(_)
+                    TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {}
-                    | TargetPathElement::ArrayElement(_)
-                    | TargetPathElement::ToTraceAsString(_)
-                    | TargetPathElement::TraceAsStringInner(_) => {}
                     TargetPathElement::DynArrayElement(_) => {
                         panic!(
                             "clock_for_past: clock must be a static target (you can't use `Expr<UInt>` array indexes):\n{clock_for_past:?}"
@@ -1591,7 +1535,6 @@ impl TargetState {
         }
     }
     fn new(target: Interned<Target>, declared_in_block: usize) -> Self {
-        let target = Target::unwrap_transparent_types_interned(target);
         Self {
             target,
             inner: match target.canonical_ty() {
@@ -1643,71 +1586,17 @@ impl TargetState {
                     declared_in_block,
                     written_in_blocks: RefCell::default(),
                 },
-                CanonicalType::TraceAsString(_) => {
-                    unreachable!("handled by Target::unwrap_transparent_types_interned")
-                }
             },
         }
     }
 }
 
-struct VisibleExprsStack {
-    buf: Vec<HashSet<ExprEnum>>,
-    len: usize,
-}
-
-impl VisibleExprsStack {
-    fn top(&mut self) -> &mut HashSet<ExprEnum> {
-        &mut self.buf[self.len - 1]
-    }
-    fn slice(&self) -> &[HashSet<ExprEnum>] {
-        &self.buf[..self.len]
-    }
-    fn contains(&self, v: &ExprEnum) -> bool {
-        self.slice().iter().any(|i| i.contains(v))
-    }
-    fn push_empty(&mut self) {
-        #[cold]
-        fn push_empty_cold(stack: &mut VisibleExprsStack) {
-            stack.buf.push(HashSet::default());
-            assert_eq!(stack.buf.len(), stack.len)
-        }
-        self.len += 1;
-        if self.len > self.buf.len() {
-            push_empty_cold(self)
-        }
-    }
-    fn pop(&mut self) {
-        let Some(new_len) = self.len.checked_sub(1) else {
-            unreachable!("visible exprs stack underflow");
-        };
-        self.buf[new_len].clear();
-        self.len = new_len;
-    }
-}
-
-impl Default for VisibleExprsStack {
-    fn default() -> Self {
-        Self {
-            buf: Vec::new(),
-            len: 0,
-        }
-    }
-}
-
 struct AssertValidityState {
     module: Module<Bundle>,
     blocks: Vec<Block>,
-    visible_exprs: VisibleExprsStack,
     target_states: HashMap<Interned<TargetBase>, TargetState>,
 }
 
-enum GetTargetStatesError {
-    NotFound,
-    IsGlobal,
-    FoundSimIoForGlobal(crate::expr::ops::SimIoForGlobal),
-}
-
 impl AssertValidityState {
     fn make_block_index(&mut self, block: Block) -> usize {
         let retval = self.blocks.len();
@@ -1716,79 +1605,48 @@ impl AssertValidityState {
     }
     fn get_target_states<'a>(
         &'a self,
-        target: Target,
+        target: &Target,
         process_target_state: &dyn Fn(&'a TargetState, bool),
-    ) -> Result<(), GetTargetStatesError> {
+    ) -> Result<(), ()> {
-        let mut target = target.unwrap_transparent_types();
+        match target {
-        loop {
+            Target::Base(target_base) => {
-            break match target {
+                let target_state = self.get_base_state(*target_base)?;
-                Target::Base(target_base) => {
+                process_target_state(target_state, false);
-                    let target_state = self.get_base_state(target_base)?;
+                Ok(())
-                    process_target_state(target_state, false);
+            }
-                    Ok(())
+            Target::Child(target_child) => self.get_target_states(
-                }
+                &target_child.parent(),
-                Target::Child(target_child) => match *target_child.path_element() {
+                &|target_state, exact_target_unknown| {
-                    TargetPathElement::BundleField(_)
+                    let TargetStateInner::Decomposed { subtargets } = &target_state.inner else {
-                    | TargetPathElement::ArrayElement(_)
+                        unreachable!(
-                    | TargetPathElement::DynArrayElement(_) => self.get_target_states(
+                            "TargetState::new makes TargetState tree match the Target type"
-                        *target_child.parent(),
+                        );
-                        &|target_state, exact_target_unknown| {
+                    };
-                            let TargetStateInner::Decomposed { subtargets } = &target_state.inner
+                    match *target_child.path_element() {
-                            else {
+                        TargetPathElement::BundleField(_) => process_target_state(
-                                unreachable!(
+                            subtargets
-                                    "TargetState::new makes TargetState tree match the Target type"
+                                .get(&target_child.path_element())
-                                );
+                                .expect("bundle fields filled in by TargetState::new"),
-                            };
+                            exact_target_unknown,
-                            match *target_child.path_element() {
+                        ),
-                                TargetPathElement::BundleField(_) => process_target_state(
+                        TargetPathElement::ArrayElement(_) => process_target_state(
-                                    subtargets
+                            subtargets
-                                        .get(&target_child.path_element())
+                                .get(&target_child.path_element())
-                                        .expect("bundle fields filled in by TargetState::new"),
+                                .expect("array elements filled in by TargetState::new"),
-                                    exact_target_unknown,
+                            exact_target_unknown,
-                                ),
+                        ),
-                                TargetPathElement::ArrayElement(_) => process_target_state(
+                        TargetPathElement::DynArrayElement(_) => {
-                                    subtargets
+                            for target_state in subtargets.values() {
-                                        .get(&target_child.path_element())
+                                process_target_state(target_state, true);
-                                        .expect("array elements filled in by TargetState::new"),
-                                    exact_target_unknown,
-                                ),
-                                TargetPathElement::DynArrayElement(_) => {
-                                    for target_state in subtargets.values() {
-                                        process_target_state(target_state, true);
-                                    }
-                                }
-                                TargetPathElement::TraceAsStringInner(_)
-                                | TargetPathElement::ToTraceAsString(_) => unreachable!(),
                             }
-                        },
+                        }
-                    ),
-                    TargetPathElement::TraceAsStringInner(_)
-                    | TargetPathElement::ToTraceAsString(_) => {
-                        target = *target_child.parent();
-                        continue;
                     }
                 },
-            };
+            ),
         }
     }
-    fn get_base_state(
+    fn get_base_state(&self, target_base: Interned<TargetBase>) -> Result<&TargetState, ()> {
-        &self,
+        self.target_states.get(&target_base).ok_or(())
-        target_base: Interned<TargetBase>,
-    ) -> Result<&TargetState, GetTargetStatesError> {
-        match *target_base {
-            TargetBase::ModuleIO(_)
-            | TargetBase::MemPort(_)
-            | TargetBase::Reg(_)
-            | TargetBase::RegSync(_)
-            | TargetBase::RegAsync(_)
-            | TargetBase::Wire(_)
-            | TargetBase::Instance(_) => self
-                .target_states
-                .get(&target_base)
-                .ok_or(GetTargetStatesError::NotFound),
-            TargetBase::FormalInput(_) => Err(GetTargetStatesError::IsGlobal),
-            TargetBase::SimIoForGlobal(v) => Err(GetTargetStatesError::FoundSimIoForGlobal(v)),
-        }
     }
     #[track_caller]
     fn insert_new_base(&mut self, target_base: Interned<TargetBase>, declared_in_block: usize) {
@@ -1835,7 +1693,6 @@ impl AssertValidityState {
                         &TargetPathElement::BundleField(_) => {
                             let field = sub_target_state
                                 .target
-                                .without_trailing_transparent_path_elements()
                                 .child()
                                 .expect("known to be a child")
                                 .bundle_field()
@@ -1859,8 +1716,6 @@ impl AssertValidityState {
                         TargetPathElement::DynArrayElement { .. } => {
                             Self::set_connect_target_written(sub_target_state, is_lhs, block, true);
                         }
-                        TargetPathElement::TraceAsStringInner(_)
-                        | TargetPathElement::ToTraceAsString(_) => unreachable!("never added"),
                     }
                 }
             }
@@ -1878,33 +1733,19 @@ impl AssertValidityState {
             debug_assert!(!is_lhs, "the ModuleBuilder asserts lhs.target().is_some()");
             return;
         };
-        let result = self.get_target_states(*target, &|target_state, exact_target_unknown| {
+        let result = self.get_target_states(&target, &|target_state, exact_target_unknown| {
             Self::set_connect_target_written(target_state, is_lhs, block, exact_target_unknown);
         });
-        match result {
+        if result.is_err() {
-            Ok(()) => {}
+            if is_lhs {
-            Err(GetTargetStatesError::NotFound) => {
+                panic!("at {source_location}: tried to connect to not-yet-defined item: {target}");
-                if is_lhs {
+            } else {
-                    panic!(
-                        "at {source_location}: tried to connect to not-yet-defined item: {target}"
-                    );
-                } else {
-                    panic!(
-                        "at {source_location}: tried to connect from not-yet-defined item: {target}"
-                    );
-                }
-            }
-            Err(GetTargetStatesError::IsGlobal) => {
-                // no error
-            }
-            Err(GetTargetStatesError::FoundSimIoForGlobal(v)) => {
                 panic!(
-                    "at {source_location}: fayalite::expr::ops::SimIoForGlobal is not allowed in Modules: {v:?}"
+                    "at {source_location}: tried to connect from not-yet-defined item: {target}"
-                )
+                );
             }
         }
     }
-    #[track_caller]
     fn process_conditional_sub_blocks(
         &mut self,
         parent_block: usize,
@@ -1918,40 +1759,17 @@ impl AssertValidityState {
         }
     }
     #[track_caller]
-    fn assert_expr_validity<T: Type>(&mut self, expr: Expr<T>, source_location: SourceLocation) {
-        let mut visitor = AssertExprValidity { state: self };
-        match visitor.visit_expr(&expr) {
-            Ok(()) => {}
-            Err(e) => match e {
-                InvalidExpr::ExprIsNotVisible(expr) => {
-                    if let Some(target) = expr.target() {
-                        panic!(
-                            "at {source_location}: expression isn't visible here, it's defined:\n\
-                            at {}: {expr:?}",
-                            target.base().source_location(),
-                        );
-                    } else {
-                        panic!("at {source_location}: expression isn't visible here: {expr:?}");
-                    }
-                }
-            },
-        }
-    }
-    #[track_caller]
     fn assert_subtree_validity(&mut self, block: usize) {
-        self.visible_exprs.push_empty();
         let module = self.module;
         if block == 0 {
             for module_io in &*module.module_io {
                 self.insert_new_base(TargetBase::intern_sized(module_io.module_io.into()), block);
-                self.visible_exprs.top().insert(module_io.module_io.into());
             }
         }
         let Block { memories, stmts } = self.blocks[block];
         for m in memories {
             for port in m.ports() {
                 self.insert_new_base(TargetBase::intern_sized(port.into()), block);
-                self.visible_exprs.top().insert(port.into());
             }
         }
         for stmt in stmts {
@@ -1965,104 +1783,44 @@ impl AssertValidityState {
                     } = connect;
                     self.set_connect_side_written(lhs, source_location, true, block);
                     self.set_connect_side_written(rhs, source_location, false, block);
-                    self.assert_expr_validity(lhs, source_location);
-                    self.assert_expr_validity(rhs, source_location);
-                }
-                Stmt::Formal(formal) => {
-                    let StmtFormal {
-                        kind: _,
-                        clk,
-                        pred,
-                        en,
-                        text: _,
-                        source_location,
-                    } = formal;
-                    self.assert_expr_validity(clk, source_location);
-                    self.assert_expr_validity(pred, source_location);
-                    self.assert_expr_validity(en, source_location);
                 }
+                Stmt::Formal(_) => {}
                 Stmt::If(if_stmt) => {
-                    let StmtIf {
+                    let sub_blocks = if_stmt.blocks.map(|block| self.make_block_index(block));
-                        cond,
-                        source_location,
-                        blocks: sub_blocks,
-                    } = if_stmt;
-                    self.assert_expr_validity(cond, source_location);
-                    let sub_blocks = sub_blocks.map(|block| self.make_block_index(block));
                     self.process_conditional_sub_blocks(block, sub_blocks)
                 }
                 Stmt::Match(match_stmt) => {
                     match_stmt.assert_validity();
-                    let StmtMatch {
-                        expr,
-                        source_location,
-                        blocks: sub_blocks,
-                    } = match_stmt;
-                    self.assert_expr_validity(expr, source_location);
                     let sub_blocks = Vec::from_iter(
-                        sub_blocks
+                        match_stmt
+                            .blocks
                             .into_iter()
                             .map(|block| self.make_block_index(block)),
                     );
-                    self.visible_exprs.push_empty();
+                    self.process_conditional_sub_blocks(block, sub_blocks.iter().copied())
-                    let visible_exprs_top = self.visible_exprs.top();
-                    for variant_index in 0..expr.ty().variants().len() {
-                        visible_exprs_top
-                            .insert(<VariantAccess>::new_by_index(expr, variant_index).into());
-                    }
-                    self.process_conditional_sub_blocks(block, sub_blocks.iter().copied());
-                    self.visible_exprs.pop();
                 }
                 Stmt::Declaration(StmtDeclaration::Wire(StmtWire {
                     annotations: _,
                     wire,
-                })) => {
+                })) => self.insert_new_base(TargetBase::intern_sized(wire.into()), block),
-                    self.insert_new_base(TargetBase::intern_sized(wire.into()), block);
-                    self.visible_exprs.top().insert(wire.into());
-                }
                 Stmt::Declaration(StmtDeclaration::Reg(StmtReg {
                     annotations: _,
                     reg,
-                })) => {
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
-                    self.assert_expr_validity(reg.clock_domain(), reg.source_location());
-                    if let Some(init) = reg.init() {
-                        self.assert_expr_validity(init, reg.source_location());
-                    }
-                    self.insert_new_base(TargetBase::intern_sized(reg.into()), block);
-                    self.visible_exprs.top().insert(reg.into());
-                }
                 Stmt::Declaration(StmtDeclaration::RegSync(StmtReg {
                     annotations: _,
                     reg,
-                })) => {
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
-                    self.assert_expr_validity(reg.clock_domain(), reg.source_location());
-                    if let Some(init) = reg.init() {
-                        self.assert_expr_validity(init, reg.source_location());
-                    }
-                    self.insert_new_base(TargetBase::intern_sized(reg.into()), block);
-                    self.visible_exprs.top().insert(reg.into());
-                }
                 Stmt::Declaration(StmtDeclaration::RegAsync(StmtReg {
                     annotations: _,
                     reg,
-                })) => {
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
-                    self.assert_expr_validity(reg.clock_domain(), reg.source_location());
-                    if let Some(init) = reg.init() {
-                        self.assert_expr_validity(init, reg.source_location());
-                    }
-                    self.insert_new_base(TargetBase::intern_sized(reg.into()), block);
-                    self.visible_exprs.top().insert(reg.into());
-                }
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations: _,
                     instance,
-                })) => {
+                })) => self.insert_new_base(TargetBase::intern_sized(instance.into()), block),
-                    self.insert_new_base(TargetBase::intern_sized(instance.into()), block);
-                    self.visible_exprs.top().insert(instance.into());
-                }
             }
         }
-        self.visible_exprs.pop();
     }
     #[track_caller]
     fn assert_validity(&mut self) {
@@ -2091,142 +1849,6 @@ impl AssertValidityState {
     }
 }
 
-struct AssertExprValidity<'a> {
-    state: &'a mut AssertValidityState,
-}
-
-enum InvalidExpr {
-    ExprIsNotVisible(Expr<CanonicalType>),
-}
-
-impl transform::visit::Visitor for AssertExprValidity<'_> {
-    type Error = InvalidExpr;
-    fn visit_expr_enum(&mut self, v: &ExprEnum) -> Result<(), Self::Error> {
-        match v {
-            ExprEnum::UIntLiteral(_)
-            | ExprEnum::SIntLiteral(_)
-            | ExprEnum::BoolLiteral(_)
-            | ExprEnum::PhantomConst(_)
-            | ExprEnum::BundleLiteral(_)
-            | ExprEnum::ArrayLiteral(_)
-            | ExprEnum::EnumLiteral(_)
-            | ExprEnum::Uninit(_)
-            | ExprEnum::NotU(_)
-            | ExprEnum::NotS(_)
-            | ExprEnum::NotB(_)
-            | ExprEnum::Neg(_)
-            | ExprEnum::BitAndU(_)
-            | ExprEnum::BitAndS(_)
-            | ExprEnum::BitAndB(_)
-            | ExprEnum::BitOrU(_)
-            | ExprEnum::BitOrS(_)
-            | ExprEnum::BitOrB(_)
-            | ExprEnum::BitXorU(_)
-            | ExprEnum::BitXorS(_)
-            | ExprEnum::BitXorB(_)
-            | ExprEnum::AddU(_)
-            | ExprEnum::AddS(_)
-            | ExprEnum::SubU(_)
-            | ExprEnum::SubS(_)
-            | ExprEnum::MulU(_)
-            | ExprEnum::MulS(_)
-            | ExprEnum::DivU(_)
-            | ExprEnum::DivS(_)
-            | ExprEnum::RemU(_)
-            | ExprEnum::RemS(_)
-            | ExprEnum::DynShlU(_)
-            | ExprEnum::DynShlS(_)
-            | ExprEnum::DynShrU(_)
-            | ExprEnum::DynShrS(_)
-            | ExprEnum::FixedShlU(_)
-            | ExprEnum::FixedShlS(_)
-            | ExprEnum::FixedShrU(_)
-            | ExprEnum::FixedShrS(_)
-            | ExprEnum::CmpLtB(_)
-            | ExprEnum::CmpLeB(_)
-            | ExprEnum::CmpGtB(_)
-            | ExprEnum::CmpGeB(_)
-            | ExprEnum::CmpEqB(_)
-            | ExprEnum::CmpNeB(_)
-            | ExprEnum::CmpLtU(_)
-            | ExprEnum::CmpLeU(_)
-            | ExprEnum::CmpGtU(_)
-            | ExprEnum::CmpGeU(_)
-            | ExprEnum::CmpEqU(_)
-            | ExprEnum::CmpNeU(_)
-            | ExprEnum::CmpLtS(_)
-            | ExprEnum::CmpLeS(_)
-            | ExprEnum::CmpGtS(_)
-            | ExprEnum::CmpGeS(_)
-            | ExprEnum::CmpEqS(_)
-            | ExprEnum::CmpNeS(_)
-            | ExprEnum::CastUIntToUInt(_)
-            | ExprEnum::CastUIntToSInt(_)
-            | ExprEnum::CastSIntToUInt(_)
-            | ExprEnum::CastSIntToSInt(_)
-            | ExprEnum::CastBoolToUInt(_)
-            | ExprEnum::CastBoolToSInt(_)
-            | ExprEnum::CastUIntToBool(_)
-            | ExprEnum::CastSIntToBool(_)
-            | ExprEnum::CastBoolToSyncReset(_)
-            | ExprEnum::CastUIntToSyncReset(_)
-            | ExprEnum::CastSIntToSyncReset(_)
-            | ExprEnum::CastBoolToAsyncReset(_)
-            | ExprEnum::CastUIntToAsyncReset(_)
-            | ExprEnum::CastSIntToAsyncReset(_)
-            | ExprEnum::CastSyncResetToBool(_)
-            | ExprEnum::CastSyncResetToUInt(_)
-            | ExprEnum::CastSyncResetToSInt(_)
-            | ExprEnum::CastSyncResetToReset(_)
-            | ExprEnum::CastAsyncResetToBool(_)
-            | ExprEnum::CastAsyncResetToUInt(_)
-            | ExprEnum::CastAsyncResetToSInt(_)
-            | ExprEnum::CastAsyncResetToReset(_)
-            | ExprEnum::CastResetToBool(_)
-            | ExprEnum::CastResetToUInt(_)
-            | ExprEnum::CastResetToSInt(_)
-            | ExprEnum::CastBoolToClock(_)
-            | ExprEnum::CastUIntToClock(_)
-            | ExprEnum::CastSIntToClock(_)
-            | ExprEnum::CastClockToBool(_)
-            | ExprEnum::CastClockToUInt(_)
-            | ExprEnum::CastClockToSInt(_)
-            | ExprEnum::FieldAccess(_)
-            | ExprEnum::ArrayIndex(_)
-            | ExprEnum::DynArrayIndex(_)
-            | ExprEnum::ReduceBitAndU(_)
-            | ExprEnum::ReduceBitAndS(_)
-            | ExprEnum::ReduceBitOrU(_)
-            | ExprEnum::ReduceBitOrS(_)
-            | ExprEnum::ReduceBitXorU(_)
-            | ExprEnum::ReduceBitXorS(_)
-            | ExprEnum::SliceUInt(_)
-            | ExprEnum::SliceSInt(_)
-            | ExprEnum::CastToBits(_)
-            | ExprEnum::CastBitsTo(_)
-            | ExprEnum::ToTraceAsString(_)
-            | ExprEnum::TraceAsStringAsInner(_)
-            | ExprEnum::FormalInput(_) => v.default_visit(self),
-            ExprEnum::VariantAccess(_)
-            | ExprEnum::ModuleIO(_)
-            | ExprEnum::Instance(_)
-            | ExprEnum::Wire(_)
-            | ExprEnum::Reg(_)
-            | ExprEnum::RegSync(_)
-            | ExprEnum::RegAsync(_)
-            | ExprEnum::MemPort(_) => {
-                if self.state.visible_exprs.contains(v) {
-                    // no need to visit inner expressions, we already checked them before adding them to visible_exprs
-                    Ok(())
-                } else {
-                    Err(InvalidExpr::ExprIsNotVisible(v.to_expr()))
-                }
-            }
-            ExprEnum::SimIoForGlobal(_) => Err(InvalidExpr::ExprIsNotVisible(v.to_expr())),
-        }
-    }
-}
-
 impl<T: BundleType> Module<T> {
     /// you generally should use the [`#[hdl_module]`][`crate::hdl_module`] proc-macro and [`ModuleBuilder`] instead
     #[track_caller]
@@ -2352,7 +1974,6 @@ impl<T: BundleType> Module<T> {
         AssertValidityState {
             module: self.canonical(),
             blocks: vec![],
-            visible_exprs: VisibleExprsStack::default(),
             target_states: HashMap::with_capacity_and_hasher(64, Default::default()),
         }
         .assert_validity();
@@ -2458,7 +2079,7 @@ impl<T: Type, R: ResetType> RegBuilder<Expr<ClockDomain<R>>, Option<Expr<T>>, T>
             ty,
         } = self;
         ModuleBuilder::with(|module_builder| {
-            let scoped_name = ScopedNameId(module_builder.name.into(), NameId(name, Id::new()));
+            let scoped_name = ScopedNameId(module_builder.name, NameId(name, Id::new()));
             let reg = Reg::new_unchecked(scoped_name, source_location, ty, clock_domain, init);
             let retval = reg.to_expr();
             // convert before borrow_mut since ModuleBuilder could be reentered by T::canonical()
@@ -2854,9 +2475,6 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
             instance,
         }
         .into(),
-        TargetBase::FormalInput(_) | TargetBase::SimIoForGlobal(_) => {
-            unreachable!("not a valid annotation target")
-        }
     };
     ModuleBuilder::with(|m| {
         unwrap!(m.impl_.borrow_mut().body.builder_normal_body_opt())
@@ -2871,7 +2489,7 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
 #[track_caller]
 pub fn wire_with_loc<T: Type>(name: &str, source_location: SourceLocation, ty: T) -> Expr<T> {
     ModuleBuilder::with(|m| {
-        let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new()));
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let wire = Wire::<T>::new_unchecked(scoped_name, source_location, ty);
         let retval = wire.to_expr();
         let canonical_wire = wire.canonical();
@@ -2903,7 +2521,7 @@ fn incomplete_declaration(
     source_location: SourceLocation,
 ) -> Rc<RefCell<IncompleteDeclaration>> {
     ModuleBuilder::with(|m| {
-        let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new()));
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete {
             name: scoped_name,
             source_location,
@@ -3079,7 +2697,7 @@ pub fn instance_with_loc<T: BundleType>(
     source_location: SourceLocation,
 ) -> Expr<T> {
     ModuleBuilder::with(|m| {
-        let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new()));
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let instance = Instance::<T> {
             scoped_name,
             instantiated,
@@ -3118,7 +2736,7 @@ fn memory_impl<Element: Type, Len: Size>(
     source_location: SourceLocation,
 ) -> MemBuilder<Element, Len> {
     ModuleBuilder::with(|m| {
-        let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new()));
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let (retval, target_mem) = MemBuilder::new(scoped_name, source_location, mem_element_type);
         let mut impl_ = m.impl_.borrow_mut();
         let body = impl_.body.builder_normal_body();
@@ -3273,7 +2891,7 @@ impl<T: Type> ModuleIO<T> {
         NameId(self.bundle_field.name, self.id)
     }
     pub fn scoped_name(&self) -> ScopedNameId {
-        ScopedNameId(self.containing_module_name.into(), self.name_id())
+        ScopedNameId(self.containing_module_name, self.name_id())
     }
     pub fn source_location(&self) -> SourceLocation {
         self.source_location
@@ -3346,102 +2964,10 @@ impl fmt::Debug for InstantiatedModule {
     }
 }
 
-#[derive(PartialEq, Eq, Hash, Clone, Copy)]
-pub enum InstantiatedModuleOrGlobal {
-    Global,
-    InstantiatedModule(InstantiatedModule),
-}
-
-impl InstantiatedModuleOrGlobal {
-    pub fn leaf_module_source_location(self) -> SourceLocation {
-        match self {
-            Self::Global => SourceLocation::builtin(),
-            Self::InstantiatedModule(v) => v.leaf_module().source_location(),
-        }
-    }
-}
-
-impl From<InstantiatedModule> for InstantiatedModuleOrGlobal {
-    fn from(value: InstantiatedModule) -> Self {
-        Self::InstantiatedModule(value)
-    }
-}
-
-impl fmt::Debug for InstantiatedModuleOrGlobal {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        match self {
-            Self::Global => f.write_str("Global"),
-            Self::InstantiatedModule(v) => v.fmt(f),
-        }
-    }
-}
-
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-pub struct TargetInInstantiatedModuleOrGlobal {
+pub struct TargetInInstantiatedModule {
-    instantiated_module_or_global: InstantiatedModuleOrGlobal,
+    pub instantiated_module: InstantiatedModule,
-    target: Target,
+    pub target: Target,
-}
-
-impl TargetInInstantiatedModuleOrGlobal {
-    #[track_caller]
-    pub fn new(instantiated_module_or_global: InstantiatedModuleOrGlobal, target: Target) -> Self {
-        match (
-            instantiated_module_or_global,
-            target.base().target_name().0.0,
-        ) {
-            (InstantiatedModuleOrGlobal::Global, NameIdOrGlobal::Global)
-            | (InstantiatedModuleOrGlobal::InstantiatedModule(_), NameIdOrGlobal::NameId(_)) => {
-                Self {
-                    instantiated_module_or_global,
-                    target,
-                }
-            }
-            (InstantiatedModuleOrGlobal::Global, NameIdOrGlobal::NameId(_))
-            | (InstantiatedModuleOrGlobal::InstantiatedModule(_), NameIdOrGlobal::Global) => {
-                panic!(
-                    "instantiated_module_or_global doesn't match target.base().target_name().0.0:\n\
-                    instantiated_module_or_global: {instantiated_module_or_global:?}\n\
-                    target: {target:?}"
-                )
-            }
-        }
-    }
-    #[track_caller]
-    pub fn from_target(
-        instantiated_module: impl Into<InstantiatedModuleOrGlobal>,
-        target: Target,
-    ) -> Self {
-        let instantiated_module = instantiated_module.into();
-        Self {
-            instantiated_module_or_global: match target.base().target_name().0.0 {
-                NameIdOrGlobal::Global => InstantiatedModuleOrGlobal::Global,
-                NameIdOrGlobal::NameId(name_id) => {
-                    let InstantiatedModuleOrGlobal::InstantiatedModule(instantiated_module) =
-                        instantiated_module
-                    else {
-                        panic!(
-                            "target is in a module, but no InstantiatedModule was provided: {target:#?}"
-                        );
-                    };
-                    assert_eq!(
-                        name_id,
-                        instantiated_module.leaf_module().name_id(),
-                        "target isn't contained in module:\n\
-                        target: {target:#?}\n\
-                        instantiated_module: {instantiated_module:?}",
-                    );
-                    InstantiatedModuleOrGlobal::InstantiatedModule(instantiated_module)
-                }
-            },
-            target,
-        }
-    }
-    pub fn instantiated_module_or_global(self) -> InstantiatedModuleOrGlobal {
-        self.instantiated_module_or_global
-    }
-    pub fn target(self) -> Target {
-        self.target
-    }
 }
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]

crates/fayalite/src/module/transform/deduce_resets.rs

@@ -10,8 +10,7 @@ use crate::{
         ops::{self, ArrayLiteral},
         target::{
             Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
-            TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString,
+            TargetPathDynArrayElement, TargetPathElement,
-            TargetPathTraceAsStringInner,
         },
     },
     formal::FormalKind,
@@ -27,7 +26,6 @@ use crate::{
     prelude::*,
     reset::{ResetType, ResetTypeDispatch},
     sim::ExternModuleSimulation,
-    ty::TraceAsString,
     util::{HashMap, HashSet},
 };
 use hashbrown::hash_map::Entry;
@@ -105,10 +103,6 @@ enum ResetsLayout {
         element: Interned<ResetsLayout>,
         reset_count: usize,
     },
-    Transparent {
-        inner: Interned<ResetsLayout>,
-        reset_count: usize,
-    },
 }
 
 impl ResetsLayout {
@@ -118,8 +112,7 @@ impl ResetsLayout {
             ResetsLayout::Reset | ResetsLayout::SyncReset | ResetsLayout::AsyncReset => 1,
             ResetsLayout::Bundle { reset_count, .. }
             | ResetsLayout::Enum { reset_count, .. }
-            | ResetsLayout::Array { reset_count, .. }
+            | ResetsLayout::Array { reset_count, .. } => reset_count,
-            | ResetsLayout::Transparent { reset_count, .. } => reset_count,
         }
     }
     fn new(ty: CanonicalType) -> Self {
@@ -173,13 +166,6 @@ impl ResetsLayout {
                     CanonicalType::Clock(_) => ResetsLayout::NoResets,
                     CanonicalType::PhantomConst(_) => ResetsLayout::NoResets,
                     CanonicalType::DynSimOnly(_) => ResetsLayout::NoResets,
-                    CanonicalType::TraceAsString(ty) => {
-                        let inner = ResetsLayout::new(ty.inner_ty()).intern_sized();
-                        ResetsLayout::Transparent {
-                            inner,
-                            reset_count: inner.reset_count(),
-                        }
-                    }
                 }
             }
         }
@@ -329,12 +315,6 @@ impl ResetGraph {
             } => {
                 self.append_new_nodes_for_layout(*element, node_indexes, source_location);
             }
-            ResetsLayout::Transparent {
-                inner,
-                reset_count: _,
-            } => {
-                self.append_new_nodes_for_layout(*inner, node_indexes, source_location);
-            }
         }
     }
 }
@@ -377,21 +357,6 @@ impl Resets {
             node_indexes: self.node_indexes,
         }
     }
-    fn trace_as_string_inner(self) -> Self {
-        let trace_as_string = TraceAsString::from_canonical(self.ty);
-        let ResetsLayout::Transparent {
-            inner,
-            reset_count: _,
-        } = self.layout
-        else {
-            unreachable!();
-        };
-        Self {
-            ty: trace_as_string.inner_ty(),
-            layout: *inner,
-            node_indexes: self.node_indexes,
-        }
-    }
     fn bundle_fields(self) -> impl Iterator<Item = Self> {
         let bundle = Bundle::from_canonical(self.ty);
         let ResetsLayout::Bundle {
@@ -515,17 +480,6 @@ impl Resets {
                     CanonicalType::SyncReset(SyncReset)
                 },
             ),
-            CanonicalType::TraceAsString(ty) => Ok(CanonicalType::TraceAsString(
-                ty.with_new_inner_ty(
-                    self.array_elements()
-                        .substituted_type(
-                            reset_graph,
-                            fallback_to_sync_reset,
-                            fallback_error_source_location,
-                        )?
-                        .intern_sized(),
-                ),
-            )),
         }
     }
 }
@@ -1059,8 +1013,7 @@ fn cast_bit_op<P: Pass, T: Type, A: Type>(
                             | CanonicalType::Bundle(_)
                             | CanonicalType::Reset(_)
                             | CanonicalType::PhantomConst(_)
-                            | CanonicalType::DynSimOnly(_)
+                            | CanonicalType::DynSimOnly(_) => unreachable!(),
-                            | CanonicalType::TraceAsString(_) => unreachable!(),
                             $(CanonicalType::$Variant(ty) => Expr::expr_enum($arg.cast_to(ty)),)*
                         }
                     };
@@ -1071,8 +1024,7 @@ fn cast_bit_op<P: Pass, T: Type, A: Type>(
                             CanonicalType::Array(_)
                             | CanonicalType::Enum(_)
                             | CanonicalType::Bundle(_)
-                            | CanonicalType::Reset(_)
+                            | CanonicalType::Reset(_) => unreachable!(),
-                            | CanonicalType::TraceAsString(_) => unreachable!(),
                             CanonicalType::PhantomConst(_) |
                             CanonicalType::DynSimOnly(_) => Expr::expr_enum(arg),
                             $(CanonicalType::$Variant(_) => {
@@ -1204,10 +1156,6 @@ impl<P: Pass> RunPass<P> for ExprEnum {
             ExprEnum::SliceSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::CastToBits(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::CastBitsTo(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
-            ExprEnum::TraceAsStringAsInner(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::ToTraceAsString(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::ModuleIO(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::Instance(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::Wire(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
@@ -1215,10 +1163,6 @@ impl<P: Pass> RunPass<P> for ExprEnum {
             ExprEnum::RegSync(expr) => reg_expr_run_pass(expr, pass_args),
             ExprEnum::RegAsync(expr) => reg_expr_run_pass(expr, pass_args),
             ExprEnum::MemPort(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
-            ExprEnum::FormalInput(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
-            ExprEnum::SimIoForGlobal(_) => {
-                unreachable!("Module is known to not contain SimIoForGlobal from validation")
-            }
         }
     }
 }
@@ -1592,67 +1536,6 @@ impl RunPassExpr for ops::CastBitsTo {
     }
 }
 
-impl RunPassExpr for ops::TraceAsStringAsInner {
-    type Args<'a> = [Expr<CanonicalType>; 1];
-
-    fn args<'a>(&'a self) -> Self::Args<'a> {
-        [Expr::canonical(self.arg())]
-    }
-
-    fn source_location(&self) -> Option<SourceLocation> {
-        None
-    }
-
-    fn union_parts(
-        &self,
-        resets: Resets,
-        args_resets: Vec<Resets>,
-        mut pass_args: PassArgs<'_, BuildResetGraph>,
-    ) -> Result<(), DeduceResetsError> {
-        pass_args.union(resets, args_resets[0].trace_as_string_inner(), None)
-    }
-
-    fn new(
-        &self,
-        _ty: CanonicalType,
-        new_args: Vec<Expr<CanonicalType>>,
-    ) -> Result<Self, DeduceResetsError> {
-        Ok(Self::new(Expr::from_canonical(new_args[0])))
-    }
-}
-
-impl RunPassExpr for ops::ToTraceAsString {
-    type Args<'a> = [Expr<CanonicalType>; 1];
-
-    fn args<'a>(&'a self) -> Self::Args<'a> {
-        [Expr::canonical(self.inner())]
-    }
-
-    fn source_location(&self) -> Option<SourceLocation> {
-        None
-    }
-
-    fn union_parts(
-        &self,
-        resets: Resets,
-        args_resets: Vec<Resets>,
-        mut pass_args: PassArgs<'_, BuildResetGraph>,
-    ) -> Result<(), DeduceResetsError> {
-        pass_args.union(resets.trace_as_string_inner(), args_resets[0], None)
-    }
-
-    fn new(
-        &self,
-        _ty: CanonicalType,
-        new_args: Vec<Expr<CanonicalType>>,
-    ) -> Result<Self, DeduceResetsError> {
-        Ok(Self::new(
-            new_args[0],
-            self.ty().with_new_inner_ty(new_args[0].ty().intern_sized()),
-        ))
-    }
-}
-
 impl RunPassExpr for ModuleIO<CanonicalType> {
     type Args<'a> = [Expr<CanonicalType>; 0];
 
@@ -1808,8 +1691,7 @@ impl RunPassDispatch for AnyReg {
                 | CanonicalType::Reset(_)
                 | CanonicalType::Clock(_)
                 | CanonicalType::PhantomConst(_)
-                | CanonicalType::DynSimOnly(_)
+                | CanonicalType::DynSimOnly(_) => unreachable!(),
-                | CanonicalType::TraceAsString(_) => unreachable!(),
             }
         })
     }
@@ -1936,7 +1818,6 @@ impl_run_pass_copy!([] SVAttributeAnnotation);
 impl_run_pass_copy!([] UInt);
 impl_run_pass_copy!([] usize);
 impl_run_pass_copy!([] FormalKind);
-impl_run_pass_copy!([] crate::formal::FormalInput);
 impl_run_pass_copy!([] PhantomConst);
 
 macro_rules! impl_run_pass_for_struct {
@@ -2253,12 +2134,6 @@ impl<P: Pass> RunPass<P> for TargetBase {
             &TargetBase::RegAsync(v) => v.into(),
             TargetBase::Wire(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Wire)),
             TargetBase::Instance(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Instance)),
-            TargetBase::FormalInput(v) => {
-                return Ok(v.run_pass(pass_args)?.map(TargetBase::FormalInput));
-            }
-            TargetBase::SimIoForGlobal(_) => {
-                unreachable!("Module is known to not contain SimIoForGlobal from validation")
-            }
         };
         Ok(reg.run_pass(pass_args)?.map(|reg| match reg {
             AnyReg::Reg(reg) => TargetBase::Reg(reg),
@@ -2298,6 +2173,30 @@ impl<P: Pass> RunPass<P> for StmtDeclaration {
     }
 }
 
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathBundleField {
+        name: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathArrayElement {
+        index: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathDynArrayElement {}
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for TargetPathElement {
+        BundleField(v),
+        ArrayElement(v),
+        DynArrayElement(v),
+    }
+}
+
 impl_run_pass_for_enum! {
     impl[] RunPass for Target {
         Base(v),
@@ -2305,28 +2204,11 @@ impl_run_pass_for_enum! {
     }
 }
 
-impl<P: Pass> RunPass<P> for TargetChild {
+impl_run_pass_for_struct! {
-    fn run_pass(
+    #[constructor = TargetChild::new(parent, path_element)]
-        &self,
+    impl[] RunPass for TargetChild {
-        mut pass_args: PassArgs<'_, P>,
+        parent(): _,
-    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        path_element(): _,
-        Ok(self.parent().run_pass(pass_args.as_mut())?.map(|parent| {
-            let path_element = match *self.path_element() {
-                TargetPathElement::BundleField(TargetPathBundleField { name: _ })
-                | TargetPathElement::ArrayElement(TargetPathArrayElement { index: _ })
-                | TargetPathElement::DynArrayElement(TargetPathDynArrayElement {})
-                | TargetPathElement::TraceAsStringInner(TargetPathTraceAsStringInner {}) => {
-                    self.path_element()
-                }
-                TargetPathElement::ToTraceAsString(TargetPathToTraceAsString { ty }) => {
-                    TargetPathElement::from(TargetPathToTraceAsString {
-                        ty: ty.with_new_inner_ty(parent.canonical_ty().intern_sized()),
-                    })
-                    .intern_sized()
-                }
-            };
-            TargetChild::new(parent, path_element)
-        }))
     }
 }
 

crates/fayalite/src/module/transform/simplify_enums.rs

@@ -17,7 +17,7 @@ use crate::{
         transform::visit::{Fold, Folder},
     },
     source_location::SourceLocation,
-    ty::{CanonicalType, TraceAsString, Type},
+    ty::{CanonicalType, Type},
     util::HashMap,
     wire::Wire,
 };
@@ -64,7 +64,6 @@ fn contains_any_enum_types(ty: CanonicalType) -> bool {
                     .fields()
                     .iter()
                     .any(|field| contains_any_enum_types(field.ty)),
-                CanonicalType::TraceAsString(ty) => contains_any_enum_types(ty.inner_ty()),
                 CanonicalType::UInt(_)
                 | CanonicalType::SInt(_)
                 | CanonicalType::Bool(_)
@@ -96,12 +95,11 @@ enum EnumTypeState {
 
 struct ModuleState {
     module_name: NameId,
-    expr_cache: HashMap<ExprEnum, ExprEnum>,
 }
 
 impl ModuleState {
     fn gen_name(&mut self, name: &str) -> ScopedNameId {
-        ScopedNameId(self.module_name.into(), NameId(name.intern(), Id::new()))
+        ScopedNameId(self.module_name, NameId(name.intern(), Id::new()))
     }
 }
 
@@ -315,24 +313,6 @@ impl State {
         }
         Ok(())
     }
-    fn handle_stmt_connect_trace_as_string(
-        &mut self,
-        unfolded_lhs_ty: TraceAsString,
-        unfolded_rhs_ty: TraceAsString,
-        folded_lhs: Expr<TraceAsString>,
-        folded_rhs: Expr<TraceAsString>,
-        source_location: SourceLocation,
-        output_stmts: &mut Vec<Stmt>,
-    ) -> Result<(), SimplifyEnumsError> {
-        self.handle_stmt_connect(
-            unfolded_lhs_ty.inner_ty(),
-            unfolded_rhs_ty.inner_ty(),
-            ops::TraceAsStringAsInner::new(folded_lhs).to_expr(),
-            ops::TraceAsStringAsInner::new(folded_rhs).to_expr(),
-            source_location,
-            output_stmts,
-        )
-    }
     fn handle_stmt_connect_bundle(
         &mut self,
         unfolded_lhs_ty: Bundle,
@@ -529,15 +509,6 @@ impl State {
                 source_location,
                 output_stmts,
             ),
-            CanonicalType::TraceAsString(unfolded_lhs_ty) => self
-                .handle_stmt_connect_trace_as_string(
-                    unfolded_lhs_ty,
-                    TraceAsString::from_canonical(unfolded_rhs_ty),
-                    Expr::from_canonical(folded_lhs),
-                    Expr::from_canonical(folded_rhs),
-                    source_location,
-                    output_stmts,
-                ),
             CanonicalType::UInt(_)
             | CanonicalType::SInt(_)
             | CanonicalType::Bool(_)
@@ -557,8 +528,6 @@ fn connect_port(
     rhs: Expr<CanonicalType>,
     source_location: SourceLocation,
 ) {
-    let lhs = Expr::unwrap_transparent_types(lhs);
-    let rhs = Expr::unwrap_transparent_types(rhs);
     if lhs.ty() == rhs.ty() {
         stmts.push(
             StmtConnect {
@@ -604,9 +573,6 @@ fn connect_port(
                 connect_port(stmts, lhs[index], rhs[index], source_location);
             }
         }
-        (CanonicalType::TraceAsString(_), CanonicalType::TraceAsString(_)) => {
-            unreachable!("handled by unwrap_transparent_types")
-        }
         (CanonicalType::Bundle(_), _)
         | (CanonicalType::Enum(_), _)
         | (CanonicalType::Array(_), _)
@@ -618,8 +584,7 @@ fn connect_port(
         | (CanonicalType::SyncReset(_), _)
         | (CanonicalType::Reset(_), _)
         | (CanonicalType::PhantomConst(_), _)
-        | (CanonicalType::DynSimOnly(_), _)
+        | (CanonicalType::DynSimOnly(_), _) => unreachable!(
-        | (CanonicalType::TraceAsString(_), _) => unreachable!(
             "trying to connect memory ports:\n{:?}\n{:?}",
             lhs.ty(),
             rhs.ty(),
@@ -676,7 +641,6 @@ impl Folder for State {
     fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> {
         self.module_state_stack.push(ModuleState {
             module_name: v.name_id(),
-            expr_cache: HashMap::default(),
         });
         let retval = Fold::default_fold(v, self);
         self.module_state_stack.pop();
@@ -684,39 +648,30 @@ impl Folder for State {
     }
 
     fn fold_expr_enum(&mut self, op: ExprEnum) -> Result<ExprEnum, Self::Error> {
-        if let Some(folded_op) = self
+        match op {
-            .module_state_stack
-            .last()
-            .expect("known to be in module")
-            .expr_cache
-            .get(&op)
-        {
-            return Ok(*folded_op);
-        }
-        let folded_op = match op {
             ExprEnum::EnumLiteral(op) => {
                 let folded_variant_value = op.variant_value().map(|v| v.fold(self)).transpose()?;
-                *Expr::expr_enum(self.handle_enum_literal(
+                Ok(*Expr::expr_enum(self.handle_enum_literal(
                     op.ty(),
                     op.variant_index(),
                     folded_variant_value,
-                )?)
+                )?))
             }
             ExprEnum::VariantAccess(op) => {
                 let folded_base_expr = Expr::canonical(op.base()).fold(self)?;
-                *Expr::expr_enum(self.handle_variant_access(
+                Ok(*Expr::expr_enum(self.handle_variant_access(
                     op.base().ty(),
                     folded_base_expr,
                     op.variant_index(),
-                )?)
+                )?))
             }
-            ExprEnum::MemPort(mem_port) => {
+            ExprEnum::MemPort(mem_port) => Ok(
                 if let Some(&wire) = self.replacement_mem_ports.get(&mem_port) {
                     ExprEnum::Wire(wire)
                 } else {
                     ExprEnum::MemPort(mem_port.fold(self)?)
-                }
+                },
-            }
+            ),
             ExprEnum::UIntLiteral(_)
             | ExprEnum::SIntLiteral(_)
             | ExprEnum::BoolLiteral(_)
@@ -817,23 +772,13 @@ impl Folder for State {
             | ExprEnum::SliceSInt(_)
             | ExprEnum::CastToBits(_)
             | ExprEnum::CastBitsTo(_)
-            | ExprEnum::TraceAsStringAsInner(_)
-            | ExprEnum::ToTraceAsString(_)
             | ExprEnum::ModuleIO(_)
             | ExprEnum::Instance(_)
             | ExprEnum::Wire(_)
             | ExprEnum::Reg(_)
             | ExprEnum::RegSync(_)
-            | ExprEnum::RegAsync(_)
+            | ExprEnum::RegAsync(_) => op.default_fold(self),
-            | ExprEnum::FormalInput(_)
+        }
-            | ExprEnum::SimIoForGlobal(_) => op.default_fold(self)?,
-        };
-        self.module_state_stack
-            .last_mut()
-            .expect("known to be in module")
-            .expr_cache
-            .insert(op, folded_op);
-        Ok(folded_op)
     }
 
     fn fold_block(&mut self, block: Block) -> Result<Block, Self::Error> {
@@ -991,8 +936,7 @@ impl Folder for State {
             | CanonicalType::SyncReset(_)
             | CanonicalType::Reset(_)
             | CanonicalType::PhantomConst(_)
-            | CanonicalType::DynSimOnly(_)
+            | CanonicalType::DynSimOnly(_) => canonical_type.default_fold(self),
-            | CanonicalType::TraceAsString(_) => canonical_type.default_fold(self),
         }
     }
 

crates/fayalite/src/module/transform/simplify_memories.rs

@@ -90,7 +90,7 @@ impl MemSplit {
         }
     }
     fn new(element_type: CanonicalType) -> Self {
-        match element_type.unwrap_transparent_types() {
+        match element_type {
             CanonicalType::Bundle(bundle_ty) => MemSplit::Bundle {
                 fields: bundle_ty
                     .fields()
@@ -195,7 +195,6 @@ impl MemSplit {
             | CanonicalType::SyncReset(_)
             | CanonicalType::Reset(_) => unreachable!("memory element type is a storable type"),
             CanonicalType::DynSimOnly(_) => todo!("memory containing sim-only values"),
-            CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"),
         }
     }
 }
@@ -307,9 +306,7 @@ impl SplitMemState<'_, '_> {
         let outer_mem_name_path_len = self.mem_name_path.len();
         match self.split {
             MemSplit::Bundle { fields } => {
-                let CanonicalType::Bundle(bundle_type) =
+                let CanonicalType::Bundle(bundle_type) = self.element_type else {
-                    self.element_type.unwrap_transparent_types()
-                else {
                     unreachable!();
                 };
                 for ((field, field_offset), split) in bundle_type
@@ -324,10 +321,7 @@ impl SplitMemState<'_, '_> {
                     let field_ty_bit_width = field.ty.bit_width();
                     self.split_state_stack.push_map(
                         |e: Expr<CanonicalType>| {
-                            Expr::field(
+                            Expr::field(Expr::<Bundle>::from_canonical(e), &field.name)
-                                Expr::<Bundle>::from_canonical(Expr::unwrap_transparent_types(e)),
-                                &field.name,
-                            )
                         },
                         |initial_value_element| {
                             let Some(field_offset) = field_offset.only_bit_width() else {
@@ -383,8 +377,8 @@ impl SplitMemState<'_, '_> {
                         };
                         self.output_stmts.push(
                             StmtConnect {
-                                lhs: Expr::unwrap_transparent_types(Expr::field(port_expr, name)),
+                                lhs: Expr::field(port_expr, name),
-                                rhs: Expr::unwrap_transparent_types(Expr::field(wire_expr, name)),
+                                rhs: Expr::field(wire_expr, name),
                                 source_location: port.source_location(),
                             }
                             .into(),
@@ -395,8 +389,7 @@ impl SplitMemState<'_, '_> {
                 self.output_mems.push(new_mem);
             }
             MemSplit::Array { elements } => {
-                let CanonicalType::Array(array_type) = self.element_type.unwrap_transparent_types()
+                let CanonicalType::Array(array_type) = self.element_type else {
-                else {
                     unreachable!();
                 };
                 let element_type = array_type.element();
@@ -405,7 +398,7 @@ impl SplitMemState<'_, '_> {
                     self.mem_name_path.truncate(outer_mem_name_path_len);
                     write!(self.mem_name_path, "_{index}").unwrap();
                     self.split_state_stack.push_map(
-                        |e| Expr::<Array>::from_canonical(Expr::unwrap_transparent_types(e))[index],
+                        |e| Expr::<Array>::from_canonical(e)[index],
                         |initial_value_element| {
                             &initial_value_element[index * element_bit_width..][..element_bit_width]
                         },
@@ -471,7 +464,7 @@ impl ModuleState {
         assert_eq!(memory_element_array_range_len % input_array_type.len(), 0);
         let chunk_size = memory_element_array_range_len / input_array_type.len();
         for index in 0..input_array_type.len() {
-            let map = |e| Expr::<Array>::from_canonical(Expr::unwrap_transparent_types(e))[index];
+            let map = |e| Expr::<Array>::from_canonical(e)[index];
             let wire_rdata = wire_rdata.map(map);
             let wire_wdata = wire_wdata.map(map);
             let wire_wmask = wire_wmask.map(map);
@@ -512,8 +505,8 @@ impl ModuleState {
                             port_read: Expr<CanonicalType>| {
             output_stmts.push(
                 StmtConnect {
-                    lhs: Expr::unwrap_transparent_types(wire_read),
+                    lhs: wire_read,
-                    rhs: Expr::unwrap_transparent_types(port_read),
+                    rhs: port_read,
                     source_location,
                 }
                 .into(),
@@ -524,8 +517,8 @@ impl ModuleState {
                              port_write: Expr<CanonicalType>| {
             output_stmts.push(
                 StmtConnect {
-                    lhs: Expr::unwrap_transparent_types(port_write),
+                    lhs: port_write,
-                    rhs: Expr::unwrap_transparent_types(wire_write),
+                    rhs: wire_write,
                     source_location,
                 }
                 .into(),
@@ -537,8 +530,7 @@ impl ModuleState {
             connect_read(
                 output_stmts,
                 wire_read,
-                Expr::<UInt>::from_canonical(Expr::unwrap_transparent_types(port_read))
+                Expr::<UInt>::from_canonical(port_read).cast_bits_to(wire_read.ty()),
-                    .cast_bits_to(wire_read.ty()),
             );
         };
         let connect_write_enum =
@@ -552,7 +544,7 @@ impl ModuleState {
                 );
             };
         loop {
-            match input_element_type.unwrap_transparent_types() {
+            match input_element_type {
                 CanonicalType::Bundle(_) => {
                     unreachable!("bundle types are always split")
                 }
@@ -633,9 +625,6 @@ impl ModuleState {
                 | CanonicalType::SyncReset(_)
                 | CanonicalType::Reset(_) => unreachable!("memory element type is a storable type"),
                 CanonicalType::DynSimOnly(_) => todo!("memory containing sim-only values"),
-                CanonicalType::TraceAsString(_) => {
-                    unreachable!("handled by unwrap_transparent_types")
-                }
             }
             break;
         }

crates/fayalite/src/module/transform/visit.rs

@@ -14,17 +14,16 @@ use crate::{
         Expr, ExprEnum, ValueType, ops,
         target::{
             Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
-            TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString,
+            TargetPathDynArrayElement, TargetPathElement,
-            TargetPathTraceAsStringInner,
         },
     },
-    formal::{FormalInput, FormalInputKind, FormalKind},
+    formal::FormalKind,
     int::{Bool, SIntType, SIntValue, Size, UIntType, UIntValue},
     intern::{Intern, Interned},
     memory::{Mem, MemPort, PortKind, PortName, PortType, ReadUnderWrite},
     module::{
         AnnotatedModuleIO, Block, BlockId, ExternModuleBody, ExternModuleParameter,
-        ExternModuleParameterValue, Instance, Module, ModuleBody, ModuleIO, NameId, NameIdOrGlobal,
+        ExternModuleParameterValue, Instance, Module, ModuleBody, ModuleIO, NameId,
         NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf,
         StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
@@ -33,7 +32,7 @@ use crate::{
     reset::{AsyncReset, Reset, ResetType, SyncReset},
     sim::{ExternModuleSimulation, value::DynSimOnly},
     source_location::SourceLocation,
-    ty::{CanonicalType, TraceAsString, Type},
+    ty::{CanonicalType, Type},
     vendor::xilinx::{
         XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, XilinxAnnotation,
     },
@@ -482,30 +481,4 @@ impl<T: ?Sized + Visit<State>, State: ?Sized + Visitor> Visit<State> for &'_ mut
     }
 }
 
-impl<State: ?Sized + Visitor> Visit<State> for NameIdOrGlobal {
-    fn visit(&self, state: &mut State) -> Result<(), <State>::Error> {
-        state.visit_name_id_or_global(self)
-    }
-
-    fn default_visit(&self, state: &mut State) -> Result<(), <State>::Error> {
-        match self {
-            Self::Global => Ok(()),
-            Self::NameId(name_id) => name_id.visit(state),
-        }
-    }
-}
-
-impl<State: ?Sized + Folder> Fold<State> for NameIdOrGlobal {
-    fn fold(self, state: &mut State) -> Result<Self, <State>::Error> {
-        state.fold_name_id_or_global(self)
-    }
-
-    fn default_fold(self, state: &mut State) -> Result<Self, <State>::Error> {
-        match self {
-            Self::Global => Ok(Self::Global),
-            Self::NameId(name_id) => Ok(Self::NameId(name_id.fold(state)?)),
-        }
-    }
-}
-
 include!(concat!(env!("OUT_DIR"), "/visit.rs"));

crates/fayalite/src/phantom_const.rs

@@ -9,7 +9,7 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten,
-        SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self,
+        StaticType, Type, TypeProperties, impl_match_variant_as_self,
         serde_impls::{SerdeCanonicalType, SerdePhantomConst},
     },
 };
@@ -327,15 +327,6 @@ impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
     }
 }
 
-impl<T: ?Sized + PhantomConstValue> SimValueDebug for PhantomConst<T> {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl<T: ?Sized + PhantomConstValue> Default for PhantomConst<T>
 where
     Interned<T>: Default,

crates/fayalite/src/prelude.rs

@@ -13,11 +13,11 @@ pub use crate::{
     enum_::{Enum, HdlNone, HdlOption, HdlSome},
     expr::{
         CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
-        ReduceBits, ToExpr, ToTraceAsString, ValueType, repeat,
+        ReduceBits, ToExpr, ValueType, repeat,
     },
     formal::{
-        all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, hdl_assert,
+        MakeFormalExpr, all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset,
-        hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover,
+        hdl_assert, hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover,
         hdl_cover_with_enable,
     },
     hdl, hdl_module,
@@ -37,8 +37,8 @@ pub use crate::{
         value::{SimOnly, SimOnlyValue, SimValue, ToSimValue, ToSimValueWithType},
     },
     source_location::SourceLocation,
-    testing::{FormalMode, assert_formal, checked_vcd_output},
+    testing::{FormalMode, assert_formal},
-    ty::{AsMask, CanonicalType, TraceAsString, Type},
+    ty::{AsMask, CanonicalType, Type},
     util::{ConstUsize, GenericConstUsize},
     wire::Wire,
 };

crates/fayalite/src/reg.rs

@@ -79,7 +79,6 @@ impl<T: Type, R: ResetType> Reg<T, R> {
         if let Some(init) = init {
             assert_eq!(ty, init.ty(), "register's type must match init type");
         }
-        scoped_name.0.assert_is_name_id();
         Self {
             name: scoped_name,
             source_location,
@@ -95,7 +94,7 @@ impl<T: Type, R: ResetType> Reg<T, R> {
         self.containing_module_name_id().0
     }
     pub fn containing_module_name_id(&self) -> NameId {
-        self.name.0.unwrap_name_id()
+        self.name.0
     }
     pub fn name(&self) -> Interned<str> {
         self.name_id().0

crates/fayalite/src/reset.rs

@@ -1,6 +1,5 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-
 use crate::{
     clock::Clock,
     expr::{CastToImpl, Expr, ValueType},
@@ -9,13 +8,11 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter,
-        OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties,
+        OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self,
-        impl_match_variant_as_self,
     },
     util::ConstUsize,
 };
 use bitvec::{bits, order::Lsb0};
-use std::fmt;
 
 mod sealed {
     pub trait ResetTypeSealed {}
@@ -103,15 +100,6 @@ macro_rules! reset_type {
             }
         }
 
-        impl SimValueDebug for $name {
-            fn sim_value_debug(
-                value: &<Self as Type>::SimValue,
-                f: &mut fmt::Formatter<'_>,
-            ) -> fmt::Result {
-                fmt::Debug::fmt(value, f)
-            }
-        }
-
         impl $name {
             pub fn type_properties(self) -> TypeProperties {
                 Self::TYPE_PROPERTIES

crates/fayalite/src/sim/interpreter.rs

@@ -6,9 +6,9 @@ use crate::{
     int::{BoolOrIntType, SInt, UInt},
     intern::{Intern, Interned, Memoize},
     sim::interpreter::parts::{
-        StateLayout, StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
+        StateLayout, StatePartIndex, StatePartKind, StatePartKindBigSlots, StatePartKindMemories,
-        StatePartKindMemories, StatePartKindSimOnlySlots, StatePartKindSmallSlots, StatePartLen,
+        StatePartKindSimOnlySlots, StatePartKindSmallSlots, StatePartLen, TypeIndexRange,
-        TypeIndexRange, TypeLayout, get_state_part_kinds,
+        TypeLayout, get_state_part_kinds,
     },
     source_location::SourceLocation,
     util::{HashMap, HashSet},
@@ -17,11 +17,12 @@ use bitvec::slice::BitSlice;
 use num_bigint::BigInt;
 use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
+    borrow::BorrowMut,
     convert::Infallible,
     fmt::{self, Write},
     hash::Hash,
     marker::PhantomData,
-    ops::{ControlFlow, Deref, Index, IndexMut},
+    ops::{ControlFlow, Deref, DerefMut, Index, IndexMut},
 };
 use vec_map::VecMap;
 
@@ -914,21 +915,6 @@ impl<K: StatePartKind> StatePart<K> {
             value: K::borrow_state(&mut self.value),
         }
     }
-    pub(crate) fn state_index_fetch_maybe_modified_flag(
-        &self,
-        part_index: StatePartIndex<K>,
-    ) -> bool {
-        K::state_index_fetch_maybe_modified_flag(&self.value, part_index)
-    }
-    pub(crate) fn state_index_range_fetch_maybe_modified_flags(
-        &self,
-        part_index_range: StatePartIndexRange<K>,
-    ) -> bool {
-        K::state_index_range_fetch_maybe_modified_flags(&self.value, part_index_range)
-    }
-    pub(crate) fn clear_all_maybe_modified_flags(&mut self) {
-        K::clear_all_maybe_modified_flags(&mut self.value)
-    }
 }
 
 #[derive(Clone, PartialEq, Eq, Hash, Debug)]
@@ -936,38 +922,56 @@ pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> {
     pub(crate) value: K::BorrowedState<'a>,
 }
 
-impl<K: StatePartKind> BorrowedStatePart<'_, K> {
+impl<
+    'a,
+    K: StatePartKind<
+        BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T> + BorrowMut<[T]>>,
+    >,
+    T,
+> BorrowedStatePart<'a, K>
+{
     pub(crate) fn get_disjoint_mut<const N: usize>(
         &mut self,
         indexes: [StatePartIndex<K>; N],
-    ) -> [&mut K::StateElement; N] {
+    ) -> [&mut T; N] {
-        K::borrowed_state_get_disjoint_mut(&mut self.value, indexes)
+        (*self.value)
+            .borrow_mut()
+            .get_disjoint_mut(indexes.map(|v| v.value as usize))
+            .expect("indexes are disjoint")
     }
 }
 
-impl<K: StatePartKind> Index<StatePartIndex<K>> for StatePart<K> {
+impl<K: StatePartKind<State: Deref<Target: Index<usize, Output = T>>>, T> Index<StatePartIndex<K>>
-    type Output = K::StateElement;
+    for StatePart<K>
+{
+    type Output = T;
     fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
-        K::state_index(&self.value, index)
+        &self.value[index.value as usize]
     }
 }
 
-impl<K: StatePartKind> IndexMut<StatePartIndex<K>> for StatePart<K> {
+impl<K: StatePartKind<State: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
+    IndexMut<StatePartIndex<K>> for StatePart<K>
+{
     fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
-        K::state_index_mut(&mut self.value, index)
+        &mut self.value[index.value as usize]
     }
 }
 
-impl<K: StatePartKind> Index<StatePartIndex<K>> for BorrowedStatePart<'_, K> {
+impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
-    type Output = K::StateElement;
+    Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
+{
+    type Output = T;
     fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
-        K::borrowed_state_index(&self.value, index)
+        &self.value[index.value as usize]
     }
 }
 
-impl<K: StatePartKind> IndexMut<StatePartIndex<K>> for BorrowedStatePart<'_, K> {
+impl<'a, K: StatePartKind<BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
+    IndexMut<StatePartIndex<K>> for BorrowedStatePart<'a, K>
+{
     fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
-        K::borrowed_state_index_mut(&mut self.value, index)
+        &mut self.value[index.value as usize]
     }
 }
 
@@ -980,7 +984,6 @@ macro_rules! make_state {
             pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
             pub(crate) pc: usize,
             pub(crate) memory_write_log: Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
-            pub(crate) assert_failed_log: Vec<usize>,
             $(pub(crate) $state_plural_field: StatePart<$state_kind>,)*
             $(pub(crate) $type_plural_field: StatePart<$type_kind>,)*
         }
@@ -991,7 +994,6 @@ macro_rules! make_state {
                     insns: _,
                     pc,
                     memory_write_log,
-                    assert_failed_log,
                     $($state_plural_field,)*
                     $($type_plural_field,)*
                 } = self;
@@ -999,7 +1001,6 @@ macro_rules! make_state {
                     .field("insns", &InsnsOfState(self))
                     .field("pc", pc)
                     .field("memory_write_log", memory_write_log)
-                    .field("assert_failed_log", assert_failed_log)
                     $(.field(stringify!($state_plural_field), $state_plural_field))*
                     $(.field(stringify!($type_plural_field), $type_plural_field))*
                     .finish()
@@ -1012,7 +1013,6 @@ macro_rules! make_state {
                     insns,
                     pc: 0,
                     memory_write_log: Vec::with_capacity(32),
-                    assert_failed_log: Vec::new(),
                     $($state_plural_field: StatePart::new(&insns.state_layout.$state_plural_field.layout_data),)*
                     $($type_plural_field: StatePart::new(&insns.state_layout.ty.$type_plural_field.layout_data),)*
                 }
@@ -1024,20 +1024,10 @@ macro_rules! make_state {
                     pc: self.pc,
                     orig_pc: &mut self.pc,
                     memory_write_log: &mut self.memory_write_log,
-                    assert_failed_log: &mut self.assert_failed_log,
                     $($state_plural_field: self.$state_plural_field.borrow(),)*
                     $($type_plural_field: self.$type_plural_field.borrow(),)*
                 }
             }
-            pub(crate) fn type_index_range_fetch_maybe_modified_flags(&self, range: TypeIndexRange) -> bool {
-                $(self.$type_plural_field.state_index_range_fetch_maybe_modified_flags(
-                    range.$type_plural_field,
-                ))||*
-            }
-            pub(crate) fn clear_all_maybe_modified_flags(&mut self) {
-                $(self.$state_plural_field.clear_all_maybe_modified_flags();)*
-                $(self.$type_plural_field.clear_all_maybe_modified_flags();)*
-            }
         }
 
         #[derive(Debug)]
@@ -1047,7 +1037,6 @@ macro_rules! make_state {
             pub(crate) orig_pc: &'a mut usize,
             pub(crate) pc: usize,
             pub(crate) memory_write_log: &'a mut Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
-            pub(crate) assert_failed_log: &'a mut Vec<usize>,
             $(pub(crate) $state_plural_field: BorrowedStatePart<'a, $state_kind>,)*
             $(pub(crate) $type_plural_field: BorrowedStatePart<'a, $type_kind>,)*
         }
@@ -1305,7 +1294,6 @@ impl State {
             insns: _,
             pc,
             memory_write_log: _,
-            assert_failed_log: _,
             memories: _,
             small_slots: _,
             big_slots: _,
@@ -1345,10 +1333,6 @@ impl BorrowedState<'_> {
             self.memory_write_log.push(log_entry);
         }
     }
-    #[cold]
-    fn assert_failed(&mut self, assert_index: usize) {
-        self.assert_failed_log.push(assert_index);
-    }
 }
 
 fn bigint_pow2(width: usize) -> Interned<BigInt> {
@@ -2116,19 +2100,6 @@ impl_insns! {
         state.log_memory_write(memory, addr);
         next!();
     }
-    Assert {
-        #[kind = Input]
-        clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
-        #[kind = Input]
-        pred: StatePartIndex<StatePartKindSmallSlots>,
-        #[kind = Immediate]
-        assert_index: usize,
-    } => {
-        if state.small_slots[clk_triggered] != 0 && state.small_slots[pred] == 0 {
-            state.assert_failed(assert_index);
-        }
-        next!();
-    }
     Return => {
         break RunResult::Return(());
     }

crates/fayalite/src/sim/interpreter/parts.rs

@@ -236,7 +236,6 @@ pub(crate) trait StatePartKind:
     type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
     type State: fmt::Debug + 'static + Clone;
     type BorrowedState<'a>: 'a;
-    type StateElement;
     fn new_state(layout_data: &[Self::LayoutData]) -> Self::State;
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
     fn part_debug_data<BK: InsnsBuildingKind>(
@@ -248,35 +247,6 @@ pub(crate) trait StatePartKind:
         index: StatePartIndex<Self>,
         f: &mut impl fmt::Write,
     ) -> fmt::Result;
-    fn state_index<'a>(
-        state: &'a Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement;
-    fn state_index_mut<'a>(
-        state: &'a mut Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement;
-    fn state_index_fetch_maybe_modified_flag(
-        state: &Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> bool;
-    fn state_index_range_fetch_maybe_modified_flags(
-        state: &Self::State,
-        part_index_range: StatePartIndexRange<Self>,
-    ) -> bool;
-    fn clear_all_maybe_modified_flags(state: &mut Self::State);
-    fn borrowed_state_index<'a, 'b>(
-        state: &'a Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement;
-    fn borrowed_state_index_mut<'a, 'b>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement;
-    fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_indexes: [StatePartIndex<Self>; N],
-    ) -> [&'a mut Self::StateElement; N];
 }
 
 macro_rules! make_state_part_kinds {
@@ -302,7 +272,6 @@ impl StatePartKind for StatePartKindMemories {
     type LayoutData = MemoryData<Interned<BitSlice>>;
     type State = Box<[MemoryData<BitBox>]>;
     type BorrowedState<'a> = &'a mut [MemoryData<BitBox>];
-    type StateElement = MemoryData<BitBox>;
     fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
         layout_data
             .iter()
@@ -328,95 +297,19 @@ impl StatePartKind for StatePartKindMemories {
     ) -> fmt::Result {
         write!(f, "{:#?}", &state.memories[index])
     }
-    fn state_index<'a>(
-        state: &'a Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state[part_index.as_usize()]
-    }
-    fn state_index_mut<'a>(
-        state: &'a mut Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        &mut state[part_index.as_usize()]
-    }
-    fn state_index_fetch_maybe_modified_flag(
-        _state: &Self::State,
-        _part_index: StatePartIndex<Self>,
-    ) -> bool {
-        true
-    }
-    fn state_index_range_fetch_maybe_modified_flags(
-        _state: &Self::State,
-        part_index_range: StatePartIndexRange<Self>,
-    ) -> bool {
-        part_index_range.len.value > 0
-    }
-    fn clear_all_maybe_modified_flags(_state: &mut Self::State) {}
-    fn borrowed_state_index<'a, 'b>(
-        state: &'a Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state[part_index.as_usize()]
-    }
-    fn borrowed_state_index_mut<'a, 'b>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        &mut state[part_index.as_usize()]
-    }
-    fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_indexes: [StatePartIndex<Self>; N],
-    ) -> [&'a mut Self::StateElement; N] {
-        state
-            .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
-            .expect("indexes are disjoint")
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Default)]
-pub(crate) struct StateAndModified<T, M> {
-    pub(crate) state: T,
-    pub(crate) modified: M,
-}
-
-impl<T: Deref<Target = [E]>, M: Deref<Target = [bool]>, E: fmt::Debug> fmt::Debug
-    for StateAndModified<T, M>
-{
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_list()
-            .entries(self.state.iter().zip(self.modified.iter().copied()).map(
-                |(state, modified)| {
-                    fmt::from_fn(move |f| {
-                        state.fmt(f)?;
-                        if modified {
-                            f.write_str(" (modified)")?;
-                        }
-                        Ok(())
-                    })
-                },
-            ))
-            .finish()
-    }
 }
 
 impl StatePartKind for StatePartKindSmallSlots {
     const NAME: &'static str = "SmallSlots";
     type DebugData = SlotDebugData;
     type LayoutData = ();
-    type State = StateAndModified<Box<[Self::StateElement]>, Box<[bool]>>;
+    type State = Box<[SmallUInt]>;
-    type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>;
+    type BorrowedState<'a> = &'a mut [SmallUInt];
-    type StateElement = SmallUInt;
     fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
-        StateAndModified {
+        vec![0; layout_data.len()].into_boxed_slice()
-            state: vec![0; layout_data.len()].into_boxed_slice(),
-            modified: vec![false; layout_data.len()].into_boxed_slice(),
-        }
     }
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
-        let StateAndModified { state, modified } = state;
+        state
-        StateAndModified { state, modified }
     }
     fn part_debug_data<BK: InsnsBuildingKind>(
         state_layout: &StateLayout<BK>,
@@ -437,80 +330,19 @@ impl StatePartKind for StatePartKindSmallSlots {
         write!(f, "{value:#x} {}", value as SmallSInt)?;
         Ok(())
     }
-    fn state_index<'a>(
-        state: &'a Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state.state[part_index.as_usize()]
-    }
-    fn state_index_mut<'a>(
-        state: &'a mut Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        state.modified[part_index.as_usize()] = true;
-        &mut state.state[part_index.as_usize()]
-    }
-    fn state_index_fetch_maybe_modified_flag(
-        state: &Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> bool {
-        state.modified[part_index.as_usize()]
-    }
-    fn state_index_range_fetch_maybe_modified_flags(
-        state: &Self::State,
-        part_index_range: StatePartIndexRange<Self>,
-    ) -> bool {
-        state.modified[part_index_range.start.as_usize()..]
-            [..part_index_range.len.as_index().as_usize()]
-            .contains(&true)
-    }
-    fn clear_all_maybe_modified_flags(state: &mut Self::State) {
-        state.modified.fill(false);
-    }
-    fn borrowed_state_index<'a, 'b>(
-        state: &'a Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state.state[part_index.as_usize()]
-    }
-    fn borrowed_state_index_mut<'a, 'b>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        state.modified[part_index.as_usize()] = true;
-        &mut state.state[part_index.as_usize()]
-    }
-    fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_indexes: [StatePartIndex<Self>; N],
-    ) -> [&'a mut Self::StateElement; N] {
-        for part_index in part_indexes {
-            state.modified[part_index.as_usize()] = true;
-        }
-        state
-            .state
-            .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
-            .expect("indexes are disjoint")
-    }
 }
 
 impl StatePartKind for StatePartKindBigSlots {
     const NAME: &'static str = "BigSlots";
     type DebugData = SlotDebugData;
     type LayoutData = ();
-    type State = StateAndModified<Box<[Self::StateElement]>, Box<[bool]>>;
+    type State = Box<[BigInt]>;
-    type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>;
+    type BorrowedState<'a> = &'a mut [BigInt];
-    type StateElement = BigInt;
     fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
-        let state: Box<[_]> = layout_data.iter().map(|_| BigInt::default()).collect();
+        layout_data.iter().map(|_| BigInt::default()).collect()
-        StateAndModified {
-            modified: vec![false; state.len()].into_boxed_slice(),
-            state,
-        }
     }
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
-        let StateAndModified { state, modified } = state;
+        state
-        StateAndModified { state, modified }
     }
     fn part_debug_data<BK: InsnsBuildingKind>(
         state_layout: &StateLayout<BK>,
@@ -529,80 +361,19 @@ impl StatePartKind for StatePartKindBigSlots {
     ) -> fmt::Result {
         write!(f, "{:#x}", state.big_slots[index])
     }
-    fn state_index<'a>(
-        state: &'a Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state.state[part_index.as_usize()]
-    }
-    fn state_index_mut<'a>(
-        state: &'a mut Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        state.modified[part_index.as_usize()] = true;
-        &mut state.state[part_index.as_usize()]
-    }
-    fn state_index_fetch_maybe_modified_flag(
-        state: &Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> bool {
-        state.modified[part_index.as_usize()]
-    }
-    fn state_index_range_fetch_maybe_modified_flags(
-        state: &Self::State,
-        part_index_range: StatePartIndexRange<Self>,
-    ) -> bool {
-        state.modified[part_index_range.start.as_usize()..]
-            [..part_index_range.len.as_index().as_usize()]
-            .contains(&true)
-    }
-    fn clear_all_maybe_modified_flags(state: &mut Self::State) {
-        state.modified.fill(false);
-    }
-    fn borrowed_state_index<'a, 'b>(
-        state: &'a Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state.state[part_index.as_usize()]
-    }
-    fn borrowed_state_index_mut<'a, 'b>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        state.modified[part_index.as_usize()] = true;
-        &mut state.state[part_index.as_usize()]
-    }
-    fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_indexes: [StatePartIndex<Self>; N],
-    ) -> [&'a mut Self::StateElement; N] {
-        for part_index in part_indexes {
-            state.modified[part_index.as_usize()] = true;
-        }
-        state
-            .state
-            .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
-            .expect("indexes are disjoint")
-    }
 }
 
 impl StatePartKind for StatePartKindSimOnlySlots {
     const NAME: &'static str = "SimOnlySlots";
     type DebugData = SlotDebugData;
     type LayoutData = DynSimOnly;
-    type State = StateAndModified<Box<[Self::StateElement]>, Box<[bool]>>;
+    type State = Box<[DynSimOnlyValue]>;
-    type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>;
+    type BorrowedState<'a> = &'a mut [DynSimOnlyValue];
-    type StateElement = DynSimOnlyValue;
     fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
-        let state: Box<[_]> = layout_data.iter().map(|ty| ty.default_value()).collect();
+        layout_data.iter().map(|ty| ty.default_value()).collect()
-        StateAndModified {
-            modified: vec![false; state.len()].into_boxed_slice(),
-            state,
-        }
     }
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
-        let StateAndModified { state, modified } = state;
+        state
-        StateAndModified { state, modified }
     }
     fn part_debug_data<BK: InsnsBuildingKind>(
         state_layout: &StateLayout<BK>,
@@ -621,61 +392,6 @@ impl StatePartKind for StatePartKindSimOnlySlots {
     ) -> fmt::Result {
         write!(f, "{:?}", state.sim_only_slots[index])
     }
-    fn state_index<'a>(
-        state: &'a Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state.state[part_index.as_usize()]
-    }
-    fn state_index_mut<'a>(
-        state: &'a mut Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        state.modified[part_index.as_usize()] = true;
-        &mut state.state[part_index.as_usize()]
-    }
-    fn state_index_fetch_maybe_modified_flag(
-        state: &Self::State,
-        part_index: StatePartIndex<Self>,
-    ) -> bool {
-        state.modified[part_index.as_usize()]
-    }
-    fn state_index_range_fetch_maybe_modified_flags(
-        state: &Self::State,
-        part_index_range: StatePartIndexRange<Self>,
-    ) -> bool {
-        state.modified[part_index_range.start.as_usize()..]
-            [..part_index_range.len.as_index().as_usize()]
-            .contains(&true)
-    }
-    fn clear_all_maybe_modified_flags(state: &mut Self::State) {
-        state.modified.fill(false);
-    }
-    fn borrowed_state_index<'a, 'b>(
-        state: &'a Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a Self::StateElement {
-        &state.state[part_index.as_usize()]
-    }
-    fn borrowed_state_index_mut<'a, 'b>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_index: StatePartIndex<Self>,
-    ) -> &'a mut Self::StateElement {
-        state.modified[part_index.as_usize()] = true;
-        &mut state.state[part_index.as_usize()]
-    }
-    fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
-        state: &'a mut Self::BorrowedState<'b>,
-        part_indexes: [StatePartIndex<Self>; N],
-    ) -> [&'a mut Self::StateElement; N] {
-        for part_index in part_indexes {
-            state.modified[part_index.as_usize()] = true;
-        }
-        state
-            .state
-            .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
-            .expect("indexes are disjoint")
-    }
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]

crates/fayalite/src/sim/value.rs

@@ -15,23 +15,23 @@ use crate::{
     source_location::SourceLocation,
     ty::{
         CanonicalType, OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSlice,
-        OpaqueSimValueWriter, SimValueDebug, StaticType, Type, TypeProperties,
+        OpaqueSimValueWriter, StaticType, Type, TypeProperties, impl_match_variant_as_self,
-        impl_match_variant_as_self,
     },
     util::{
-        ConstUsize,
+        ConstUsize, HashMap,
         alternating_cell::{AlternatingCell, AlternatingCellMethods},
-        serde_by_id::{SerdeById, SerdeByIdProperties, SerdeByIdTable, SerdeByIdTrait},
     },
 };
 use bitvec::{slice::BitSlice, vec::BitVec};
+use hashbrown::hash_map::Entry;
 use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error as _, ser::Error as _};
 use std::{
     borrow::{Borrow, BorrowMut, Cow},
-    fmt,
+    fmt::{self, Write},
+    hash::{BuildHasher, Hash, Hasher, RandomState},
     num::NonZero,
     ops::{Deref, DerefMut, Index, IndexMut},
-    sync::Arc,
+    sync::{Arc, Mutex},
 };
 
 pub(crate) mod sim_only_value_unsafe;
@@ -551,119 +551,113 @@ impl_sim_value_cmp_as_bool!(AsyncReset);
 
 #[doc(hidden)]
 pub mod match_sim_value {
-    use crate::{sim::value::SimValue, ty::Type};
+    use crate::{
-    use std::ops::{Deref, DerefMut};
+        sim::value::{SimValue, ToSimValue},
-
+        ty::Type,
-    macro_rules! wrapper {
+    };
-        (
-            $(pub struct $wrapper:ident<$T:ident>($inner:ty);)*
-        ) => {
-            $(#[doc(hidden)]
-            pub struct $wrapper<$T>($inner);
-
-            impl<$T> $wrapper<$T> {
-                #[inline(always)]
-                pub fn new(value: $T) -> Self {
-                    Self(<$inner>::new(value))
-                }
-            }
-
-            impl<$T> Deref for $wrapper<$T> {
-                type Target = $inner;
-
-                #[inline(always)]
-                fn deref(&self) -> &Self::Target {
-                    &self.0
-                }
-            }
-
-            impl<$T> DerefMut for $wrapper<$T> {
-                #[inline(always)]
-                fn deref_mut(&mut self) -> &mut Self::Target {
-                    &mut self.0
-                }
-            })*
-        };
-    }
-
-    wrapper! {
-        pub struct MatchSimValueHelperCheckSimValue<T>(MatchSimValueHelperCheckMutSimValue<T>);
-        pub struct MatchSimValueHelperCheckMutSimValue<T>(MatchSimValueHelperCheckRefSimValue<T>);
-        pub struct MatchSimValueHelperCheckRefSimValue<T>(MatchSimValueHelperCheckRefRefSimValue<T>);
-        pub struct MatchSimValueHelperCheckRefRefSimValue<T>(MatchSimValueHelperCheckRefMutSimValue<T>);
-        pub struct MatchSimValueHelperCheckRefMutSimValue<T>(MatchSimValueHelperCheckMutRefSimValue<T>);
-        pub struct MatchSimValueHelperCheckMutRefSimValue<T>(MatchSimValueHelperCheckMutMutSimValue<T>);
-        pub struct MatchSimValueHelperCheckMutMutSimValue<T>(MatchSimValueHelperIdentity<T>);
-    }
-
-    impl<T: Type> MatchSimValueHelperCheckSimValue<SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> T::SimValue {
-            SimValue::into_value(self.take())
-        }
-    }
-
-    impl<'a, T: Type> MatchSimValueHelperCheckMutSimValue<&'a mut SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue {
-            self.take()
-        }
-    }
-
-    impl<'a, T: Type> MatchSimValueHelperCheckRefSimValue<&'a SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue {
-            self.take()
-        }
-    }
-
-    impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefRefSimValue<&'a &'b SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue {
-            self.take()
-        }
-    }
-
-    impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefMutSimValue<&'a &'b mut SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue {
-            self.take()
-        }
-    }
-
-    impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutRefSimValue<&'a mut &'b SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue {
-            self.take()
-        }
-    }
-
-    impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutMutSimValue<&'a mut &'b mut SimValue<T>> {
-        #[inline(always)]
-        pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue {
-            self.take()
-        }
-    }
 
     #[doc(hidden)]
-    pub struct MatchSimValueHelperIdentity<T>(Option<T>);
+    pub struct MatchSimValueHelper<T>(Option<T>);
 
-    impl<T> MatchSimValueHelperIdentity<T> {
+    impl<T> MatchSimValueHelper<T> {
-        fn new(v: T) -> Self {
+        pub fn new(v: T) -> Self {
             Self(Some(v))
         }
-        #[inline(always)]
+    }
-        fn take(&mut self) -> T {
+
-            self.0.take().expect("known to be Some")
+    #[doc(hidden)]
+    pub trait MatchSimValue {
+        type MatchValue;
+
+        /// use `self` so it comes first in the method resolution order
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue
+        where
+            Self: Sized;
+    }
+
+    impl<T: Type> MatchSimValue for MatchSimValueHelper<SimValue<T>> {
+        type MatchValue = T::SimValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            SimValue::into_value(self.0.expect("should be Some"))
         }
-        #[inline(always)]
+    }
-        pub fn __fayalite_match_sim_value(&mut self) -> T {
+
-            self.take()
+    impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a SimValue<T>> {
+        type MatchValue = &'a T::SimValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            SimValue::value(self.0.expect("should be Some"))
+        }
+    }
+
+    impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a mut SimValue<T>> {
+        type MatchValue = &'a mut T::SimValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            SimValue::value_mut(self.0.expect("should be Some"))
+        }
+    }
+
+    impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ &'a T>
+    where
+        MatchSimValueHelper<&'a T>: MatchSimValue,
+    {
+        type MatchValue = <MatchSimValueHelper<&'a T> as MatchSimValue>::MatchValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v)))
+        }
+    }
+
+    impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ mut &'a T>
+    where
+        MatchSimValueHelper<&'a T>: MatchSimValue,
+    {
+        type MatchValue = <MatchSimValueHelper<&'a T> as MatchSimValue>::MatchValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v)))
+        }
+    }
+
+    impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a &'_ mut T>
+    where
+        MatchSimValueHelper<&'a T>: MatchSimValue,
+    {
+        type MatchValue = <MatchSimValueHelper<&'a T> as MatchSimValue>::MatchValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &**v)))
+        }
+    }
+
+    impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a mut &'_ mut T>
+    where
+        MatchSimValueHelper<&'a mut T>: MatchSimValue,
+    {
+        type MatchValue = <MatchSimValueHelper<&'a mut T> as MatchSimValue>::MatchValue;
+
+        fn __fayalite_match_sim_value(self) -> Self::MatchValue {
+            MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &mut **v)))
         }
     }
 
     #[doc(hidden)]
-    pub type MatchSimValueHelper<T> = MatchSimValueHelperCheckSimValue<T>;
+    pub trait MatchSimValueFallback {
+        type MatchValue;
+
+        /// use `&mut self` so it comes later in the method resolution order than MatchSimValue
+        fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue;
+    }
+
+    impl<T: ToSimValue> MatchSimValueFallback for MatchSimValueHelper<T> {
+        type MatchValue = <T::Type as Type>::SimValue;
+
+        fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue {
+            SimValue::into_value(self.0.take().expect("should be Some").into_sim_value())
+        }
+    }
 }
 
 pub trait ToSimValue: ToSimValueWithType<<Self as ValueType>::Type> + ValueType {
@@ -1097,8 +1091,7 @@ impl ToSimValueWithType<CanonicalType> for bool {
             | CanonicalType::Enum(_)
             | CanonicalType::Bundle(_)
             | CanonicalType::PhantomConst(_)
-            | CanonicalType::DynSimOnly(_)
+            | CanonicalType::DynSimOnly(_) => {
-            | CanonicalType::TraceAsString(_) => {
                 panic!("can't create SimValue from bool: expected value of type: {ty:?}");
             }
             CanonicalType::Bool(_)
@@ -1227,17 +1220,80 @@ macro_rules! impl_to_sim_value_for_int_value {
 impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
 impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
 
-impl SerdeByIdTrait for DynSimOnly {
+#[derive(Default)]
-    fn serde_by_id_properties(&self) -> SerdeByIdProperties<Self> {
+struct DynSimOnlySerdeTableRest {
-        self.serde_by_id_properties_inner()
+    from_serde: HashMap<DynSimOnlySerdeId, DynSimOnly>,
-    }
+    serde_id_random_state: RandomState,
+    buffer: String,
+}
 
-    fn static_table() -> &'static SerdeByIdTable<Self> {
+impl DynSimOnlySerdeTableRest {
-        static TABLE: SerdeByIdTable<DynSimOnly> = SerdeByIdTable::new();
+    #[cold]
-        &TABLE
+    fn add_new(&mut self, ty: DynSimOnly) -> DynSimOnlySerdeId {
+        let mut try_number = 0u64;
+        let mut hasher = self.serde_id_random_state.build_hasher();
+        // extract more bits of randomness from TypeId -- its Hash impl only hashes 64-bits
+        write!(self.buffer, "{:?}", ty.type_id()).expect("shouldn't ever fail");
+        self.buffer.hash(&mut hasher);
+        loop {
+            let mut hasher = hasher.clone();
+            try_number.hash(&mut hasher);
+            try_number += 1;
+            let retval = DynSimOnlySerdeId(std::array::from_fn(|i| {
+                let mut hasher = hasher.clone();
+                i.hash(&mut hasher);
+                hasher.finish() as u32
+            }));
+            match self.from_serde.entry(retval) {
+                Entry::Occupied(_) => continue,
+                Entry::Vacant(e) => {
+                    e.insert(ty);
+                    return retval;
+                }
+            }
+        }
     }
+}
 
-    const NAME: &'static str = "DynSimOnly";
+#[derive(Default)]
+struct DynSimOnlySerdeTable {
+    to_serde: HashMap<DynSimOnly, DynSimOnlySerdeId>,
+    rest: DynSimOnlySerdeTableRest,
+}
+
+static DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE: Mutex<Option<DynSimOnlySerdeTable>> = Mutex::new(None);
+
+#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
+#[serde(transparent)]
+struct DynSimOnlySerdeId([u32; 4]);
+
+impl From<DynSimOnly> for DynSimOnlySerdeId {
+    fn from(ty: DynSimOnly) -> Self {
+        let mut locked = DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE
+            .lock()
+            .expect("shouldn't be poison");
+        let DynSimOnlySerdeTable { to_serde, rest } = locked.get_or_insert_default();
+        match to_serde.entry(ty) {
+            Entry::Occupied(occupied_entry) => *occupied_entry.get(),
+            Entry::Vacant(vacant_entry) => *vacant_entry.insert(rest.add_new(ty)),
+        }
+    }
+}
+
+impl DynSimOnlySerdeId {
+    fn ty(self) -> Option<DynSimOnly> {
+        let locked = DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE
+            .lock()
+            .expect("shouldn't be poison");
+        Some(*locked.as_ref()?.rest.from_serde.get(&self)?)
+    }
+}
+
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
+struct DynSimOnlySerde<'a> {
+    random_id: DynSimOnlySerdeId,
+    #[serde(borrow)]
+    type_name: Cow<'a, str>,
 }
 
 impl Serialize for DynSimOnly {
@@ -1245,7 +1301,11 @@ impl Serialize for DynSimOnly {
     where
         S: Serializer,
     {
-        SerdeById { inner: *self }.serialize(serializer)
+        DynSimOnlySerde {
+            random_id: (*self).into(),
+            type_name: Cow::Borrowed(self.type_name()),
+        }
+        .serialize(serializer)
     }
 }
 
@@ -1254,7 +1314,16 @@ impl<'de> Deserialize<'de> for DynSimOnly {
     where
         D: Deserializer<'de>,
     {
-        Ok(SerdeById::deserialize(deserializer)?.inner)
+        let deserialized = DynSimOnlySerde::deserialize(deserializer)?;
+        let retval = deserialized
+            .random_id
+            .ty()
+            .filter(|ty| ty.type_name() == deserialized.type_name);
+        retval.ok_or_else(|| {
+            D::Error::custom(
+                "doesn't match any DynSimOnly that was serialized this time this program was run",
+            )
+        })
     }
 }
 
@@ -1325,15 +1394,6 @@ impl Type for DynSimOnly {
     }
 }
 
-impl SimValueDebug for DynSimOnly {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl<T: SimOnlyValueTrait> Type for SimOnly<T> {
     type BaseType = DynSimOnly;
     type MaskType = Bool;
@@ -1399,15 +1459,6 @@ impl<T: SimOnlyValueTrait> Type for SimOnly<T> {
     }
 }
 
-impl<T: SimOnlyValueTrait> SimValueDebug for SimOnly<T> {
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        fmt::Debug::fmt(value, f)
-    }
-}
-
 impl<T: SimOnlyValueTrait> StaticType for SimOnly<T> {
     const TYPE: Self = Self::new();
 

crates/fayalite/src/sim/value/sim_only_value_unsafe.rs

@@ -3,10 +3,7 @@
 
 //! `unsafe` parts of [`DynSimOnlyValue`]
 
-use crate::{
+use crate::expr::{ValueType, value_category::ValueCategoryValue};
-    expr::{ValueType, value_category::ValueCategoryValue},
-    util::serde_by_id::SerdeByIdProperties,
-};
 use serde::{Serialize, de::DeserializeOwned};
 use std::{
     any::{self, TypeId},
@@ -36,7 +33,6 @@ unsafe trait DynSimOnlyTrait: 'static + Send + Sync {
         &self,
         json_str: &str,
     ) -> serde_json::Result<Rc<dyn DynSimOnlyValueTrait>>;
-    fn serde_by_id_properties_inner(&self) -> SerdeByIdProperties<DynSimOnly>;
 }
 
 /// Safety: `type_id_dyn` is implemented correctly
@@ -59,9 +55,6 @@ unsafe impl<T: SimOnlyValueTrait> DynSimOnlyTrait for SimOnly<T> {
     ) -> serde_json::Result<Rc<dyn DynSimOnlyValueTrait>> {
         Ok(Rc::<T>::new(serde_json::from_str(json_str)?))
     }
-    fn serde_by_id_properties_inner(&self) -> SerdeByIdProperties<DynSimOnly> {
-        SerdeByIdProperties::of::<T>()
-    }
 }
 
 /// Safety:
@@ -158,9 +151,6 @@ impl DynSimOnly {
     pub fn default_value(self) -> DynSimOnlyValue {
         DynSimOnlyValue(self.ty.default_value())
     }
-    pub(super) fn serde_by_id_properties_inner(self) -> SerdeByIdProperties<Self> {
-        self.ty.serde_by_id_properties_inner()
-    }
 }
 
 impl PartialEq for DynSimOnly {

crates/fayalite/src/sim/vcd.rs

@@ -9,15 +9,14 @@ use crate::{
     prelude::PhantomConst,
     sim::{
         TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
-        TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceFormalInput,
+        TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
-        TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation,
+        TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule,
-        TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar,
+        TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar, TraceScalarId,
-        TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceTraceAsString, TraceUInt,
+        TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, TraceWriter,
-        TraceWire, TraceWriter, TraceWriterDecls,
+        TraceWriterDecls,
         time::{SimDuration, SimInstant},
         value::DynSimOnlyValue,
     },
-    ty::{OpaqueSimValueSlice, TraceAsString},
     util::HashMap,
 };
 use bitvec::{order::Lsb0, slice::BitSlice};
@@ -332,7 +331,6 @@ impl WriteTrace for TraceScalar {
             Self::AsyncReset(v) => v.write_trace(writer, arg),
             Self::PhantomConst(v) => v.write_trace(writer, arg),
             Self::SimOnly(v) => v.write_trace(writer, arg),
-            Self::TraceAsString(v) => v.write_trace(writer, arg),
         }
     }
 }
@@ -728,34 +726,6 @@ impl WriteTrace for TraceSimOnly {
     }
 }
 
-impl WriteTrace for TraceTraceAsString {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgInType {
-            source_var_type: _,
-            sink_var_type: _,
-            duplex_var_type: _,
-            properties,
-            scope,
-        } = arg.in_type();
-        let Self {
-            location,
-            name,
-            ty,
-            flow: _,
-        } = self;
-        write_vcd_var(
-            properties,
-            scope,
-            MemoryElementPartBody::TraceAsString { ty },
-            writer,
-            "string",
-            1,
-            location,
-            name,
-        )
-    }
-}
-
 impl WriteTrace for TraceScope {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
         match self {
@@ -766,7 +736,6 @@ impl WriteTrace for TraceScope {
             Self::Wire(v) => v.write_trace(writer, arg),
             Self::Reg(v) => v.write_trace(writer, arg),
             Self::ModuleIO(v) => v.write_trace(writer, arg),
-            Self::FormalInput(v) => v.write_trace(writer, arg),
             Self::Bundle(v) => v.write_trace(writer, arg),
             Self::Array(v) => v.write_trace(writer, arg),
             Self::EnumWithFields(v) => v.write_trace(writer, arg),
@@ -964,27 +933,6 @@ impl WriteTrace for TraceModuleIO {
     }
 }
 
-impl WriteTrace for TraceFormalInput {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties, scope } = arg.module_body();
-        let Self {
-            name: _,
-            child,
-            formal_input: _,
-        } = self;
-        child.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "wire",
-                sink_var_type: "wire",
-                duplex_var_type: "wire",
-                properties,
-                scope: Some(scope),
-            },
-        )
-    }
-}
-
 impl WriteTrace for TraceBundle {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
         let ArgInType {
@@ -1145,7 +1093,6 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
             finished_init: false,
             timescale,
             properties,
-            trace_as_string_buf: String::with_capacity(256),
         })
     }
 }
@@ -1153,7 +1100,6 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
 enum MemoryElementPartBody {
     Scalar,
     EnumDiscriminant { ty: Enum },
-    TraceAsString { ty: TraceAsString },
 }
 
 struct MemoryElementPart {
@@ -1271,7 +1217,6 @@ pub struct VcdWriter<W: io::Write + 'static> {
     finished_init: bool,
     timescale: SimDuration,
     properties: VcdWriterProperties,
-    trace_as_string_buf: String,
 }
 
 impl<W: io::Write + 'static> VcdWriter<W> {
@@ -1381,21 +1326,6 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
                             .built_scalar_id_to_vcd_id(first_id + element_index),
                     )?
                 }
-                MemoryElementPartBody::TraceAsString { ty } => {
-                    self.trace_as_string_buf.clear();
-                    ty.trace_fmt_append_to_string(
-                        &mut self.trace_as_string_buf,
-                        OpaqueSimValueSlice::from_bitslice(&element_data[start..start + len]),
-                    );
-                    write_string_value_change(
-                        &mut self.writer,
-                        &self.trace_as_string_buf,
-                        self.properties
-                            .scalar_id_to_vcd_id_map
-                            .built_scalar_id_to_vcd_id(first_id + element_index),
-                    )?;
-                    self.trace_as_string_buf.clear();
-                }
             }
         }
         Ok(())
@@ -1489,16 +1419,6 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
                 .built_scalar_id_to_vcd_id(id.as_usize()),
         )
     }
-
-    fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error> {
-        write_string_value_change(
-            &mut self.writer,
-            value,
-            self.properties
-                .scalar_id_to_vcd_id_map
-                .built_scalar_id_to_vcd_id(id.as_usize()),
-        )
-    }
 }
 
 impl<W: io::Write> fmt::Debug for VcdWriter<W> {
@@ -1508,7 +1428,6 @@ impl<W: io::Write> fmt::Debug for VcdWriter<W> {
             finished_init,
             timescale,
             properties: _,
-            trace_as_string_buf: _,
         } = self;
         f.debug_struct("VcdWriter")
             .field("finished_init", finished_init)

crates/fayalite/src/testing.rs

@@ -12,13 +12,11 @@ use crate::{
     bundle::BundleType,
     firrtl::ExportOptions,
     module::Module,
-    sim::{Simulation, vcd::VcdWriterDecls},
+    util::HashMap,
-    util::{HashMap, RcWriter},
 };
 use serde::{Deserialize, Serialize};
 use std::{
     fmt::{self, Write},
-    panic::Location,
     path::{Path, PathBuf},
     process::Command,
     sync::{Mutex, OnceLock},
@@ -224,190 +222,3 @@ pub fn assert_formal<M: AsRef<Module<T>>, T: BundleType>(
     )
     .expect("testing::assert_formal() failed");
 }
-
-pub struct CheckedVcdOutput {
-    writer: Option<RcWriter>,
-    expected_path: PathBuf,
-    expected_contents: Result<String, (Option<PathBuf>, std::io::Error)>,
-    location: &'static Location<'static>,
-}
-
-impl CheckedVcdOutput {
-    #[must_use]
-    #[track_caller]
-    pub fn new<T: BundleType>(sim: &mut Simulation<T>, expected_path: PathBuf) -> Self {
-        let writer = RcWriter::default();
-        sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-        Self {
-            writer: Some(writer),
-            expected_contents: std::fs::read_to_string(&expected_path).map_err(|e| {
-                eprintln!(
-                    "error: failed to read expected VCD from: {}",
-                    expected_path.display(),
-                );
-                (std::env::current_dir().ok(), e)
-            }),
-            expected_path,
-            location: Location::caller(),
-        }
-    }
-    #[must_use]
-    #[track_caller]
-    #[doc(hidden)]
-    pub fn __checked_vcd_output_macro_helper<T: BundleType>(
-        sim: &mut Simulation<T>,
-        cargo_manifest_dir: &'static str,
-        path: &'static str,
-    ) -> Self {
-        Self::new(sim, Path::new(cargo_manifest_dir).join(path))
-    }
-    pub fn with_vcd_output<R>(&self, f: impl FnOnce(&str) -> R) -> R {
-        let Some(writer) = &self.writer else {
-            unreachable!();
-        };
-        writer.clone().borrow(|output| {
-            let Ok(output) = str::from_utf8(output) else {
-                unreachable!("VcdWriter writes valid UTF-8");
-            };
-            f(output)
-        })
-    }
-    #[track_caller]
-    pub fn finish(mut self) {
-        let Ok(()) = self.finish_impl(|msg| panic!("{msg}"));
-    }
-    fn finish_impl<E>(
-        &mut self,
-        error: impl FnOnce(std::fmt::Arguments<'_>) -> E,
-    ) -> Result<(), E> {
-        let Self {
-            writer: Some(writer),
-            expected_path,
-            expected_contents,
-            location,
-        } = self
-        else {
-            // already finished
-            return Ok(());
-        };
-        let Ok(vcd) = String::from_utf8(writer.take()) else {
-            unreachable!("VcdWriter writes valid UTF-8");
-        };
-        let expected_path_d = expected_path.display();
-        if expected_contents
-            .as_ref()
-            .is_ok_and(|expected_contents| *expected_contents == vcd)
-        {
-            // avoid written output from being split from threads interleaving writes to stdout
-            let _stdout = std::io::stderr().lock();
-            // use println to get output captured by tests
-            println!("\n{location}: generated VCD matches the expected VCD in {expected_path_d}");
-            return Ok(());
-        }
-        // avoid written output from being split from threads interleaving writes to stderr
-        let _stderr = std::io::stderr().lock();
-        let error = |msg: std::fmt::Arguments<'_>| {
-            // print msg at both beginning and end so it's easier to find when the vcd is huge
-            Err(error(format_args!(
-                "\n{msg}####### VCD:\n{vcd}\n#######\n{msg}"
-            )))
-        };
-        let error = |msg: std::fmt::Arguments<'_>| match &*expected_contents {
-            Ok(_) => error(format_args!(
-                "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\
-                {msg}",
-            )),
-            Err((Some(current_dir), e)) => error(format_args!(
-                "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\
-                error: failed to read: {e}\n\
-                current dir: {current_dir}\n\
-                {msg}",
-                current_dir = current_dir.display(),
-            )),
-            Err((None, e)) => error(format_args!(
-                "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\
-                error: failed to read: {e}\n\
-                {msg}",
-            )),
-        };
-        const OVERWRITE_VAR_NAME: &str = "OVERWRITE_EXPECTED_VCD";
-        const OVERWRITE_VAR_VALUE: &str = "overwrite";
-        match std::env::var_os(OVERWRITE_VAR_NAME) {
-            Some(v) if v == OVERWRITE_VAR_VALUE => match std::fs::write(&expected_path, &vcd) {
-                Ok(()) => error(format_args!(
-                    "warning: since `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}` is set -- writing the generated VCD to {expected_path_d}\n"
-                )),
-                Err(e) => error(format_args!(
-                    "error: since `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}` is set -- tried to write the generated VCD to {expected_path_d}\n\
-                    error: failed to write: {e}"
-                )),
-            },
-            _ => error(format_args!(
-                "note: rerun the test with the environment variable `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}`\n\
-                to update the expected output to match the generated output.\n"
-            )),
-        }
-    }
-}
-
-impl Drop for CheckedVcdOutput {
-    #[track_caller]
-    fn drop(&mut self) {
-        let _ = self.finish_impl(|msg| {
-            if std::thread::panicking() {
-                eprintln!("{msg}"); // use eprintln to get output captured by tests
-            } else {
-                panic!("{msg}");
-            }
-        });
-    }
-}
-
-#[macro_export]
-/// Use in tests to check that [`Simulation`] generates the expected VCD traces, by comparing to a `.vcd` file containing the expected traces.
-///
-/// Use like so:
-/// ```
-/// # use fayalite::prelude::*;
-/// #
-/// # #[hdl_module]
-/// # fn my_module() {
-/// #     #[hdl]
-/// #     let a: UInt<8> = m.input();
-/// #     #[hdl]
-/// #     let b: UInt<8> = m.output();
-/// #     connect(b, 0u8);
-/// #     #[hdl]
-/// #     if a.cmp_eq(100u8) {
-/// #         connect(b, 42u8);
-/// #     }
-/// # }
-/// // inside your #[test] fn my_test():
-///
-/// // get the module to simulate:
-/// let m = my_module();
-/// // create a simulation of the module:
-/// let mut sim = Simulation::new(m);
-/// // set up the expected VCD traces, the given .vcd path is relative to env!("CARGO_MANIFEST_DIR")
-/// let _checked_vcd_output = checked_vcd_output!(
-///     &mut sim,
-///     "tests/expected/my_test.vcd",
-/// );
-/// // now run the simulation like normal:
-/// sim.write(sim.io().a, 0u8);
-/// assert_eq!(sim.read(sim.io().b).as_int(), 0);
-/// sim.advance_time(SimDuration::from_micros(1));
-/// sim.write(sim.io().a, 100u8);
-/// assert_eq!(sim.read(sim.io().b).as_int(), 42);
-/// ```
-macro_rules! checked_vcd_output {
-    ($sim:expr, $path_relative_to_manifest_dir:expr $(,)?) => {
-        $crate::testing::CheckedVcdOutput::__checked_vcd_output_macro_helper(
-            $sim,
-            $crate::__std::env!("CARGO_MANIFEST_DIR"),
-            $crate::__std::concat!($path_relative_to_manifest_dir),
-        )
-    };
-}
-
-pub use checked_vcd_output;

crates/fayalite/src/ty/serde_impls.rs

@@ -12,8 +12,7 @@ use crate::{
     prelude::PhantomConst,
     reset::{AsyncReset, Reset, SyncReset},
     sim::value::DynSimOnly,
-    ty::{BaseType, CanonicalType, TraceAsString, TraceAsStringTrait},
+    ty::{BaseType, CanonicalType},
-    util::serde_by_id::SerdeById,
 };
 use serde::{Deserialize, Deserializer, Serialize, Serializer};
 
@@ -39,7 +38,6 @@ impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for SerdePhantomConst<
 
 #[derive(Serialize, Deserialize)]
 #[serde(rename = "CanonicalType")]
-#[expect(private_interfaces)]
 pub(crate) enum SerdeCanonicalType<
     ArrayElement = CanonicalType,
     ThePhantomConst = SerdePhantomConst<Interned<PhantomConstCanonicalValue>>,
@@ -67,10 +65,6 @@ pub(crate) enum SerdeCanonicalType<
     Clock,
     PhantomConst(ThePhantomConst),
     DynSimOnly(DynSimOnly),
-    TraceAsString {
-        inner_ty: Interned<CanonicalType>,
-        trace_as_string: SerdeById<Interned<dyn TraceAsStringTrait>>,
-    },
 }
 
 impl<ArrayElement, PhantomConstInner> SerdeCanonicalType<ArrayElement, PhantomConstInner> {
@@ -88,7 +82,6 @@ impl<ArrayElement, PhantomConstInner> SerdeCanonicalType<ArrayElement, PhantomCo
             Self::Clock => "a Clock",
             Self::PhantomConst(_) => "a PhantomConst",
             Self::DynSimOnly(_) => "a SimOnlyValue",
-            Self::TraceAsString { .. } => "a TraceAsString",
         }
     }
 }
@@ -116,15 +109,6 @@ impl<T: BaseType> From<T> for SerdeCanonicalType {
             CanonicalType::Clock(Clock {}) => Self::Clock,
             CanonicalType::PhantomConst(ty) => Self::PhantomConst(SerdePhantomConst(ty.get())),
             CanonicalType::DynSimOnly(ty) => Self::DynSimOnly(ty),
-            CanonicalType::TraceAsString(TraceAsString {
-                inner_ty,
-                trace_as_string,
-            }) => Self::TraceAsString {
-                inner_ty: inner_ty.interned(),
-                trace_as_string: SerdeById {
-                    inner: trace_as_string.interned(),
-                },
-            },
         }
     }
 }
@@ -146,13 +130,6 @@ impl From<SerdeCanonicalType> for CanonicalType {
                 Self::PhantomConst(PhantomConst::new_interned(value.0))
             }
             SerdeCanonicalType::DynSimOnly(value) => Self::DynSimOnly(value),
-            SerdeCanonicalType::TraceAsString {
-                inner_ty,
-                trace_as_string,
-            } => Self::TraceAsString(TraceAsString {
-                inner_ty: crate::intern::LazyInterned::Interned(inner_ty),
-                trace_as_string: crate::intern::LazyInterned::Interned(trace_as_string.inner),
-            }),
         }
     }
 }

crates/fayalite/src/util.rs

@@ -46,4 +46,3 @@ pub(crate) use misc::{InternedStrCompareAsStr, chain, copy_le_bytes_to_bitslice}
 pub mod job_server;
 pub mod prefix_sum;
 pub mod ready_valid;
-pub(crate) mod serde_by_id;

crates/fayalite/src/util/ready_valid.rs

@@ -241,13 +241,15 @@ mod tests {
         /// happens to be in phase with the offending input or output).
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
+            #[hdl]
+            let clk: Clock = m.input();
             #[hdl]
             let cd = wire();
             connect(
                 cd,
                 #[hdl]
                 ClockDomain {
-                    clk: formal_global_clock(),
+                    clk,
                     rst: formal_reset().to_reset(),
                 },
             );
@@ -278,7 +280,7 @@ mod tests {
             #[hdl]
             let index_to_check = wire(index_ty);
             connect(index_to_check, any_const(index_ty));
-            hdl_assume(cd.clk, index_to_check.cmp_lt(capacity.get()), "");
+            hdl_assume(clk, index_to_check.cmp_lt(capacity.get()), "");
 
             // instantiate and connect the queue
             #[hdl]
@@ -298,13 +300,13 @@ mod tests {
             let expected_count_reg = reg_builder().clock_domain(cd).reset(count_ty.zero());
             #[hdl]
             if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
-                hdl_assert(cd.clk, expected_count_reg.cmp_ne(capacity.get()), "");
+                hdl_assert(clk, expected_count_reg.cmp_ne(capacity.get()), "");
                 connect_any(expected_count_reg, expected_count_reg + 1u8);
             } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
-                hdl_assert(cd.clk, expected_count_reg.cmp_ne(count_ty.zero()), "");
+                hdl_assert(clk, expected_count_reg.cmp_ne(count_ty.zero()), "");
                 connect_any(expected_count_reg, expected_count_reg - 1u8);
             }
-            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
+            hdl_assert(clk, expected_count_reg.cmp_eq(dut.count), "");
 
             // keep an independent write index into the FIFO's circular buffer
             #[hdl]
@@ -372,7 +374,7 @@ mod tests {
                     match inp_firing_data {
                         // ... and we are not receiving data, then we must not
                         // transmit any data.
-                        HdlNone => hdl_assert(cd.clk, HdlOption::is_none(out_firing_data), ""),
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(out_firing_data), ""),
                         // If we are indeed receiving some data...
                         HdlSome(data_in) => {
                             #[hdl]
@@ -380,9 +382,7 @@ mod tests {
                                 // ... and transmitting at the same time, we
                                 // must be transmitting the input data itself,
                                 // since the holding register is empty.
-                                HdlSome(data_out) => {
+                                HdlSome(data_out) => hdl_assert(clk, data_out.cmp_eq(data_in), ""),
-                                    hdl_assert(cd.clk, data_out.cmp_eq(data_in), "")
-                                }
                                 // If we are receiving, but not transmitting,
                                 // store the received data in the holding
                                 // register.
@@ -397,11 +397,11 @@ mod tests {
                     match out_firing_data {
                         // ... and we are not transmitting it, we cannot
                         // receive any more data.
-                        HdlNone => hdl_assert(cd.clk, HdlOption::is_none(inp_firing_data), ""),
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(inp_firing_data), ""),
                         // If we are transmitting a previously stored value...
                         HdlSome(data_out) => {
                             // ... it must be the same data we stored earlier.
-                            hdl_assert(cd.clk, data_out.cmp_eq(stored), "");
+                            hdl_assert(clk, data_out.cmp_eq(stored), "");
                             // Also, accept new data, if any. Otherwise,
                             // let the holding register become empty.
                             connect(stored_reg, inp_firing_data);
@@ -417,17 +417,17 @@ mod tests {
             connect(dut.dbg.index_to_check, index_to_check);
             #[hdl]
             if let HdlSome(stored) = stored_reg {
-                hdl_assert(cd.clk, stored.cmp_eq(dut.dbg.stored), "");
+                hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), "");
             }
 
             // sync the read and write indices
-            hdl_assert(cd.clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
+            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
-            hdl_assert(cd.clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
+            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
 
             // the indices should never go past the capacity, but induction
             // doesn't know that...
-            hdl_assert(cd.clk, inp_index_reg.cmp_lt(capacity.get()), "");
+            hdl_assert(clk, inp_index_reg.cmp_lt(capacity.get()), "");
-            hdl_assert(cd.clk, out_index_reg.cmp_lt(capacity.get()), "");
+            hdl_assert(clk, out_index_reg.cmp_lt(capacity.get()), "");
 
             // strongly constrain the state of the holding register
             //
@@ -455,7 +455,7 @@ mod tests {
             connect(expected_stored, pending_reads.cmp_lt(dut.count));
             // sync with the state of the holding register
             hdl_assert(
-                cd.clk,
+                clk,
                 expected_stored.cmp_eq(HdlOption::is_some(stored_reg)),
                 "",
             );

crates/fayalite/src/util/serde_by_id.rs

@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-
-use crate::util::HashMap;
-use hashbrown::hash_map::Entry;
-use serde::{Deserialize, Serialize, de::Error};
-use std::{
-    any::TypeId,
-    borrow::Cow,
-    fmt::Write,
-    hash::{BuildHasher, Hash, Hasher},
-    marker::PhantomData,
-    sync::Mutex,
-};
-
-pub(crate) struct SerdeByIdProperties<T: SerdeByIdTrait> {
-    type_id: TypeId,
-    type_name: &'static str,
-    _phantom: PhantomData<fn(T) -> T>,
-}
-
-impl<T: SerdeByIdTrait> Clone for SerdeByIdProperties<T> {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-
-impl<T: SerdeByIdTrait> Copy for SerdeByIdProperties<T> {}
-
-impl<T: SerdeByIdTrait> SerdeByIdProperties<T> {
-    pub fn of<U: ?Sized + 'static>() -> Self {
-        Self {
-            type_id: TypeId::of::<U>(),
-            type_name: std::any::type_name::<U>(),
-            _phantom: PhantomData,
-        }
-    }
-}
-
-pub(crate) trait SerdeByIdTrait: Hash + Eq + Clone + 'static + Send {
-    fn serde_by_id_properties(&self) -> SerdeByIdProperties<Self>;
-    fn static_table() -> &'static SerdeByIdTable<Self>;
-    const NAME: &'static str;
-}
-
-#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
-#[serde(transparent)]
-struct SerdeRandomId([u32; 4]);
-
-#[derive(Serialize, Deserialize)]
-pub(crate) struct SerdeId<'a, T: SerdeByIdTrait> {
-    random_id: SerdeRandomId,
-    #[serde(borrow)]
-    type_name: Cow<'a, str>,
-    #[serde(skip)]
-    _phantom: PhantomData<fn(T) -> T>,
-}
-
-impl<'a, T: SerdeByIdTrait> Clone for SerdeId<'a, T> {
-    fn clone(&self) -> Self {
-        Self {
-            random_id: self.random_id,
-            type_name: self.type_name.clone(),
-            _phantom: PhantomData,
-        }
-    }
-}
-
-impl<'a, T: SerdeByIdTrait> Eq for SerdeId<'a, T> {}
-
-impl<'a, 'b, T: SerdeByIdTrait> PartialEq<SerdeId<'b, T>> for SerdeId<'a, T> {
-    fn eq(&self, other: &SerdeId<'b, T>) -> bool {
-        let Self {
-            random_id,
-            type_name,
-            _phantom: _,
-        } = self;
-        *random_id == other.random_id && *type_name == other.type_name
-    }
-}
-
-impl<'a, T: SerdeByIdTrait> Hash for SerdeId<'a, T> {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        let Self {
-            random_id,
-            type_name: _,
-            _phantom: _,
-        } = self;
-        random_id.hash(state);
-    }
-}
-
-struct SerdeByIdTableRest<T: SerdeByIdTrait> {
-    from_serde: HashMap<SerdeId<'static, T>, T>,
-    serde_id_random_state: std::hash::RandomState,
-    buffer: String,
-}
-
-impl<T: SerdeByIdTrait> Default for SerdeByIdTableRest<T> {
-    fn default() -> Self {
-        Self {
-            from_serde: Default::default(),
-            serde_id_random_state: Default::default(),
-            buffer: Default::default(),
-        }
-    }
-}
-
-impl<T: SerdeByIdTrait> SerdeByIdTableRest<T> {
-    fn add_new(&mut self, value: T) -> SerdeId<'static, T> {
-        let properties = value.serde_by_id_properties();
-        let mut try_number = 0u64;
-        let mut hasher = self.serde_id_random_state.build_hasher();
-        // extract more bits of randomness from TypeId -- its Hash impl only hashes 64-bits
-        write!(self.buffer, "{:?}", properties.type_id).expect("shouldn't ever fail");
-        self.buffer.hash(&mut hasher);
-        loop {
-            let mut hasher = hasher.clone();
-            try_number.hash(&mut hasher);
-            try_number += 1;
-            let key = SerdeId {
-                random_id: SerdeRandomId(std::array::from_fn(|i| {
-                    let mut hasher = hasher.clone();
-                    i.hash(&mut hasher);
-                    hasher.finish() as u32
-                })),
-                type_name: Cow::Borrowed(properties.type_name),
-                _phantom: PhantomData,
-            };
-            match self.from_serde.entry(key) {
-                Entry::Occupied(_) => continue,
-                Entry::Vacant(e) => {
-                    let key = e.key().clone();
-                    e.insert(value);
-                    return key;
-                }
-            }
-        }
-    }
-}
-
-pub(crate) struct SerdeByIdTableMut<T: SerdeByIdTrait> {
-    to_serde: HashMap<T, SerdeId<'static, T>>,
-    rest: SerdeByIdTableRest<T>,
-}
-
-impl<T: SerdeByIdTrait> Default for SerdeByIdTableMut<T> {
-    fn default() -> Self {
-        Self {
-            to_serde: Default::default(),
-            rest: Default::default(),
-        }
-    }
-}
-
-impl<T: SerdeByIdTrait> SerdeByIdTableMut<T> {
-    pub(crate) fn to_serde(&mut self, value: &T) -> SerdeId<'static, T> {
-        if let Some(retval) = self.to_serde.get(value) {
-            return retval.clone();
-        }
-        self.to_serde_insert(value)
-    }
-    #[cold]
-    fn to_serde_insert(&mut self, value: &T) -> SerdeId<'static, T> {
-        let value = value.clone();
-        let retval = self.rest.add_new(value.clone());
-        self.to_serde.insert(value, retval.clone());
-        retval
-    }
-    pub(crate) fn from_serde(&self, id: &SerdeId<'_, T>) -> Option<T> {
-        self.rest.from_serde.get(id).cloned()
-    }
-}
-
-pub(crate) struct SerdeByIdTable<T: SerdeByIdTrait>(Mutex<Option<SerdeByIdTableMut<T>>>);
-
-impl<T: SerdeByIdTrait> SerdeByIdTable<T> {
-    pub(crate) const fn new() -> Self {
-        Self(Mutex::new(None))
-    }
-    pub(crate) fn to_serde(&self, value: &T) -> SerdeId<'static, T> {
-        self.0
-            .lock()
-            .expect("shouldn't be poison")
-            .get_or_insert_with(
-                #[cold]
-                || Default::default(),
-            )
-            .to_serde(value)
-    }
-    pub(crate) fn from_serde(&self, id: &SerdeId<'_, T>) -> Option<T> {
-        self.0
-            .lock()
-            .expect("shouldn't be poison")
-            .get_or_insert_with(
-                #[cold]
-                || Default::default(),
-            )
-            .from_serde(id)
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default, Ord, PartialOrd)]
-pub(crate) struct SerdeById<T: SerdeByIdTrait> {
-    pub(crate) inner: T,
-}
-
-impl<'de, T: SerdeByIdTrait> Deserialize<'de> for SerdeById<T> {
-    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
-    where
-        D: serde::Deserializer<'de>,
-    {
-        let id = SerdeId::deserialize(deserializer)?;
-        let inner = T::static_table().from_serde(&id).ok_or_else(|| {
-            D::Error::custom(format_args!(
-                "doesn't match any {} that was serialized this time this program was run: type_name={:?}",
-                T::NAME,
-                id.type_name,
-            ))
-        })?;
-        Ok(Self { inner })
-    }
-}
-
-impl<T: SerdeByIdTrait> Serialize for SerdeById<T> {
-    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
-    where
-        S: serde::Serializer,
-    {
-        T::static_table()
-            .to_serde(&self.inner)
-            .serialize(serializer)
-    }
-}

crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs

@@ -546,7 +546,7 @@ impl<W: fmt::Write> Visitor for XdcFileWriter<W> {
                                 base.source_location(),
                             )? {},
                         }
-                        match base.canonical_ty().unwrap_transparent_types() {
+                        match base.canonical_ty() {
                             CanonicalType::UInt(_)
                             | CanonicalType::SInt(_)
                             | CanonicalType::Bool(_)
@@ -563,9 +563,6 @@ impl<W: fmt::Write> Visitor for XdcFileWriter<W> {
                                 v,
                                 base.source_location(),
                             )? {},
-                            CanonicalType::TraceAsString(_) => {
-                                unreachable!("handled by unwrap_transparent_types")
-                            }
                         }
                         self.required_dont_touch_targets.insert(target);
                         match v {
@@ -595,9 +592,6 @@ impl<W: fmt::Write> Visitor for XdcFileWriter<W> {
                         v,
                         instance.source_location(),
                     )? {},
-                    TargetBase::FormalInput(_) | TargetBase::SimIoForGlobal(_) => {
-                        unreachable!("base.is_valid_annotation_target() is known to be false")
-                    }
                 }
             }
         }

crates/fayalite/src/wire.rs

@@ -58,13 +58,11 @@ impl<T: Type> Wire<T> {
             ty: T::from_canonical(ty),
         }
     }
-    #[track_caller]
     pub fn new_unchecked(
         scoped_name: ScopedNameId,
         source_location: SourceLocation,
         ty: T,
     ) -> Self {
-        scoped_name.0.assert_is_name_id();
         Self {
             name: scoped_name,
             source_location,
@@ -78,7 +76,7 @@ impl<T: Type> Wire<T> {
         self.containing_module_name_id().0
     }
     pub fn containing_module_name_id(&self) -> NameId {
-        self.name.0.unwrap_name_id()
+        self.name.0
     }
     pub fn name(&self) -> Interned<str> {
         self.name_id().0

crates/fayalite/tests/expected/my_test.md

@@ -1,6 +0,0 @@
-<!--
-SPDX-License-Identifier: LGPL-3.0-or-later
-See Notices.txt for copyright information
--->
-
-`my_test.vcd` is used in the doctest of `fayalite::testing::checked_vcd_output`

crates/fayalite/tests/expected/my_test.vcd

@@ -1,13 +0,0 @@
-$timescale 1 ps $end
-$scope module my_module $end
-$var wire 8 gAF7X a $end
-$var wire 8 QS=a/ b $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b0 gAF7X
-b0 QS=a/
-$end
-#1000000
-b1100100 gAF7X
-b101010 QS=a/

crates/fayalite/tests/hdl_types_fmt.rs

@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-use fayalite::{prelude::*, ty::SimValueDebug};
-use std::fmt;
-
-#[hdl(outline_generated)]
-struct MyStruct0<T, S: Size> {
-    v: T,
-    a: ArrayType<UInt<8>, S>,
-}
-
-#[hdl]
-#[test]
-fn check_my_struct0() {
-    let ty = MyStruct0[UInt[8]][3];
-    assert_eq!(
-        format!("{ty:?}"),
-        "MyStruct0 { v: UInt<8>, a: Array<UInt<8>, 3> }",
-    );
-    assert_eq!(
-        format!("{:?}", ty.mask_type()),
-        "MaskType<MyStruct0> { v: Bool, a: Array<Bool, 3> }",
-    );
-    let v = #[hdl(sim)]
-    MyStruct0::<_, _> {
-        v: 0x23u8,
-        a: [1u8, 2, 3],
-    };
-    assert_eq!(
-        format!("{v:?}"),
-        "MyStruct0 { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }",
-    );
-}
-
-#[hdl(outline_generated, custom_debug())]
-struct MyStruct1<T, S: Size> {
-    v: T,
-    a: ArrayType<UInt<8>, S>,
-}
-
-impl<T: Type, S: Size> fmt::Debug for MyStruct1<T, S> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self { v, a } = self;
-        f.debug_struct("Custom<MyStruct1>")
-            .field("v", v)
-            .field("a", a)
-            .finish()
-    }
-}
-
-impl<T: Type, S: Size> SimValueDebug for MyStruct1<T, S> {
-    #[hdl]
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        #[hdl(sim)]
-        let Self { v, a } = value;
-        f.debug_struct("Custom<MyStruct1>")
-            .field("v", &v)
-            .field("a", &a)
-            .finish()
-    }
-}
-
-#[hdl]
-#[test]
-fn check_my_struct1() {
-    let ty = MyStruct1[UInt[8]][3];
-    assert_eq!(
-        format!("{ty:?}"),
-        "Custom<MyStruct1> { v: UInt<8>, a: Array<UInt<8>, 3> }",
-    );
-    assert_eq!(
-        format!("{:?}", ty.mask_type()),
-        "MaskType<MyStruct1> { v: Bool, a: Array<Bool, 3> }",
-    );
-    let v = #[hdl(sim)]
-    MyStruct1::<_, _> {
-        v: 0x23u8,
-        a: [1u8, 2, 3],
-    };
-    assert_eq!(
-        format!("{v:?}"),
-        "Custom<MyStruct1> { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }",
-    );
-}
-
-#[hdl(outline_generated)]
-enum MyEnum0<T, S: Size> {
-    Unit,
-    V(T),
-    A(ArrayType<UInt<8>, S>),
-}
-
-#[hdl]
-#[test]
-fn check_my_enum0() {
-    let ty = MyEnum0[UInt[8]][3];
-    assert_eq!(
-        format!("{ty:?}"),
-        "MyEnum0 { Unit: (), V: UInt<8>, A: Array<UInt<8>, 3> }",
-    );
-    let v = #[hdl(sim)]
-    ty.Unit();
-    assert_eq!(format!("{v:?}"), "Unit");
-    let v = #[hdl(sim)]
-    ty.V(0x23u8);
-    assert_eq!(format!("{v:?}"), "V(0x23_u8)");
-    let v = #[hdl(sim)]
-    ty.A([1u8, 2, 3]);
-    assert_eq!(format!("{v:?}"), "A([0x1_u8, 0x2_u8, 0x3_u8])");
-}
-
-#[hdl(outline_generated, custom_debug())]
-enum MyEnum1<T, S: Size> {
-    Unit,
-    V(T),
-    A(ArrayType<UInt<8>, S>),
-}
-
-impl<T: Type, S: Size> fmt::Debug for MyEnum1<T, S> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self { Unit, V, A } = self;
-        f.debug_struct("Custom<MyEnum1>")
-            .field("Unit", Unit)
-            .field("V", V)
-            .field("A", A)
-            .finish()
-    }
-}
-
-impl<T: Type, S: Size> SimValueDebug for MyEnum1<T, S> {
-    #[hdl]
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut fmt::Formatter<'_>,
-    ) -> fmt::Result {
-        type SimValueT<T> = <T as Type>::SimValue;
-        match value {
-            SimValueT::<Self>::Unit(_) => f.write_str("MyEnum1::Unit"),
-            SimValueT::<Self>::V(v, _) => f.debug_tuple("MyEnum1::V").field(v).finish(),
-            SimValueT::<Self>::A(a, _) => f.debug_tuple("MyEnum1::A").field(a).finish(),
-            SimValueT::<Self>::Unknown(_) => f.write_str("MyEnum1::Unknown"),
-        }
-    }
-}
-
-#[hdl]
-#[test]
-fn check_my_enum1() {
-    let ty = MyEnum1[UInt[8]][3];
-    assert_eq!(
-        format!("{ty:?}"),
-        "Custom<MyEnum1> { Unit: (), V: UInt<8>, A: Array<UInt<8>, 3> }",
-    );
-    let v = #[hdl(sim)]
-    ty.Unit();
-    assert_eq!(format!("{v:?}"), "MyEnum1::Unit");
-    let v = #[hdl(sim)]
-    ty.V(0x23u8);
-    assert_eq!(format!("{v:?}"), "MyEnum1::V(0x23_u8)");
-    let v = #[hdl(sim)]
-    ty.A([1u8, 2, 3]);
-    assert_eq!(format!("{v:?}"), "MyEnum1::A([0x1_u8, 0x2_u8, 0x3_u8])");
-}

crates/fayalite/tests/module.rs

@@ -13,7 +13,7 @@ use fayalite::{
 };
 use serde_json::json;
 
-#[hdl(outline_generated, cmp_eq)]
+#[hdl(outline_generated)]
 pub enum TestEnum {
     A,
     B(UInt<8>),
@@ -679,270 +679,6 @@ circuit check_enum_literals:
     };
 }
 
-#[hdl_module(outline_generated)]
-pub fn check_enum_cmp_eq() {
-    #[hdl]
-    let lhs: TestEnum = m.input();
-    #[hdl]
-    let rhs: TestEnum = m.input();
-    #[hdl]
-    let eq: Bool = m.output();
-    connect(eq, lhs.cmp_eq(rhs));
-}
-
-#[test]
-fn test_enum_cmp_eq() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let m = check_enum_cmp_eq();
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
-circuit check_enum_cmp_eq:
-    type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
-    module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
-        input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1]
-        output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
-        wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
-        connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
-        match lhs: @[module-XXXXXXXXXX.rs 5:1]
-            A:
-                match rhs: @[module-XXXXXXXXXX.rs 5:1]
-                    A:
-                        connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
-                    B(_match_arm_value):
-                        skip
-                    C(_match_arm_value_1):
-                        skip
-            B(_match_arm_value_2):
-                match rhs: @[module-XXXXXXXXXX.rs 5:1]
-                    A:
-                        skip
-                    B(_match_arm_value_3):
-                        connect TestEnum_cmp_eq, eq(_match_arm_value_2, _match_arm_value_3) @[module-XXXXXXXXXX.rs 5:1]
-                    C(_match_arm_value_4):
-                        skip
-            C(_match_arm_value_5):
-                match rhs: @[module-XXXXXXXXXX.rs 5:1]
-                    A:
-                        skip
-                    B(_match_arm_value_6):
-                        skip
-                    C(_match_arm_value_7):
-                        wire _array_literal_expr: UInt<1>[3]
-                        connect _array_literal_expr[0], eq(_match_arm_value_5[0], _match_arm_value_7[0])
-                        connect _array_literal_expr[1], eq(_match_arm_value_5[1], _match_arm_value_7[1])
-                        connect _array_literal_expr[2], eq(_match_arm_value_5[2], _match_arm_value_7[2])
-                        wire _cast_array_to_bits_expr: UInt<1>[3]
-                        connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
-                        connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
-                        connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
-                        wire _cast_to_bits_expr: UInt<3>
-                        connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-                        connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
-        connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
-",
-    };
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
-            ..ExportOptions::default()
-        },
-        "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
-circuit check_enum_cmp_eq:
-    type Ty0 = {|A, B, C|}
-    type Ty1 = {tag: Ty0, body: UInt<8>}
-    module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
-        input lhs: Ty1 @[module-XXXXXXXXXX.rs 2:1]
-        input rhs: Ty1 @[module-XXXXXXXXXX.rs 3:1]
-        output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
-        wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
-        connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
-        match lhs.tag: @[module-XXXXXXXXXX.rs 5:1]
-            A:
-                match rhs.tag: @[module-XXXXXXXXXX.rs 5:1]
-                    A:
-                        connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
-                    B:
-                        skip
-                    C:
-                        skip
-            B:
-                match rhs.tag: @[module-XXXXXXXXXX.rs 5:1]
-                    A:
-                        skip
-                    B:
-                        connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1]
-                    C:
-                        skip
-            C:
-                match rhs.tag: @[module-XXXXXXXXXX.rs 5:1]
-                    A:
-                        skip
-                    B:
-                        skip
-                    C:
-                        wire _array_literal_expr: UInt<1>[3]
-                        wire _cast_bits_to_array_expr: UInt<1>[3]
-                        wire _cast_bits_to_array_expr_flattened: UInt<1>[3]
-                        connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0)
-                        connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0]
-                        connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1)
-                        connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
-                        connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2)
-                        connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
-                        wire _cast_bits_to_array_expr_1: UInt<1>[3]
-                        wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3]
-                        connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0)
-                        connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0]
-                        connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1)
-                        connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
-                        connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
-                        connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
-                        connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
-                        connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
-                        connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
-                        wire _cast_array_to_bits_expr: UInt<1>[3]
-                        connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
-                        connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
-                        connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
-                        wire _cast_to_bits_expr: UInt<3>
-                        connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-                        connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
-        connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
-",
-    };
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
-            ..ExportOptions::default()
-        },
-        "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
-circuit check_enum_cmp_eq:
-    type Ty0 = {tag: UInt<2>, body: UInt<8>}
-    module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
-        input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1]
-        input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1]
-        output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
-        wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
-        connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
-        when eq(lhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-            when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-                connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
-            else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-                skip
-        else when eq(lhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-            when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-                skip
-            else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-                connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1]
-        else when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-            skip
-        else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-            skip
-        else:
-            wire _array_literal_expr: UInt<1>[3]
-            wire _cast_bits_to_array_expr: UInt<1>[3]
-            wire _cast_bits_to_array_expr_flattened: UInt<1>[3]
-            connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0)
-            connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0]
-            connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1)
-            connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
-            connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2)
-            connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
-            wire _cast_bits_to_array_expr_1: UInt<1>[3]
-            wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3]
-            connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0)
-            connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0]
-            connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1)
-            connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
-            connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
-            connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
-            connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
-            connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
-            connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
-            wire _cast_array_to_bits_expr: UInt<1>[3]
-            connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
-            connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
-            connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
-            wire _cast_to_bits_expr: UInt<3>
-            connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-            connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
-        connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
-",
-    };
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt),
-            ..ExportOptions::default()
-        },
-        "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
-circuit check_enum_cmp_eq:
-    module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
-        input lhs: UInt<10> @[module-XXXXXXXXXX.rs 2:1]
-        input rhs: UInt<10> @[module-XXXXXXXXXX.rs 3:1]
-        output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
-        wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
-        connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
-        when eq(bits(lhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-            when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-                connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
-            else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-                skip
-        else when eq(bits(lhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-            when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-                skip
-            else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-                connect TestEnum_cmp_eq, eq(bits(bits(lhs, 9, 2), 7, 0), bits(bits(rhs, 9, 2), 7, 0)) @[module-XXXXXXXXXX.rs 5:1]
-        else when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
-            skip
-        else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
-            skip
-        else:
-            wire _array_literal_expr: UInt<1>[3]
-            wire _cast_bits_to_array_expr: UInt<1>[3]
-            wire _cast_bits_to_array_expr_flattened: UInt<1>[3]
-            connect _cast_bits_to_array_expr_flattened[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
-            connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0]
-            connect _cast_bits_to_array_expr_flattened[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
-            connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
-            connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
-            connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
-            wire _cast_bits_to_array_expr_1: UInt<1>[3]
-            wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3]
-            connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
-            connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0]
-            connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
-            connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
-            connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
-            connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
-            connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
-            connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1])
-            connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2])
-            wire _cast_array_to_bits_expr: UInt<1>[3]
-            connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
-            connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
-            connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
-            wire _cast_to_bits_expr: UInt<3>
-            connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-            connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
-        connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
-",
-    };
-}
-
 #[hdl_module(outline_generated)]
 pub fn check_struct_enum_match() {
     #[hdl]
@@ -3683,176 +3419,20 @@ circuit check_formal: %[[
         input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
         input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
         input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
-        inst formal_reset of formal_reset @[builtin 1:1]
+        inst formal_reset of formal_reset @[formal.rs 185:24]
         assert(clk, pred1, and(en1, not(formal_reset.rst)), "en check 1") @[module-XXXXXXXXXX.rs 9:1]
-        assume(clk, pred2, and(en2, not(formal_reset.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1]
+        inst formal_reset_1 of formal_reset @[formal.rs 185:24]
-        cover(clk, pred3, and(en3, not(formal_reset.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1]
+        assume(clk, pred2, and(en2, not(formal_reset_1.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1]
-        assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1]
+        inst formal_reset_2 of formal_reset @[formal.rs 185:24]
-        assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1]
+        cover(clk, pred3, and(en3, not(formal_reset_2.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1]
-        cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1]
+        inst formal_reset_3 of formal_reset @[formal.rs 185:24]
-    extmodule formal_reset: @[builtin 1:1]
+        assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset_3.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1]
-        output rst: UInt<1> @[builtin 1:1]
+        inst formal_reset_4 of formal_reset @[formal.rs 185:24]
-        defname = __fayalite_formal_reset
+        assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset_4.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1]
-"#,
+        inst formal_reset_5 of formal_reset @[formal.rs 185:24]
-    };
+        cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset_5.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1]
-}
+    extmodule formal_reset: @[formal.rs 169:5]
-
+        output rst: UInt<1> @[formal.rs 172:32]
-#[hdl_module(outline_generated)]
-pub fn check_formal_input() {
-    #[hdl]
-    let bool_in: Bool = m.input();
-    #[hdl]
-    let bool_out: Bool = m.output();
-    #[hdl]
-    let any_const_out1: Bool = m.output();
-    #[hdl]
-    let any_const_out2: UInt<16> = m.output();
-    #[hdl]
-    let any_const_out3: SInt<12> = m.output();
-    #[hdl]
-    let any_seq_out: UInt<10> = m.output();
-    #[hdl]
-    let all_const_out: UInt<10> = m.output();
-    #[hdl]
-    let all_seq_out: UInt<10> = m.output();
-
-    #[hdl]
-    let bool_reg = reg_builder()
-        .clock_domain(
-            #[hdl]
-            ClockDomain {
-                clk: formal_global_clock(),
-                rst: formal_reset(),
-            },
-        )
-        .reset(false);
-
-    connect(bool_reg, bool_in);
-    connect(bool_out, bool_reg);
-    connect(any_const_out1, any_const(StaticType::TYPE));
-    connect(any_const_out2, any_const(StaticType::TYPE));
-    connect(any_const_out3, any_const(StaticType::TYPE));
-    connect(any_seq_out, any_seq(StaticType::TYPE));
-    connect(all_const_out, all_const(StaticType::TYPE));
-    connect(all_seq_out, all_seq(StaticType::TYPE));
-}
-
-#[test]
-fn test_formal_input() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let m = check_formal_input();
-    dbg!(m);
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        "/test/check_formal_input.fir": r#"FIRRTL version 3.2.0
-circuit check_formal_input: %[[
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "gclk",
-    "target": "~check_formal_input|check_formal_input>formal_global_clock"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>formal_global_clock"
-  },
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "anyconst",
-    "target": "~check_formal_input|check_formal_input>any_const"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>any_const"
-  },
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "anyconst",
-    "target": "~check_formal_input|check_formal_input>any_const_1"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>any_const_1"
-  },
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "anyconst",
-    "target": "~check_formal_input|check_formal_input>any_const_2"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>any_const_2"
-  },
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "anyseq",
-    "target": "~check_formal_input|check_formal_input>any_seq"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>any_seq"
-  },
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "allconst",
-    "target": "~check_formal_input|check_formal_input>all_const"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>all_const"
-  },
-  {
-    "class": "firrtl.AttributeAnnotation",
-    "description": "allseq",
-    "target": "~check_formal_input|check_formal_input>all_seq"
-  },
-  {
-    "class": "firrtl.transforms.DontTouchAnnotation",
-    "target": "~check_formal_input|check_formal_input>all_seq"
-  },
-  {
-    "class": "firrtl.transforms.BlackBoxInlineAnno",
-    "name": "fayalite_formal_reset.v",
-    "text": "module __fayalite_formal_reset(output rst);\n    assign rst = $initstate;\nendmodule\n",
-    "target": "~check_formal_input|formal_reset"
-  }
-]]
-    type Ty0 = {clk: Clock, rst: UInt<1>}
-    type Ty1 = {rst: UInt<1>}
-    module check_formal_input: @[module-XXXXXXXXXX.rs 1:1]
-        input bool_in: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
-        output bool_out: UInt<1> @[module-XXXXXXXXXX.rs 3:1]
-        output any_const_out1: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
-        output any_const_out2: UInt<16> @[module-XXXXXXXXXX.rs 5:1]
-        output any_const_out3: SInt<12> @[module-XXXXXXXXXX.rs 6:1]
-        output any_seq_out: UInt<10> @[module-XXXXXXXXXX.rs 7:1]
-        output all_const_out: UInt<10> @[module-XXXXXXXXXX.rs 8:1]
-        output all_seq_out: UInt<10> @[module-XXXXXXXXXX.rs 9:1]
-        wire _bundle_literal_expr_1: Ty0
-        connect _bundle_literal_expr_1.clk, asClock(UInt<1>(0h0))
-        connect _bundle_literal_expr_1.rst, UInt<1>(0h0)
-        reg formal_global_clock: UInt<1>, _bundle_literal_expr_1.clk @[builtin 1:1]
-        inst formal_reset of formal_reset @[builtin 1:1]
-        reg any_const: UInt<1>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 13:1]
-        reg any_const_1: UInt<16>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 15:1]
-        reg any_const_2: SInt<12>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 17:1]
-        reg any_seq: UInt<10>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 19:1]
-        reg all_const: UInt<10>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 21:1]
-        reg all_seq: UInt<10>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 23:1]
-        wire _bundle_literal_expr: Ty0
-        connect _bundle_literal_expr.clk, asClock(formal_global_clock)
-        connect _bundle_literal_expr.rst, formal_reset.rst
-        regreset bool_reg: UInt<1>, _bundle_literal_expr.clk, _bundle_literal_expr.rst, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 10:1]
-        connect bool_reg, bool_in @[module-XXXXXXXXXX.rs 11:1]
-        connect bool_out, bool_reg @[module-XXXXXXXXXX.rs 12:1]
-        connect any_const_out1, any_const @[module-XXXXXXXXXX.rs 14:1]
-        connect any_const_out2, any_const_1 @[module-XXXXXXXXXX.rs 16:1]
-        connect any_const_out3, any_const_2 @[module-XXXXXXXXXX.rs 18:1]
-        connect any_seq_out, any_seq @[module-XXXXXXXXXX.rs 20:1]
-        connect all_const_out, all_const @[module-XXXXXXXXXX.rs 22:1]
-        connect all_seq_out, all_seq @[module-XXXXXXXXXX.rs 24:1]
-    extmodule formal_reset: @[builtin 1:1]
-        output rst: UInt<1> @[builtin 1:1]
         defname = __fayalite_formal_reset
 "#,
     };
@@ -3985,10 +3565,21 @@ circuit check_enum_connect_any:
                             connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
                         HdlSome:
                             wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                            wire _cast_bits_to_bundle_expr_1: Ty5
+                            wire _cast_bits_to_bundle_expr_flattened_1: Ty6
+                            connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
+                            wire _cast_bits_to_enum_expr_1: Ty3
+                            when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
+                                connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
+                            else:
+                                connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
+                            connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
+                            connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
+                            connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
                             ; connect different types:
                             ; lhs: SInt<1>
                             ; rhs: SInt<2>
-                            connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
+                            connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
                             wire _bundle_literal_expr_2: Ty4
                             connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
                             connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
@@ -4010,18 +3601,18 @@ circuit check_enum_connect_any:
                     connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
                 C:
                     wire __connect_variant_body_3: Ty8 @[module-XXXXXXXXXX.rs 8:1]
-                    wire _cast_bits_to_bundle_expr_1: Ty8
+                    wire _cast_bits_to_bundle_expr_2: Ty8
-                    wire _cast_bits_to_bundle_expr_flattened_1: Ty9
+                    wire _cast_bits_to_bundle_expr_flattened_2: Ty9
-                    connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
-                    wire _cast_bits_to_enum_expr_1: Ty3
+                    wire _cast_bits_to_enum_expr_2: Ty3
-                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
-                        connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
+                        connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
                     else:
-                        connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
+                        connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
-                    connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
+                    connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
-                    connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0)
+                    connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
-                    connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
+                    connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
-                    connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1]
+                    connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
                     wire _bundle_literal_expr_4: Ty1
                     connect _bundle_literal_expr_4.tag, {|A, B, C|}(C)
                     wire _cast_bundle_to_bits_expr_1: Ty9
@@ -4050,18 +3641,18 @@ circuit check_enum_connect_any:
                     connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
                 B:
                     wire __connect_variant_body_5: Ty5 @[module-XXXXXXXXXX.rs 9:1]
-                    wire _cast_bits_to_bundle_expr_2: Ty4
+                    wire _cast_bits_to_bundle_expr_3: Ty4
-                    wire _cast_bits_to_bundle_expr_flattened_2: Ty7
+                    wire _cast_bits_to_bundle_expr_flattened_3: Ty7
-                    connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
-                    wire _cast_bits_to_enum_expr_2: Ty3
+                    wire _cast_bits_to_enum_expr_3: Ty3
-                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
-                        connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
+                        connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
                     else:
-                        connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
+                        connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
-                    connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
+                    connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
-                    connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1)
+                    connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
-                    connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
+                    connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
-                    match _cast_bits_to_bundle_expr_2.tag: @[module-XXXXXXXXXX.rs 9:1]
+                    match _cast_bits_to_bundle_expr_3.tag: @[module-XXXXXXXXXX.rs 9:1]
                         HdlNone:
                             wire _bundle_literal_expr_6: Ty5
                             connect _bundle_literal_expr_6.tag, {|HdlNone, HdlSome|}(HdlNone)
@@ -4069,10 +3660,21 @@ circuit check_enum_connect_any:
                             connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
                         HdlSome:
                             wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                            wire _cast_bits_to_bundle_expr_4: Ty4
+                            wire _cast_bits_to_bundle_expr_flattened_4: Ty7
+                            connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                            wire _cast_bits_to_enum_expr_4: Ty3
+                            when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_4.tag, 0)):
+                                connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlNone)
+                            else:
+                                connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlSome)
+                            connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
+                            connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
+                            connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
                             ; connect different types:
                             ; lhs: SInt<2>
                             ; rhs: SInt<1>
-                            connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
+                            connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
                             wire _bundle_literal_expr_7: Ty5
                             connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
                             connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
@@ -4094,18 +3696,18 @@ circuit check_enum_connect_any:
                     connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
                 C:
                     wire __connect_variant_body_7: Ty8 @[module-XXXXXXXXXX.rs 9:1]
-                    wire _cast_bits_to_bundle_expr_3: Ty8
+                    wire _cast_bits_to_bundle_expr_5: Ty8
-                    wire _cast_bits_to_bundle_expr_flattened_3: Ty9
+                    wire _cast_bits_to_bundle_expr_flattened_5: Ty9
-                    connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
-                    wire _cast_bits_to_enum_expr_3: Ty3
+                    wire _cast_bits_to_enum_expr_5: Ty3
-                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_5.tag, 0)):
-                        connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
+                        connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlNone)
                     else:
-                        connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
+                        connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlSome)
-                    connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
+                    connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_enum_expr_5
-                    connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0)
+                    connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
-                    connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
+                    connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
-                    connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1]
+                    connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
                     wire _bundle_literal_expr_9: Ty2
                     connect _bundle_literal_expr_9.tag, {|A, B, C|}(C)
                     wire _cast_bundle_to_bits_expr_3: Ty9
@@ -4172,10 +3774,16 @@ circuit check_enum_connect_any:
                     connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
                 else:
                     wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                    wire _cast_bits_to_bundle_expr_1: Ty3
+                    wire _cast_bits_to_bundle_expr_flattened_1: Ty3
+                    connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
+                    connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
+                    connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
                     ; connect different types:
                     ; lhs: SInt<1>
                     ; rhs: SInt<2>
-                    connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
+                    connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
                     wire _bundle_literal_expr_2: Ty2
                     connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
                     connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
@@ -4191,13 +3799,13 @@ circuit check_enum_connect_any:
                 connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
             else:
                 wire __connect_variant_body_3: Ty4 @[module-XXXXXXXXXX.rs 8:1]
-                wire _cast_bits_to_bundle_expr_1: Ty4
+                wire _cast_bits_to_bundle_expr_2: Ty4
-                wire _cast_bits_to_bundle_expr_flattened_1: Ty4
+                wire _cast_bits_to_bundle_expr_flattened_2: Ty4
-                connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
-                connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
+                connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
-                connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0)
+                connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
-                connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
+                connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
-                connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1]
+                connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
                 wire _bundle_literal_expr_4: Ty0
                 connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
                 wire _cast_bundle_to_bits_expr_1: Ty4
@@ -4219,23 +3827,29 @@ circuit check_enum_connect_any:
                 connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
             else when eq(i1.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
                 wire __connect_variant_body_5: Ty3 @[module-XXXXXXXXXX.rs 9:1]
-                wire _cast_bits_to_bundle_expr_2: Ty2
+                wire _cast_bits_to_bundle_expr_3: Ty2
-                wire _cast_bits_to_bundle_expr_flattened_2: Ty2
+                wire _cast_bits_to_bundle_expr_flattened_3: Ty2
-                connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
-                connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
+                connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
-                connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1)
+                connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
-                connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
+                connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
-                when eq(_cast_bits_to_bundle_expr_2.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
+                when eq(_cast_bits_to_bundle_expr_3.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
                     wire _bundle_literal_expr_6: Ty3
                     connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
                     connect _bundle_literal_expr_6.body, UInt<2>(0h0)
                     connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
                 else:
                     wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                    wire _cast_bits_to_bundle_expr_4: Ty2
+                    wire _cast_bits_to_bundle_expr_flattened_4: Ty2
+                    connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
+                    connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
+                    connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
                     ; connect different types:
                     ; lhs: SInt<2>
                     ; rhs: SInt<1>
-                    connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
+                    connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
                     wire _bundle_literal_expr_7: Ty3
                     connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
                     connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
@@ -4251,13 +3865,13 @@ circuit check_enum_connect_any:
                 connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
             else:
                 wire __connect_variant_body_7: Ty4 @[module-XXXXXXXXXX.rs 9:1]
-                wire _cast_bits_to_bundle_expr_3: Ty4
+                wire _cast_bits_to_bundle_expr_5: Ty4
-                wire _cast_bits_to_bundle_expr_flattened_3: Ty4
+                wire _cast_bits_to_bundle_expr_flattened_5: Ty4
-                connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
-                connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
+                connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_bundle_expr_flattened_5.tag
-                connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0)
+                connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
-                connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
+                connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
-                connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1]
+                connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
                 wire _bundle_literal_expr_9: Ty1
                 connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
                 wire _cast_bundle_to_bits_expr_3: Ty4

crates/fayalite/tests/sim.rs

@@ -1,28 +1,15 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
-use bitvec::{order::Lsb0, view::BitView};
 use fayalite::{
-    assert_export_firrtl,
+    memory::{ReadStruct, ReadWriteStruct, WriteStruct},
-    firrtl::ExportOptions,
+    module::{instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc},
-    formal::FormalInputKind,
-    memory::{ReadStruct, ReadWriteStruct, WriteStruct, splat_mask},
-    module::{
-        instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc,
-        transform::simplify_enums::SimplifyEnumsKind,
-    },
     prelude::*,
     reset::ResetType,
     sim::vcd::VcdWriterDecls,
-    ty::SimValueDebug,
     util::{RcWriter, ready_valid::queue},
 };
-use std::{
+use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc};
-    collections::BTreeMap,
-    num::NonZeroUsize,
-    panic::{AssertUnwindSafe, catch_unwind, resume_unwind},
-    rc::Rc,
-};
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -563,150 +550,6 @@ fn test_enums() {
     }
 }
 
-#[hdl]
-pub enum EnumWithSimpleBody {
-    A(UInt<8>),
-    B(UInt<8>),
-    C(UInt<8>),
-}
-
-#[hdl_module(outline_generated)]
-pub fn enum_with_simple_body() {
-    #[hdl]
-    let which_in: UInt<8> = m.input();
-    #[hdl]
-    let data_in: UInt<8> = m.input();
-    #[hdl]
-    let which_out: UInt<8> = m.output();
-    #[hdl]
-    let data_out: UInt<8> = m.output();
-    #[hdl]
-    let enum_out: EnumWithSimpleBody = m.output();
-
-    #[hdl]
-    if which_in.cmp_eq(0u8) {
-        connect(enum_out, EnumWithSimpleBody.A(data_in));
-    } else if which_in.cmp_eq(1u8) {
-        connect(enum_out, EnumWithSimpleBody.B(data_in));
-    } else {
-        connect(enum_out, EnumWithSimpleBody.C(data_in));
-    }
-
-    #[hdl]
-    match enum_out {
-        EnumWithSimpleBody::A(v) => {
-            connect(which_out, 0u8);
-            connect(data_out, v);
-        }
-        EnumWithSimpleBody::B(v) => {
-            connect(which_out, 1u8);
-            connect(data_out, v);
-        }
-        EnumWithSimpleBody::C(v) => {
-            connect(which_out, 2u8);
-            connect(data_out, v);
-        }
-    }
-}
-
-#[hdl]
-#[test]
-fn test_enum_with_simple_body() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let mut sim = Simulation::new(enum_with_simple_body());
-    let mut writer = RcWriter::default();
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    for which in 0u8..=2 {
-        for data in (0..u8::MAX).step_by(45) {
-            sim.write(sim.io().which_in, which);
-            sim.write(sim.io().data_in, data);
-            sim.advance_time(SimDuration::from_micros(1));
-            assert_eq!(sim.read(sim.io().which_out).as_int(), which);
-            assert_eq!(sim.read(sim.io().data_out).as_int(), data);
-        }
-    }
-    sim.flush_traces().unwrap();
-    let vcd = String::from_utf8(writer.take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    #[derive(Debug)]
-    struct WireState<'a> {
-        name: &'a str,
-        space_then_id: Option<&'a str>,
-        value: Option<&'a str>,
-    }
-    impl<'a> WireState<'a> {
-        fn new(name: &'a str) -> Self {
-            Self {
-                name,
-                space_then_id: None,
-                value: None,
-            }
-        }
-    }
-    let mut variant_wires = [
-        WireState::new("A"),
-        WireState::new("B"),
-        WireState::new("C"),
-    ];
-    // check that output .vcd has the proper values for all variants' wires
-    for (is_last, line) in vcd.lines().map(|line| (false, line)).chain([(true, "")]) {
-        if let Some(line) = line.strip_prefix("$var wire 8")
-            && let Some(line) = line.strip_suffix(" $end")
-            && let Some((space_then_id, state)) = variant_wires
-                .iter_mut()
-                .find_map(|state| Some((line.strip_suffix(state.name)?.strip_suffix(" ")?, state)))
-        {
-            assert_eq!(space_then_id.chars().next(), Some(' '));
-            assert!(
-                space_then_id
-                    .chars()
-                    .skip(1)
-                    .all(|ch| matches!(ch, '!'..='~'))
-            );
-            assert_eq!(state.space_then_id.replace(space_then_id), None);
-        } else if line.starts_with("#") || is_last {
-            let Some(expected_value) = variant_wires[0].value else {
-                panic!(
-                    "variant {} hasn't been initialized before a timestamp or EOF: {variant_wires:#?}\n\
-                    line={line:?}",
-                    variant_wires[0].name,
-                );
-            };
-            for state in &variant_wires {
-                assert_eq!(
-                    state.value,
-                    Some(expected_value),
-                    "at a timestamp or EOF: variant value for {} doesn't match expected value.\n\
-                    {variant_wires:#?}\nline={line:?}",
-                    state.name,
-                );
-            }
-        } else if line.starts_with("b") {
-            for state in &mut variant_wires {
-                let Some(space_then_id) = state.space_then_id else {
-                    let name = state.name;
-                    panic!(
-                        "variant {name} hasn't had an id assigned yet: {variant_wires:#?}\n\
-                        line={line:?}",
-                    );
-                };
-                if let Some(value) = line.strip_suffix(space_then_id) {
-                    state.value = Some(value);
-                    break;
-                }
-            }
-        }
-    }
-    if vcd != include_str!("sim/expected/enum_with_simple_body.vcd") {
-        panic!();
-    }
-    let sim_debug = format!("{sim:#?}");
-    println!("#######\n{sim_debug}\n#######");
-    if sim_debug != include_str!("sim/expected/enum_with_simple_body.txt") {
-        panic!();
-    }
-}
-
 #[hdl_module(outline_generated)]
 pub fn memories() {
     #[hdl]
@@ -2998,754 +2841,3 @@ fn test_queue_4_true_true() {
         include_str!("sim/expected/queue_4_true_true.txt"),
     );
 }
-
-#[hdl(outline_generated, custom_debug(sim), cmp_eq)]
-pub enum HasCustomDebug {
-    Text(UInt<512>),
-    FmtError,
-}
-
-impl HasCustomDebug {
-    #[hdl]
-    pub fn new_sim(text: Result<&str, std::fmt::Error>) -> SimValue<Self> {
-        match text {
-            Ok(text) => {
-                let mut retval = HasCustomDebug.Text.zero();
-                let src = text.as_bytes().view_bits::<Lsb0>();
-                let dest = retval.bits_mut();
-                let len = src.len().min(dest.len());
-                dest[..len].clone_from_bitslice(&src[..len]);
-                #[hdl(sim)]
-                HasCustomDebug.Text(retval)
-            }
-            Err(std::fmt::Error) =>
-            {
-                #[hdl(sim)]
-                HasCustomDebug.FmtError()
-            }
-        }
-    }
-    pub fn new(text: Result<&str, std::fmt::Error>) -> Expr<Self> {
-        Self::new_sim(text).to_expr()
-    }
-}
-
-impl SimValueDebug for HasCustomDebug {
-    #[hdl]
-    fn sim_value_debug(
-        value: &<Self as Type>::SimValue,
-        f: &mut std::fmt::Formatter<'_>,
-    ) -> std::fmt::Result {
-        if f.alternate() {
-            return #[hdl(sim)]
-            match value {
-                Self::FmtError => f.write_str("FmtError"),
-                Self::Text(text) => f.debug_tuple("Text").field(text).finish(),
-            };
-        }
-        #[hdl(sim)]
-        match value {
-            Self::FmtError => Err(std::fmt::Error),
-            Self::Text(text) => {
-                assert_eq!(text.ty().width() % u8::BITS as usize, 0);
-                let mut bytes = vec![0u8; text.ty().width() / u8::BITS as usize];
-                bytes
-                    .view_bits_mut::<Lsb0>()
-                    .clone_from_bitslice(text.bits());
-                if let Some(len) = bytes.iter().position(|b| *b == 0) {
-                    bytes.truncate(len);
-                }
-                f.write_str(&String::from_utf8_lossy(&bytes))
-            }
-        }
-    }
-}
-
-#[hdl_module(outline_generated)]
-pub fn sim_trace_as_string() {
-    #[hdl]
-    let clk: Clock = m.input();
-    #[hdl]
-    let read: ReadStruct<TraceAsString<Array<HasCustomDebug, 2>>, ConstUsize<8>> = m.input();
-    #[hdl]
-    let write: WriteStruct<Array<TraceAsString<HasCustomDebug>, 2>, ConstUsize<8>> = m.input();
-    #[hdl]
-    let mut mem = memory_with_init([[HasCustomDebug::new(Ok("")).to_trace_as_string(); 2]; 4]);
-    let read_port = mem.new_read_port();
-    connect(read_port.clk, clk);
-    connect_any(read_port.addr, read.addr);
-    connect(read_port.en, read.en);
-    for (l, r) in read.data.iter().zip(read_port.data.iter()) {
-        connect(l, &**r);
-    }
-    let write_port = mem.new_write_port();
-    connect(write_port.clk, clk);
-    connect_any(write_port.addr, write.addr);
-    connect(write_port.data, write.data);
-    connect(write_port.en, write.en);
-    connect(write_port.mask, write.mask);
-}
-
-#[hdl]
-#[test]
-fn test_sim_trace_as_string() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let m = sim_trace_as_string();
-    let mut sim = Simulation::new(m);
-    // sim.set_breakpoints_unstable(Default::default(), true);
-    let mut writer = RcWriter::default();
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write(sim.io().clk, false);
-    sim.write(sim.io().read.clk, false);
-    sim.write(sim.io().write.clk, false);
-    #[derive(Debug)]
-    struct TestCase {
-        read: Option<(u8, [Result<&'static str, std::fmt::Error>; 2])>,
-        write_addr: Option<u8>,
-        write_data: [Result<&'static str, std::fmt::Error>; 2],
-        write_mask: [bool; 2],
-    }
-    const TEST_CASES: &[TestCase] = &[
-        TestCase {
-            read: None,
-            write_addr: None,
-            write_data: [Ok(""); 2],
-            write_mask: [false; 2],
-        },
-        TestCase {
-            read: None,
-            write_addr: Some(0),
-            write_data: [Ok("mem[0][0]"), Ok("mem[0][1]")],
-            write_mask: [true; 2],
-        },
-        TestCase {
-            read: None,
-            write_addr: Some(1),
-            write_data: [Ok("mem[1][0]"), Ok("mem[1][1]")],
-            write_mask: [true; 2],
-        },
-        TestCase {
-            read: None,
-            write_addr: Some(2),
-            write_data: [Ok("mem[2][0]"), Ok("mem[2][1]")],
-            write_mask: [true; 2],
-        },
-        TestCase {
-            read: None,
-            write_addr: Some(3),
-            write_data: [Ok("mem[3][0]"), Ok("mem[3][1]")],
-            write_mask: [true; 2],
-        },
-        TestCase {
-            read: Some((1, [Ok("mem[1][0]"), Ok("mem[1][1]")])),
-            write_addr: None,
-            write_data: [Err(std::fmt::Error), Err(std::fmt::Error)],
-            write_mask: [true; 2],
-        },
-        TestCase {
-            read: Some((1, [Err(std::fmt::Error), Err(std::fmt::Error)])),
-            write_addr: Some(1),
-            write_data: [Err(std::fmt::Error), Err(std::fmt::Error)],
-            write_mask: [true; 2],
-        },
-    ];
-    for test_case in TEST_CASES {
-        let TestCase {
-            read,
-            write_addr,
-            write_data,
-            write_mask,
-        } = test_case;
-        sim.write(sim.io().read.addr, read.map(|v| v.0).unwrap_or(0));
-        sim.write(sim.io().read.en, read.is_some());
-        sim.write(sim.io().write.addr, write_addr.unwrap_or(0));
-        sim.write(sim.io().write.en, write_addr.is_some());
-        sim.write(
-            sim.io().write.data,
-            write_data.map(|v| HasCustomDebug::new_sim(v).to_trace_as_string()),
-        );
-        sim.write(
-            sim.io().write.mask,
-            write_mask.map(|v| splat_mask(TraceAsString[HasCustomDebug], v.to_expr())),
-        );
-        sim.write(sim.io().clk, false);
-        sim.advance_time(SimDuration::from_nanos(500));
-        sim.write(sim.io().clk, true);
-        sim.advance_time(SimDuration::from_nanos(500));
-        if let Some((_, expected_read_data)) = read {
-            let read_data = sim.read(sim.io().read.data);
-            let expected_read_data = expected_read_data
-                .map(HasCustomDebug::new_sim)
-                .into_sim_value();
-            assert!(
-                *read_data.inner() == expected_read_data,
-                "{read_data:#?}\n!= {expected_read_data:#?}",
-            );
-        }
-    }
-    sim.flush_traces().unwrap();
-    let vcd = String::from_utf8(writer.take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("sim/expected/sim_trace_as_string.vcd") {
-        panic!();
-    }
-    let sim_debug = format!("{sim:#?}");
-    println!("#######\n{sim_debug}\n#######");
-    if sim_debug != include_str!("sim/expected/sim_trace_as_string.txt") {
-        panic!();
-    }
-}
-
-#[test]
-fn test_firrtl_trace_as_string() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let m = sim_trace_as_string();
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_memories: false,
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0
-circuit sim_trace_as_string: %[[
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem.mem",
-    "hexOrBinary": "b",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem"
-  }
-]]
-    type Ty0 = {|Text: UInt<512>, FmtError|}
-    type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty0[2]}
-    type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]}
-    type Ty3 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty0[2]}
-    type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]}
-    module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1]
-        input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
-        input `read`: Ty1 @[module-XXXXXXXXXX.rs 3:1]
-        input `write`: Ty2 @[module-XXXXXXXXXX.rs 4:1]
-        mem `mem`: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => Ty0[2]
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 7:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect `mem`.r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1]
-        connect `mem`.r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1]
-        connect `read`.data[0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 10:1]
-        connect `read`.data[1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 10:1]
-        connect `mem`.w1.clk, clk @[module-XXXXXXXXXX.rs 12:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect `mem`.w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1]
-        connect `mem`.w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1]
-        connect `mem`.w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1]
-        connect `mem`.w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1]
-"#,
-        "/test/sim_trace_as_string/mem.mem": r"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-",
-    };
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_memories: true,
-            simplify_enums: None,
-            ..ExportOptions::default()
-        },
-        "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0
-circuit sim_trace_as_string: %[[
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem.mem",
-    "hexOrBinary": "b",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem"
-  }
-]]
-    type Ty0 = {|Text: UInt<512>, FmtError|}
-    type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty0[2]}
-    type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]}
-    type Ty3 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty0[2]}
-    type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]}
-    type Ty5 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<513>[2]}
-    type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<513>[2], mask: UInt<1>[2]}
-    module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1]
-        input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
-        input `read`: Ty1 @[module-XXXXXXXXXX.rs 3:1]
-        input `write`: Ty2 @[module-XXXXXXXXXX.rs 4:1]
-        mem `mem`: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => UInt<513>[2]
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        wire mem_r0: Ty3 @[module-XXXXXXXXXX.rs 6:1]
-        wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 11:1]
-        wire _cast_bits_to_enum_expr: Ty0
-        wire _cast_bits_to_enum_expr_body: UInt<512>
-        connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 512)
-        when eq(UInt<1>(0), tail(`mem`.r0.data[0], 512)):
-            connect _cast_bits_to_enum_expr, {|Text: UInt<512>, FmtError|}(Text, _cast_bits_to_enum_expr_body)
-        else:
-            connect _cast_bits_to_enum_expr, {|Text: UInt<512>, FmtError|}(FmtError)
-        connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 6:1]
-        wire _cast_bits_to_enum_expr_1: Ty0
-        wire _cast_bits_to_enum_expr_body_1: UInt<512>
-        connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 512)
-        when eq(UInt<1>(0), tail(`mem`.r0.data[1], 512)):
-            connect _cast_bits_to_enum_expr_1, {|Text: UInt<512>, FmtError|}(Text, _cast_bits_to_enum_expr_body_1)
-        else:
-            connect _cast_bits_to_enum_expr_1, {|Text: UInt<512>, FmtError|}(FmtError)
-        connect mem_r0.data[1], _cast_bits_to_enum_expr_1 @[module-XXXXXXXXXX.rs 6:1]
-        wire _cast_enum_to_bits_expr: UInt<513>
-        match mem_w1.data[0]:
-            Text(_cast_enum_to_bits_expr_Text):
-                connect _cast_enum_to_bits_expr, pad(cat(_cast_enum_to_bits_expr_Text, UInt<1>(0)), 513)
-            FmtError:
-                connect _cast_enum_to_bits_expr, UInt<513>(1)
-        connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1]
-        wire _cast_enum_to_bits_expr_1: UInt<513>
-        match mem_w1.data[1]:
-            Text(_cast_enum_to_bits_expr_Text_1):
-                connect _cast_enum_to_bits_expr_1, pad(cat(_cast_enum_to_bits_expr_Text_1, UInt<1>(0)), 513)
-            FmtError:
-                connect _cast_enum_to_bits_expr_1, UInt<513>(1)
-        connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1]
-        connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1]
-        connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1]
-        connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 7:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect mem_r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1]
-        connect mem_r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1]
-        connect `read`.data[0], mem_r0.data[0] @[module-XXXXXXXXXX.rs 10:1]
-        connect `read`.data[1], mem_r0.data[1] @[module-XXXXXXXXXX.rs 10:1]
-        connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 12:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect mem_w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1]
-        connect mem_w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1]
-        connect mem_w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1]
-"#,
-        "/test/sim_trace_as_string/mem.mem": r"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-",
-    };
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_memories: false,
-            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
-            ..ExportOptions::default()
-        },
-        "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0
-circuit sim_trace_as_string: %[[
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem.mem",
-    "hexOrBinary": "b",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem"
-  }
-]]
-    type Ty0 = {|Text, FmtError|}
-    type Ty1 = {tag: Ty0, body: UInt<512>}
-    type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty1[2]}
-    type Ty3 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]}
-    type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]}
-    type Ty5 = {tag: UInt<1>, body: UInt<1>}
-    type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: Ty5[2]}
-    type Ty7 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty1[2]}
-    module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1]
-        input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
-        input `read`: Ty2 @[module-XXXXXXXXXX.rs 3:1]
-        input `write`: Ty3 @[module-XXXXXXXXXX.rs 4:1]
-        mem `mem`: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => Ty1[2]
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.data, mem_w1.data @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.mask[0].tag, mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.mask[0].body, mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.mask[1].tag, mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.w1.mask[1].body, mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1]
-        connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 7:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect `mem`.r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1]
-        connect `mem`.r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1]
-        connect `read`.data[0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 10:1]
-        connect `read`.data[1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 10:1]
-        connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 12:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect mem_w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1]
-        connect mem_w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1]
-        connect mem_w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1]
-"#,
-        "/test/sim_trace_as_string/mem.mem": r"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-",
-    };
-    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
-    assert_export_firrtl! {
-        m =>
-        options: ExportOptions {
-            simplify_memories: true,
-            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
-            ..ExportOptions::default()
-        },
-        "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0
-circuit sim_trace_as_string: %[[
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem_0_tag.mem",
-    "hexOrBinary": "b",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem_0_tag"
-  },
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem_0_body.mem",
-    "hexOrBinary": "h",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem_0_body"
-  },
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem_1_tag.mem",
-    "hexOrBinary": "b",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem_1_tag"
-  },
-  {
-    "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/sim_trace_as_string/mem_1_body.mem",
-    "hexOrBinary": "h",
-    "target": "~sim_trace_as_string|sim_trace_as_string>mem_1_body"
-  }
-]]
-    type Ty0 = {|Text, FmtError|}
-    type Ty1 = {tag: Ty0, body: UInt<512>}
-    type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty1[2]}
-    type Ty3 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]}
-    type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty1[2]}
-    type Ty5 = {tag: UInt<1>, body: UInt<1>}
-    type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: Ty5[2]}
-    type Ty7 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<1>}
-    type Ty8 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<1>, mask: UInt<1>}
-    type Ty9 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<512>}
-    type Ty10 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<512>, mask: UInt<1>}
-    type Ty11 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]}
-    module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1]
-        input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
-        input `read`: Ty2 @[module-XXXXXXXXXX.rs 3:1]
-        input `write`: Ty3 @[module-XXXXXXXXXX.rs 4:1]
-        mem mem_0_tag: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => UInt<1>
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        mem mem_0_body: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => UInt<512>
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        mem mem_1_tag: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => UInt<1>
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        mem mem_1_body: @[module-XXXXXXXXXX.rs 5:1]
-            data-type => UInt<512>
-            depth => 4
-            read-latency => 0
-            write-latency => 1
-            read-under-write => old
-            reader => r0
-            writer => w1
-        wire mem_r0: Ty4 @[module-XXXXXXXXXX.rs 6:1]
-        wire mem_w1: Ty6 @[module-XXXXXXXXXX.rs 11:1]
-        wire _cast_bits_to_enum_expr: Ty0
-        when eq(UInt<1>(0), tail(mem_0_tag.r0.data, 0)):
-            connect _cast_bits_to_enum_expr, {|Text, FmtError|}(Text)
-        else:
-            connect _cast_bits_to_enum_expr, {|Text, FmtError|}(FmtError)
-        connect mem_r0.data[0].tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 6:1]
-        wire _cast_enum_to_bits_expr: UInt<1>
-        match mem_w1.data[0].tag:
-            Text:
-                connect _cast_enum_to_bits_expr, UInt<1>(0)
-            FmtError:
-                connect _cast_enum_to_bits_expr, UInt<1>(1)
-        connect mem_0_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_tag.w1.mask, mem_w1.mask[0].tag @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_r0.data[0].body, mem_0_body.r0.data @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_body.w1.data, mem_w1.data[0].body @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_body.w1.mask, mem_w1.mask[0].body @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_0_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_0_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1]
-        wire _cast_bits_to_enum_expr_1: Ty0
-        when eq(UInt<1>(0), tail(mem_1_tag.r0.data, 0)):
-            connect _cast_bits_to_enum_expr_1, {|Text, FmtError|}(Text)
-        else:
-            connect _cast_bits_to_enum_expr_1, {|Text, FmtError|}(FmtError)
-        connect mem_r0.data[1].tag, _cast_bits_to_enum_expr_1 @[module-XXXXXXXXXX.rs 6:1]
-        wire _cast_enum_to_bits_expr_1: UInt<1>
-        match mem_w1.data[1].tag:
-            Text:
-                connect _cast_enum_to_bits_expr_1, UInt<1>(0)
-            FmtError:
-                connect _cast_enum_to_bits_expr_1, UInt<1>(1)
-        connect mem_1_tag.w1.data, _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_tag.w1.mask, mem_w1.mask[1].tag @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_r0.data[1].body, mem_1_body.r0.data @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_body.w1.data, mem_w1.data[1].body @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_body.w1.mask, mem_w1.mask[1].body @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1]
-        connect mem_1_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_1_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1]
-        wire mem_w1_1: Ty11 @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.mask[0].tag, mem_w1_1.mask[0] @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.mask[0].body, mem_w1_1.mask[0] @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.mask[1].tag, mem_w1_1.mask[1] @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_w1.mask[1].body, mem_w1_1.mask[1] @[module-XXXXXXXXXX.rs 11:1]
-        connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 7:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect mem_r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1]
-        connect mem_r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1]
-        connect `read`.data[0], mem_r0.data[0] @[module-XXXXXXXXXX.rs 10:1]
-        connect `read`.data[1], mem_r0.data[1] @[module-XXXXXXXXXX.rs 10:1]
-        connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 12:1]
-        ; connect different types:
-        ; lhs: UInt<2>
-        ; rhs: UInt<8>
-        connect mem_w1_1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1]
-        connect mem_w1_1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1]
-        connect mem_w1_1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1]
-"#,
-        "/test/sim_trace_as_string/mem_0_body.mem": r"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-",
-        "/test/sim_trace_as_string/mem_0_tag.mem": r"0
-0
-0
-0
-",
-        "/test/sim_trace_as_string/mem_1_body.mem": r"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-",
-        "/test/sim_trace_as_string/mem_1_tag.mem": r"0
-0
-0
-0
-",
-    };
-}
-
-#[hdl_module(outline_generated)]
-pub fn formal_counter(count_modulus: u8, asserted_max_count: u8) {
-    #[hdl]
-    let cd = wire();
-    connect(
-        cd,
-        #[hdl]
-        ClockDomain {
-            clk: formal_global_clock(),
-            rst: formal_reset(),
-        },
-    );
-    #[hdl]
-    let count_reg: UInt<8> = reg_builder().clock_domain(cd).reset(0u8);
-    let next_count = count_reg + 1u8;
-    #[hdl]
-    if next_count.cmp_lt(count_modulus) {
-        connect_any(count_reg, next_count);
-    } else {
-        connect(count_reg, 0u8);
-    }
-    #[hdl]
-    let count: UInt<8> = m.output();
-    connect(count, count_reg);
-    #[hdl]
-    let enable_assert: Bool = m.input();
-    #[hdl]
-    if enable_assert {
-        hdl_assert(cd.clk, count_reg.cmp_le(asserted_max_count), "");
-    }
-    #[hdl]
-    let any_seq_out: UInt<16> = m.output();
-    connect(any_seq_out, any_seq(any_seq_out.ty()));
-}
-
-#[hdl]
-#[test]
-fn test_formal_counter() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let mut sim = Simulation::new(formal_counter(10, 10));
-    let _checked_vcd_output =
-        checked_vcd_output!(&mut sim, "tests/sim/expected/test_formal_counter.vcd");
-    let Some((_, any_seq_in)) = sim
-        .global_io()
-        .into_iter()
-        .find(|(global, _)| global.kind() == FormalInputKind::AnySeq)
-    else {
-        panic!("can't find any_seq");
-    };
-    let any_seq_in = Expr::<UInt<16>>::from_canonical(any_seq_in);
-    sim.write_clock(formal_global_clock(), false);
-    sim.write_reset(formal_reset(), true);
-    sim.write(any_seq_in, 0u16);
-    sim.write(sim.io().enable_assert, true);
-    sim.advance_time(SimDuration::from_micros(1));
-    assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 0u16);
-    sim.write_clock(formal_global_clock(), true);
-    sim.write(any_seq_in, 1234u16);
-    assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 1234u16);
-    assert_eq!(sim.read(sim.io().count).as_int(), 0);
-    sim.write_reset(formal_reset(), false);
-    sim.advance_time(SimDuration::from_micros(1));
-    for i in 0..32u8 {
-        assert_eq!(i % 10, sim.read(sim.io().count).as_int());
-        sim.write_clock(formal_global_clock(), false);
-        sim.advance_time(SimDuration::from_micros(1));
-        sim.write_clock(formal_global_clock(), true);
-        sim.advance_time(SimDuration::from_micros(1));
-    }
-    let sim_debug = format!("{sim:#?}");
-    println!("#######\n{sim_debug}\n#######");
-    if sim_debug != include_str!("sim/expected/test_formal_counter.txt") {
-        panic!();
-    }
-}
-
-#[cfg(panic = "unwind")]
-#[hdl]
-#[test]
-fn test_formal_counter_assert() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let mut sim = Simulation::new(formal_counter(10, 8));
-    let _checked_vcd_output = checked_vcd_output!(
-        &mut sim,
-        "tests/sim/expected/test_formal_counter_assert.vcd"
-    );
-    let Some((_, any_seq_in)) = sim
-        .global_io()
-        .into_iter()
-        .find(|(global, _)| global.kind() == FormalInputKind::AnySeq)
-    else {
-        panic!("can't find any_seq");
-    };
-    let any_seq_in = Expr::<UInt<16>>::from_canonical(any_seq_in);
-    let half_us = SimDuration::from_nanos(500);
-    sim.write_clock(formal_global_clock(), false);
-    sim.write_reset(formal_reset(), true);
-    sim.write(any_seq_in, 0u16);
-    sim.write(sim.io().enable_assert, false);
-    sim.advance_time(half_us);
-    assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 0u16);
-    sim.write_clock(formal_global_clock(), true);
-    sim.write(any_seq_in, 1234u16);
-    assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 1234u16);
-    assert_eq!(sim.read(sim.io().count).as_int(), 0);
-    sim.write_reset(formal_reset(), false);
-    sim.advance_time(half_us);
-    const PANIC_MSG: &str = "Assertions/Assumptions failed at time 20.500000000000 \u{3bc}s:\n\
-at module-XXXXXXXXXX.rs:12:1: in InstantiatedModule(formal_counter: formal_counter): assert failed: \n";
-    const EXPECTED_FAILURE_CYCLE: u8 = 19;
-    for i in 0.. {
-        dbg!(i);
-        assert_eq!(i % 10, sim.read(sim.io().count).as_int());
-        sim.write(sim.io().enable_assert, i > 15);
-        sim.write_clock(formal_global_clock(), false);
-        sim.advance_time(half_us);
-        match catch_unwind(AssertUnwindSafe(|| {
-            sim.write_clock(formal_global_clock(), true);
-            sim.advance_time(half_us);
-        })) {
-            Ok(()) => assert!(i < EXPECTED_FAILURE_CYCLE),
-            Err(e) => match e.downcast::<String>() {
-                Ok(e) if *e == PANIC_MSG => {
-                    assert_eq!(i, EXPECTED_FAILURE_CYCLE);
-                    break;
-                }
-                Ok(e) => resume_unwind(e),
-                Err(e) => resume_unwind(e),
-            },
-        }
-    }
-}

crates/fayalite/tests/sim/expected/array_rw.txt

@@ -419,7 +419,6 @@ Simulation {
         },
         pc: 38,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -498,7 +497,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1220,7 +1218,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xff,
             last_state: 0xff,
         },
@@ -1230,7 +1227,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(1),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x7f,
             last_state: 0x7f,
         },
@@ -1240,7 +1236,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x3f,
             last_state: 0x3f,
         },
@@ -1250,7 +1245,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1260,7 +1254,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x0f,
             last_state: 0x0f,
         },
@@ -1270,7 +1263,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x07,
             last_state: 0x07,
         },
@@ -1280,7 +1272,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(6),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x03,
             last_state: 0x03,
         },
@@ -1290,7 +1281,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(7),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x01,
             last_state: 0x01,
         },
@@ -1300,7 +1290,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(8),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -1310,7 +1299,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x80,
             last_state: 0x80,
         },
@@ -1320,7 +1308,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xc0,
             last_state: 0xc0,
         },
@@ -1330,7 +1317,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xe0,
             last_state: 0xe0,
         },
@@ -1340,7 +1326,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(12),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xf0,
             last_state: 0xf0,
         },
@@ -1350,7 +1335,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(13),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xf8,
             last_state: 0xf8,
         },
@@ -1360,7 +1344,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xfc,
             last_state: 0xfc,
         },
@@ -1370,7 +1353,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xfe,
             last_state: 0xfe,
         },
@@ -1380,7 +1362,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(16),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xff,
             last_state: 0xff,
         },
@@ -1390,7 +1371,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(17),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x7f,
             last_state: 0x7f,
         },
@@ -1400,7 +1380,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x3f,
             last_state: 0x3f,
         },
@@ -1410,7 +1389,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(19),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1420,7 +1398,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(20),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x0f,
             last_state: 0x0f,
         },
@@ -1430,7 +1407,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(21),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x07,
             last_state: 0x07,
         },
@@ -1440,7 +1416,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x03,
             last_state: 0x03,
         },
@@ -1450,7 +1425,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(23),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x01,
             last_state: 0x01,
         },
@@ -1460,7 +1434,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(24),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -1470,7 +1443,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x80,
             last_state: 0x80,
         },
@@ -1480,7 +1452,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(26),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xc0,
             last_state: 0xc0,
         },
@@ -1490,7 +1461,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(27),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xe0,
             last_state: 0xe0,
         },
@@ -1500,7 +1470,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(28),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xf0,
             last_state: 0xf0,
         },
@@ -1510,7 +1479,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(29),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xf8,
             last_state: 0xf8,
         },
@@ -1520,7 +1488,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(30),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xfc,
             last_state: 0xfc,
         },
@@ -1530,7 +1497,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(31),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xfe,
             last_state: 0xe1,
         },
@@ -1540,7 +1506,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(32),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -1550,7 +1515,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(33),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xff,
             last_state: 0xff,
         },
@@ -1560,7 +1524,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(34),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x10,
             last_state: 0x0f,
         },
@@ -1570,7 +1533,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(35),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0xe1,
         },
@@ -1579,7 +1541,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1589,7 +1550,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(37),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xff,
             last_state: 0xff,
         },
@@ -1599,7 +1559,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(38),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x7f,
             last_state: 0x7f,
         },
@@ -1609,7 +1568,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(39),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x3f,
             last_state: 0x3f,
         },
@@ -1619,7 +1577,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(40),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1629,7 +1586,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(41),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x0f,
             last_state: 0x0f,
         },
@@ -1639,7 +1595,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x07,
             last_state: 0x07,
         },
@@ -1649,7 +1604,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(43),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x03,
             last_state: 0x03,
         },
@@ -1659,7 +1613,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(44),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x01,
             last_state: 0x01,
         },
@@ -1669,7 +1622,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(45),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -1679,7 +1631,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(46),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x80,
             last_state: 0x80,
         },
@@ -1689,7 +1640,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(47),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xc0,
             last_state: 0xc0,
         },
@@ -1699,7 +1649,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(48),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xe0,
             last_state: 0xe0,
         },
@@ -1709,7 +1658,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(49),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xf0,
             last_state: 0xf0,
         },
@@ -1719,7 +1667,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(50),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xf8,
             last_state: 0xf8,
         },
@@ -1729,7 +1676,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(51),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xfc,
             last_state: 0xfc,
         },
@@ -1739,7 +1685,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(52),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xfe,
             last_state: 0xe1,
         },
@@ -1761,6 +1706,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/conditional_assignment_last.txt

@@ -76,7 +76,6 @@ Simulation {
         },
         pc: 5,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -102,7 +101,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -157,7 +155,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -166,7 +163,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -188,6 +184,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/connect_const.txt

@@ -54,7 +54,6 @@ Simulation {
         },
         pc: 2,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -78,7 +77,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -126,7 +124,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x05,
             last_state: 0x05,
         },
@@ -140,6 +137,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/connect_const_reset.txt

@@ -80,7 +80,6 @@ Simulation {
         },
         pc: 5,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -107,7 +106,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -177,7 +175,6 @@ Simulation {
             kind: BigAsyncReset {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -186,7 +183,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -208,6 +204,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/counter_async.txt

@@ -180,7 +180,6 @@ Simulation {
         },
         pc: 19,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -217,7 +216,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -334,7 +332,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -343,7 +340,6 @@ Simulation {
             kind: BigAsyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -353,7 +349,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x2,
         },
@@ -363,7 +358,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x2,
         },
@@ -387,6 +381,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/counter_sync.txt

@@ -162,7 +162,6 @@ Simulation {
         },
         pc: 16,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -198,7 +197,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -315,7 +313,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -324,7 +321,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -334,7 +330,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x2,
         },
@@ -344,7 +339,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x2,
         },
@@ -368,6 +362,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/duplicate_names.txt

@@ -72,7 +72,6 @@ Simulation {
         },
         pc: 4,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -98,7 +97,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [],
         uninitialized_ios: {},
@@ -139,7 +137,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x05,
             last_state: 0x05,
         },
@@ -149,7 +146,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x06,
             last_state: 0x06,
         },
@@ -171,6 +167,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/enum_with_simple_body.txt

@@ -1,752 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    A,
-                                    B,
-                                    C,
-                                },
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 33,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out",
-                                ty: Enum {
-                                    A(UInt<8>),
-                                    B(UInt<8>),
-                                    C(UInt<8>),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    A(UInt<8>),
-                                    B(UInt<8>),
-                                    C(UInt<8>),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    A(UInt<8>),
-                                    B(UInt<8>),
-                                    C(UInt<8>),
-                                },
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<10>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    A(UInt<8>),
-                                    B(UInt<8>),
-                                    C(UInt<8>),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                    sim_only_slots: StatePartLayout<SimOnlySlots> {
-                        len: 0,
-                        debug_data: [],
-                        layout_data: [],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(32), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x2,
-                },
-                1: Const {
-                    dest: StatePartIndex<BigSlots>(27), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x2,
-                },
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(27), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(26), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> },
-                },
-                4: Shl {
-                    dest: StatePartIndex<BigSlots>(28), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                    lhs: StatePartIndex<BigSlots>(26), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> },
-                    rhs: 2,
-                },
-                5: Or {
-                    dest: StatePartIndex<BigSlots>(29), // (0x386) SlotDebugData { name: "", ty: UInt<10> },
-                    lhs: StatePartIndex<BigSlots>(25), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(28), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                },
-                6: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(30), // (0x386) SlotDebugData { name: "", ty: UInt<10> },
-                    src: StatePartIndex<BigSlots>(29), // (0x386) SlotDebugData { name: "", ty: UInt<10> },
-                    dest_width: 10,
-                },
-                7: Copy {
-                    dest: StatePartIndex<BigSlots>(31), // (0x386) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    src: StatePartIndex<BigSlots>(30), // (0x386) SlotDebugData { name: "", ty: UInt<10> },
-                },
-                8: Const {
-                    dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x1,
-                },
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> },
-                },
-                11: Shl {
-                    dest: StatePartIndex<BigSlots>(21), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                    lhs: StatePartIndex<BigSlots>(19), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> },
-                    rhs: 2,
-                },
-                12: Or {
-                    dest: StatePartIndex<BigSlots>(22), // (0x385) SlotDebugData { name: "", ty: UInt<10> },
-                    lhs: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(21), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                },
-                13: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(23), // (0x385) SlotDebugData { name: "", ty: UInt<10> },
-                    src: StatePartIndex<BigSlots>(22), // (0x385) SlotDebugData { name: "", ty: UInt<10> },
-                    dest_width: 10,
-                },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(24), // (0x385) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    src: StatePartIndex<BigSlots>(23), // (0x385) SlotDebugData { name: "", ty: UInt<10> },
-                },
-                15: Const {
-                    dest: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x1,
-                },
-                16: CmpEq {
-                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", ty: UInt<8> },
-                    rhs: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                17: Const {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x0,
-                },
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                19: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> },
-                },
-                20: Shl {
-                    dest: StatePartIndex<BigSlots>(12), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                    lhs: StatePartIndex<BigSlots>(10), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> },
-                    rhs: 2,
-                },
-                21: Or {
-                    dest: StatePartIndex<BigSlots>(13), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                    lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(12), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                },
-                22: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(14), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                    src: StatePartIndex<BigSlots>(13), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                    dest_width: 10,
-                },
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(15), // (0x384) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    src: StatePartIndex<BigSlots>(14), // (0x384) SlotDebugData { name: "", ty: UInt<10> },
-                },
-                24: Const {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x0,
-                },
-                25: CmpEq {
-                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", ty: UInt<8> },
-                    rhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:7:1
-                26: BranchIfZero {
-                    target: 28,
-                    value: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:8:1
-                27: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    src: StatePartIndex<BigSlots>(15), // (0x384) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                },
-                // at: module-XXXXXXXXXX.rs:7:1
-                28: BranchIfNonZero {
-                    target: 33,
-                    value: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                29: BranchIfZero {
-                    target: 31,
-                    value: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:10:1
-                30: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    src: StatePartIndex<BigSlots>(24), // (0x385) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                31: BranchIfNonZero {
-                    target: 33,
-                    value: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                32: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    src: StatePartIndex<BigSlots>(31), // (0x386) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                33: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x386) SlotDebugData { name: "", ty: UInt<10> },
-                    src: StatePartIndex<BigSlots>(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                },
-                34: SliceInt {
-                    dest: StatePartIndex<BigSlots>(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(5), // (0x386) SlotDebugData { name: "", ty: UInt<10> },
-                    start: 2,
-                    len: 8,
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                35: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    lhs: StatePartIndex<BigSlots>(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} },
-                    rhs: 0x3,
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                36: BranchIfSmallNeImmediate {
-                    target: 39,
-                    lhs: StatePartIndex<SmallSlots>(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x0,
-                },
-                // at: module-XXXXXXXXXX.rs:13:1
-                37: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:14:1
-                38: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                39: BranchIfSmallNeImmediate {
-                    target: 42,
-                    lhs: StatePartIndex<SmallSlots>(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:15:1
-                40: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:16:1
-                41: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                42: BranchIfSmallNeImmediate {
-                    target: 45,
-                    lhs: StatePartIndex<SmallSlots>(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x2,
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                43: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(32), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:18:1
-                44: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                45: Return,
-            ],
-            ..
-        },
-        pc: 45,
-        memory_write_log: [],
-        assert_failed_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [
-                2,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                2,
-                225,
-                2 (modified),
-                225 (modified),
-                902,
-                902,
-                225,
-                0,
-                0,
-                0,
-                225,
-                0,
-                900,
-                900,
-                900,
-                900,
-                1,
-                0,
-                1,
-                225,
-                1,
-                900,
-                901,
-                901,
-                901,
-                2,
-                225,
-                2,
-                900,
-                902,
-                902,
-                902,
-                2,
-            ],
-        },
-        sim_only_slots: StatePart {
-            value: [],
-        },
-    },
-    io: Instance {
-        name: <simulator>::enum_with_simple_body,
-        instantiated: Module {
-            name: enum_with_simple_body,
-            ..
-        },
-    },
-    global_io: {},
-    main_module: SimulationModuleState {
-        base_targets: [
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.which_in,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.data_in,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.which_out,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.data_out,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.enum_out,
-        ],
-        uninitialized_ios: {},
-        io_targets: {
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.data_in,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.data_out,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.enum_out,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.which_in,
-            Instance {
-                name: <simulator>::enum_with_simple_body,
-                instantiated: Module {
-                    name: enum_with_simple_body,
-                    ..
-                },
-            }.which_out,
-        },
-        did_initial_settle: true,
-        clocks_for_past: {},
-    },
-    extern_modules: [],
-    trace_decls: TraceModule {
-        name: "enum_with_simple_body",
-        children: [
-            TraceModuleIO {
-                name: "which_in",
-                child: TraceUInt {
-                    location: TraceScalarId(0),
-                    name: "which_in",
-                    ty: UInt<8>,
-                    flow: Source,
-                },
-                ty: UInt<8>,
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "data_in",
-                child: TraceUInt {
-                    location: TraceScalarId(1),
-                    name: "data_in",
-                    ty: UInt<8>,
-                    flow: Source,
-                },
-                ty: UInt<8>,
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "which_out",
-                child: TraceUInt {
-                    location: TraceScalarId(2),
-                    name: "which_out",
-                    ty: UInt<8>,
-                    flow: Sink,
-                },
-                ty: UInt<8>,
-                flow: Sink,
-            },
-            TraceModuleIO {
-                name: "data_out",
-                child: TraceUInt {
-                    location: TraceScalarId(3),
-                    name: "data_out",
-                    ty: UInt<8>,
-                    flow: Sink,
-                },
-                ty: UInt<8>,
-                flow: Sink,
-            },
-            TraceModuleIO {
-                name: "enum_out",
-                child: TraceEnumWithFields {
-                    name: "enum_out",
-                    discriminant: TraceEnumDiscriminant {
-                        location: TraceScalarId(4),
-                        name: "$tag",
-                        ty: Enum {
-                            A(UInt<8>),
-                            B(UInt<8>),
-                            C(UInt<8>),
-                        },
-                        flow: Sink,
-                    },
-                    non_empty_fields: [
-                        TraceUInt {
-                            location: TraceScalarId(5),
-                            name: "A",
-                            ty: UInt<8>,
-                            flow: Source,
-                        },
-                        TraceUInt {
-                            location: TraceScalarId(6),
-                            name: "B",
-                            ty: UInt<8>,
-                            flow: Source,
-                        },
-                        TraceUInt {
-                            location: TraceScalarId(7),
-                            name: "C",
-                            ty: UInt<8>,
-                            flow: Source,
-                        },
-                    ],
-                    ty: Enum {
-                        A(UInt<8>),
-                        B(UInt<8>),
-                        C(UInt<8>),
-                    },
-                    flow: Sink,
-                },
-                ty: Enum {
-                    A(UInt<8>),
-                    B(UInt<8>),
-                    C(UInt<8>),
-                },
-                flow: Sink,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0x02,
-            last_state: 0x02,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(1),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0xe1,
-            last_state: 0xb4,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0x02,
-            last_state: 0x02,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0xe1,
-            last_state: 0xb4,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(0),
-                ty: Enum {
-                    A(UInt<8>),
-                    B(UInt<8>),
-                    C(UInt<8>),
-                },
-            },
-            maybe_changed: true,
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(6),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0xe1,
-            last_state: 0xb4,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(6),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0xe1,
-            last_state: 0xb4,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(6),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0xe1,
-            last_state: 0xb4,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    clocks_triggered: [],
-    event_queue: EventQueue(EventQueueData {
-        instant: 18 μs,
-        events: {},
-    }),
-    waiting_sensitivity_sets_by_address: {},
-    waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
-    ..
-}

crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd

@@ -1,133 +0,0 @@
-$timescale 1 ps $end
-$scope module enum_with_simple_body $end
-$var wire 8 J&-ne which_in $end
-$var wire 8 \7mo/ data_in $end
-$var wire 8 ,`>ir which_out $end
-$var wire 8 0_gMP data_out $end
-$scope struct enum_out $end
-$var string 1 kFH/w \$tag $end
-$var wire 8 |EI_= A $end
-$var wire 8 !pRd4 B $end
-$var wire 8 &RAbd C $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b0 J&-ne
-b0 \7mo/
-b0 ,`>ir
-b0 0_gMP
-sA\x20(0) kFH/w
-b0 |EI_=
-b0 !pRd4
-b0 &RAbd
-$end
-#1000000
-b101101 \7mo/
-b101101 0_gMP
-b101101 |EI_=
-b101101 !pRd4
-b101101 &RAbd
-#2000000
-b1011010 \7mo/
-b1011010 0_gMP
-b1011010 |EI_=
-b1011010 !pRd4
-b1011010 &RAbd
-#3000000
-b10000111 \7mo/
-b10000111 0_gMP
-b10000111 |EI_=
-b10000111 !pRd4
-b10000111 &RAbd
-#4000000
-b10110100 \7mo/
-b10110100 0_gMP
-b10110100 |EI_=
-b10110100 !pRd4
-b10110100 &RAbd
-#5000000
-b11100001 \7mo/
-b11100001 0_gMP
-b11100001 |EI_=
-b11100001 !pRd4
-b11100001 &RAbd
-#6000000
-b1 J&-ne
-b0 \7mo/
-b1 ,`>ir
-b0 0_gMP
-sB\x20(1) kFH/w
-b0 |EI_=
-b0 !pRd4
-b0 &RAbd
-#7000000
-b101101 \7mo/
-b101101 0_gMP
-b101101 |EI_=
-b101101 !pRd4
-b101101 &RAbd
-#8000000
-b1011010 \7mo/
-b1011010 0_gMP
-b1011010 |EI_=
-b1011010 !pRd4
-b1011010 &RAbd
-#9000000
-b10000111 \7mo/
-b10000111 0_gMP
-b10000111 |EI_=
-b10000111 !pRd4
-b10000111 &RAbd
-#10000000
-b10110100 \7mo/
-b10110100 0_gMP
-b10110100 |EI_=
-b10110100 !pRd4
-b10110100 &RAbd
-#11000000
-b11100001 \7mo/
-b11100001 0_gMP
-b11100001 |EI_=
-b11100001 !pRd4
-b11100001 &RAbd
-#12000000
-b10 J&-ne
-b0 \7mo/
-b10 ,`>ir
-b0 0_gMP
-sC\x20(2) kFH/w
-b0 |EI_=
-b0 !pRd4
-b0 &RAbd
-#13000000
-b101101 \7mo/
-b101101 0_gMP
-b101101 |EI_=
-b101101 !pRd4
-b101101 &RAbd
-#14000000
-b1011010 \7mo/
-b1011010 0_gMP
-b1011010 |EI_=
-b1011010 !pRd4
-b1011010 &RAbd
-#15000000
-b10000111 \7mo/
-b10000111 0_gMP
-b10000111 |EI_=
-b10000111 !pRd4
-b10000111 &RAbd
-#16000000
-b10110100 \7mo/
-b10110100 0_gMP
-b10110100 |EI_=
-b10110100 !pRd4
-b10110100 &RAbd
-#17000000
-b11100001 \7mo/
-b11100001 0_gMP
-b11100001 |EI_=
-b11100001 !pRd4
-b11100001 &RAbd
-#18000000

crates/fayalite/tests/sim/expected/enums.txt

@@ -1184,7 +1184,6 @@ Simulation {
         },
         pc: 133,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -1325,7 +1324,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1748,7 +1746,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -1757,7 +1754,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1766,7 +1762,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: false,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1776,7 +1771,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<2>,
             },
-            maybe_changed: false,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1786,7 +1780,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<4>,
             },
-            maybe_changed: false,
             state: 0xf,
             last_state: 0xf,
         },
@@ -1796,7 +1789,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1806,7 +1798,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(6),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xf,
             last_state: 0xf,
         },
@@ -1819,7 +1810,6 @@ Simulation {
                     HdlSome(Bundle {0: UInt<1>, 1: Bool}),
                 },
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1829,7 +1819,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(8),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1838,7 +1827,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(9),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1851,7 +1839,6 @@ Simulation {
                     HdlSome(Bundle {0: UInt<1>, 1: Bool}),
                 },
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1861,7 +1848,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(16),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1870,7 +1856,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1884,7 +1869,6 @@ Simulation {
                     C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
                 },
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1894,7 +1878,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(27),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1903,7 +1886,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(28),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1913,7 +1895,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(34),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1923,7 +1904,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(35),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1933,7 +1913,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(36),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -1957,6 +1936,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/extern_module.txt

@@ -44,7 +44,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -68,7 +67,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -223,7 +221,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: false,
             state: 0x1,
             last_state: 0x1,
         },
@@ -232,7 +229,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -263,6 +259,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/extern_module2.txt

@@ -48,7 +48,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -58,7 +57,7 @@ Simulation {
         big_slots: StatePart {
             value: [
                 0,
-                1 (modified),
+                1,
                 101,
             ],
         },
@@ -73,7 +72,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -282,7 +280,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -291,7 +288,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -301,7 +297,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x65,
             last_state: 0x65,
         },
@@ -418,6 +413,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/last_connect.txt

@@ -407,7 +407,6 @@ Simulation {
         },
         pc: 44,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -434,7 +433,7 @@ Simulation {
                 1,
                 1,
                 1,
-                7 (modified),
+                7,
                 7,
                 3,
                 0,
@@ -465,7 +464,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -616,7 +614,6 @@ Simulation {
                     HdlSome(Array<Bool, 4>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -625,7 +622,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -634,7 +630,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -643,7 +638,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -652,7 +646,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(4),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -665,7 +658,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -675,7 +667,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(17),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x03,
             last_state: 0x02,
         },
@@ -685,7 +676,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(20),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x03,
             last_state: 0x02,
         },
@@ -707,6 +697,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/memories.txt

@@ -494,7 +494,6 @@ Simulation {
         },
         pc: 41,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -580,7 +579,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1170,7 +1168,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1179,7 +1176,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1188,7 +1184,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1198,7 +1193,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xb0,
             last_state: 0xb0,
         },
@@ -1208,7 +1202,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: SInt<8>,
             },
-            maybe_changed: true,
             state: 0xc0,
             last_state: 0xc0,
         },
@@ -1218,7 +1211,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1227,7 +1219,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(6),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1236,7 +1227,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1246,7 +1236,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(8),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xd0,
             last_state: 0xd0,
         },
@@ -1256,7 +1245,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: SInt<8>,
             },
-            maybe_changed: true,
             state: 0xe0,
             last_state: 0xe0,
         },
@@ -1265,7 +1253,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(10),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1274,7 +1261,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(11),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1284,7 +1270,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(12),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1293,7 +1278,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1302,7 +1286,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(14),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1312,7 +1295,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xb0,
             last_state: 0xb0,
         },
@@ -1322,7 +1304,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(16),
                 ty: SInt<8>,
             },
-            maybe_changed: true,
             state: 0xc0,
             last_state: 0xc0,
         },
@@ -1332,7 +1313,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(17),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1341,7 +1321,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(18),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1350,7 +1329,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1360,7 +1338,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(20),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0xd0,
             last_state: 0xd0,
         },
@@ -1370,7 +1347,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(21),
                 ty: SInt<8>,
             },
-            maybe_changed: true,
             state: 0xe0,
             last_state: 0xe0,
         },
@@ -1379,7 +1355,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(22),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1388,7 +1363,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(23),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1652,6 +1626,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/memories2.txt

@@ -526,7 +526,6 @@ Simulation {
         },
         pc: 52,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -608,7 +607,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -945,7 +943,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -954,7 +951,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -963,7 +959,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -973,7 +968,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -982,7 +976,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(4),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -992,7 +985,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<2>,
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1001,7 +993,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(6),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1011,7 +1002,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(7),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1020,7 +1010,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(8),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1029,7 +1018,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(9),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1042,7 +1030,6 @@ Simulation {
                     HdlSome(Bool),
                 },
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1051,7 +1038,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1060,7 +1046,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(11),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1073,7 +1058,6 @@ Simulation {
                     HdlSome(Bool),
                 },
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1082,7 +1066,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1091,7 +1074,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1287,6 +1269,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/memories3.txt

@@ -1336,7 +1336,6 @@ Simulation {
         },
         pc: 129,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1496,7 +1495,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -2393,7 +2391,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2402,7 +2399,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2411,7 +2407,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -2421,7 +2416,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2431,7 +2425,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2441,7 +2434,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2451,7 +2443,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(6),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2461,7 +2452,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(7),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2471,7 +2461,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(8),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2481,7 +2470,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2491,7 +2479,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2501,7 +2488,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2510,7 +2496,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2519,7 +2504,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -2529,7 +2513,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2539,7 +2522,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2549,7 +2531,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(16),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2559,7 +2540,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(17),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2569,7 +2549,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2579,7 +2558,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(19),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2589,7 +2567,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(20),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2599,7 +2576,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(21),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2608,7 +2584,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(22),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2617,7 +2592,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(23),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2626,7 +2600,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(24),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2635,7 +2608,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(25),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2644,7 +2616,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(26),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2653,7 +2624,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2662,7 +2632,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(28),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2671,7 +2640,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(29),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2681,7 +2649,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(30),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2690,7 +2657,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2699,7 +2665,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -2709,7 +2674,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(33),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2719,7 +2683,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(34),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2729,7 +2692,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(35),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2739,7 +2701,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(36),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2749,7 +2710,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(37),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2759,7 +2719,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(38),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2769,7 +2728,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(39),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2779,7 +2737,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(40),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2789,7 +2746,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(57),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2798,7 +2754,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(58),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2807,7 +2762,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(59),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -2817,7 +2771,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(60),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2827,7 +2780,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(61),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2837,7 +2789,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(62),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2847,7 +2798,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(63),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2857,7 +2807,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(64),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2867,7 +2816,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(65),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2877,7 +2825,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2887,7 +2834,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(67),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x00,
             last_state: 0x00,
         },
@@ -2896,7 +2842,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(68),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2905,7 +2850,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(69),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2914,7 +2858,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(70),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2923,7 +2866,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(71),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2932,7 +2874,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(72),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2941,7 +2882,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(73),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2950,7 +2890,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(74),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2959,7 +2898,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(75),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -3347,6 +3285,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/mod1.txt

@@ -187,7 +187,6 @@ Simulation {
         },
         pc: 17,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -226,7 +225,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -447,7 +445,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xa,
             last_state: 0x3,
         },
@@ -457,7 +454,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(1),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x3,
         },
@@ -467,7 +463,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -477,7 +472,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xf,
             last_state: 0xe,
         },
@@ -487,7 +481,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(8),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xa,
             last_state: 0x3,
         },
@@ -497,7 +490,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x3,
         },
@@ -507,7 +499,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -517,7 +508,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xf,
             last_state: 0xe,
         },
@@ -527,7 +517,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xa,
             last_state: 0x3,
         },
@@ -537,7 +526,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x3,
         },
@@ -547,7 +535,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(6),
                 ty: SInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -557,7 +544,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(7),
                 ty: UInt<4>,
             },
-            maybe_changed: true,
             state: 0xf,
             last_state: 0xe,
         },
@@ -579,6 +565,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/phantom_const.txt

@@ -172,7 +172,6 @@ Simulation {
         },
         pc: 16,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -216,7 +215,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -375,7 +373,6 @@ Simulation {
                     ["a","b"],
                 ),
             },
-            maybe_changed: true,
             state: PhantomConst,
             last_state: PhantomConst,
         },
@@ -386,7 +383,6 @@ Simulation {
                     ["a","b"],
                 ),
             },
-            maybe_changed: true,
             state: PhantomConst,
             last_state: PhantomConst,
         },
@@ -396,7 +392,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -405,7 +400,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -414,7 +408,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -425,7 +418,6 @@ Simulation {
                     "mem_element",
                 ),
             },
-            maybe_changed: true,
             state: PhantomConst,
             last_state: PhantomConst,
         },
@@ -529,6 +521,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_1_false_false.txt

@@ -1083,7 +1083,6 @@ Simulation {
         },
         pc: 134,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1202,7 +1201,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1724,7 +1722,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1733,7 +1730,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1746,7 +1742,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1756,7 +1751,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x19,
             last_state: 0x19,
         },
@@ -1765,7 +1759,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1778,7 +1771,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1788,7 +1780,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x19,
             last_state: 0x19,
         },
@@ -1797,7 +1788,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1807,7 +1797,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1817,7 +1806,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1826,7 +1814,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1835,7 +1822,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1845,7 +1831,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x19,
             last_state: 0x19,
         },
@@ -1855,7 +1840,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1864,7 +1848,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1873,7 +1856,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1883,7 +1865,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x19,
             last_state: 0x19,
         },
@@ -1892,7 +1873,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1902,7 +1882,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1912,7 +1891,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1921,7 +1899,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1930,7 +1907,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1939,7 +1915,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1948,7 +1923,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1957,7 +1931,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1966,7 +1939,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1975,7 +1947,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1984,7 +1955,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1994,7 +1964,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x19,
             last_state: 0x19,
         },
@@ -2004,7 +1973,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2162,6 +2130,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_1_false_true.txt

@@ -1064,7 +1064,6 @@ Simulation {
         },
         pc: 132,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1181,7 +1180,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1703,7 +1701,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1712,7 +1709,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1725,7 +1721,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1735,7 +1730,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1744,7 +1738,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1757,7 +1750,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1767,7 +1759,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1776,7 +1767,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1786,7 +1776,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1796,7 +1785,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1805,7 +1793,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1814,7 +1801,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1824,7 +1810,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1834,7 +1819,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1843,7 +1827,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1852,7 +1835,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1862,7 +1844,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1871,7 +1852,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1881,7 +1861,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1891,7 +1870,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1900,7 +1878,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1909,7 +1886,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1918,7 +1894,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1927,7 +1902,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1936,7 +1910,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1945,7 +1918,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1954,7 +1926,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1963,7 +1934,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1973,7 +1943,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1983,7 +1952,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(64),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2141,6 +2109,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_1_true_false.txt

@@ -1093,7 +1093,6 @@ Simulation {
         },
         pc: 136,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1212,7 +1211,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1734,7 +1732,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1743,7 +1740,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1756,7 +1752,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1766,7 +1761,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1775,7 +1769,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1788,7 +1781,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1798,7 +1790,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1807,7 +1798,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1817,7 +1807,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1827,7 +1816,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1836,7 +1824,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1845,7 +1832,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1855,7 +1841,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1865,7 +1850,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1874,7 +1858,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1883,7 +1866,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1893,7 +1875,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -1902,7 +1883,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1912,7 +1892,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1922,7 +1901,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1931,7 +1909,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1940,7 +1917,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1949,7 +1925,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1958,7 +1933,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1967,7 +1941,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1976,7 +1949,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1985,7 +1957,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1994,7 +1965,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2004,7 +1974,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x1f,
             last_state: 0x1f,
         },
@@ -2014,7 +1983,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2172,6 +2140,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_1_true_true.txt

@@ -1074,7 +1074,6 @@ Simulation {
         },
         pc: 134,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1191,7 +1190,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1713,7 +1711,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1722,7 +1719,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1735,7 +1731,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1745,7 +1740,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1754,7 +1748,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1767,7 +1760,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1777,7 +1769,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1786,7 +1777,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1796,7 +1786,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1806,7 +1795,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1815,7 +1803,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1824,7 +1811,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1834,7 +1820,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1844,7 +1829,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1853,7 +1837,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1862,7 +1845,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1872,7 +1854,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1881,7 +1862,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1891,7 +1871,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1901,7 +1880,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1910,7 +1888,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1919,7 +1896,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1928,7 +1904,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1937,7 +1912,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1946,7 +1920,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1955,7 +1928,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1964,7 +1936,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1973,7 +1944,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1983,7 +1953,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1993,7 +1962,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(64),
                 ty: UInt<0>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2151,6 +2119,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_2_false_false.txt

@@ -1098,7 +1098,6 @@ Simulation {
         },
         pc: 135,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1220,7 +1219,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1742,7 +1740,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1751,7 +1748,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1764,7 +1760,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1774,7 +1769,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1783,7 +1777,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1796,7 +1789,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1806,7 +1798,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1815,7 +1806,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1825,7 +1815,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1835,7 +1824,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1844,7 +1832,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1853,7 +1840,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1863,7 +1849,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1873,7 +1858,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1882,7 +1866,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1891,7 +1874,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1901,7 +1883,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -1910,7 +1891,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1920,7 +1900,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1930,7 +1909,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1939,7 +1917,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1948,7 +1925,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1957,7 +1933,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1966,7 +1941,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1975,7 +1949,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1984,7 +1957,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1993,7 +1965,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2002,7 +1973,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2012,7 +1982,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x23,
             last_state: 0x23,
         },
@@ -2022,7 +1991,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(68),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2180,6 +2148,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_2_false_true.txt

@@ -1079,7 +1079,6 @@ Simulation {
         },
         pc: 133,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1199,7 +1198,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1721,7 +1719,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1730,7 +1727,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1743,7 +1739,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1753,7 +1748,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -1762,7 +1756,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1775,7 +1768,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1785,7 +1777,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -1794,7 +1785,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1804,7 +1794,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1814,7 +1803,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1823,7 +1811,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1832,7 +1819,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1842,7 +1828,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -1852,7 +1837,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1861,7 +1845,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1870,7 +1853,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1880,7 +1862,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -1889,7 +1870,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1899,7 +1879,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1909,7 +1888,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1918,7 +1896,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1927,7 +1904,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1936,7 +1912,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1945,7 +1920,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1954,7 +1928,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1963,7 +1936,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1972,7 +1944,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1981,7 +1952,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1991,7 +1961,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -2001,7 +1970,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2159,6 +2127,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_2_true_false.txt

@@ -1108,7 +1108,6 @@ Simulation {
         },
         pc: 137,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1230,7 +1229,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1752,7 +1750,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1761,7 +1758,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1774,7 +1770,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1784,7 +1779,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x27,
             last_state: 0x27,
         },
@@ -1793,7 +1787,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1806,7 +1799,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1816,7 +1808,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -1825,7 +1816,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1835,7 +1825,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1845,7 +1834,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1854,7 +1842,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1863,7 +1850,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1873,7 +1859,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x26,
             last_state: 0x26,
         },
@@ -1883,7 +1868,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1892,7 +1876,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1901,7 +1884,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1911,7 +1893,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x27,
             last_state: 0x27,
         },
@@ -1920,7 +1901,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1930,7 +1910,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1940,7 +1919,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1949,7 +1927,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1958,7 +1935,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1967,7 +1943,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1976,7 +1951,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1985,7 +1959,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1994,7 +1967,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2003,7 +1975,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2012,7 +1983,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2022,7 +1992,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x27,
             last_state: 0x27,
         },
@@ -2032,7 +2001,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(68),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2190,6 +2158,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_2_true_true.txt

@@ -1089,7 +1089,6 @@ Simulation {
         },
         pc: 135,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1209,7 +1208,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1731,7 +1729,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1740,7 +1737,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1753,7 +1749,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1763,7 +1758,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2a,
             last_state: 0x2a,
         },
@@ -1772,7 +1766,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1785,7 +1778,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1795,7 +1787,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1804,7 +1795,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1814,7 +1804,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1824,7 +1813,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1833,7 +1821,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1842,7 +1829,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1852,7 +1838,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1862,7 +1847,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1871,7 +1855,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1880,7 +1863,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1890,7 +1872,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2a,
             last_state: 0x2a,
         },
@@ -1899,7 +1880,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1909,7 +1889,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1919,7 +1898,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1928,7 +1906,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1937,7 +1914,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1946,7 +1922,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1955,7 +1930,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1964,7 +1938,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1973,7 +1946,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1982,7 +1954,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1991,7 +1962,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2001,7 +1971,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2a,
             last_state: 0x2a,
         },
@@ -2011,7 +1980,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<1>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2169,6 +2137,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_3_false_false.txt

@@ -1125,7 +1125,6 @@ Simulation {
         },
         pc: 139,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1249,7 +1248,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1761,7 +1759,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1770,7 +1767,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1783,7 +1779,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1793,7 +1788,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x28,
             last_state: 0x28,
         },
@@ -1802,7 +1796,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1815,7 +1808,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1825,7 +1817,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x27,
             last_state: 0x27,
         },
@@ -1834,7 +1825,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1844,7 +1834,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1854,7 +1843,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1863,7 +1851,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1872,7 +1859,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1882,7 +1868,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x27,
             last_state: 0x27,
         },
@@ -1892,7 +1877,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1901,7 +1885,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1910,7 +1893,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1920,7 +1902,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x28,
             last_state: 0x28,
         },
@@ -1929,7 +1910,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1939,7 +1919,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1949,7 +1928,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1958,7 +1936,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1967,7 +1944,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1976,7 +1952,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1985,7 +1960,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1994,7 +1968,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2003,7 +1976,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2012,7 +1984,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2021,7 +1992,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2031,7 +2001,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x28,
             last_state: 0x28,
         },
@@ -2189,6 +2158,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_3_false_true.txt

@@ -1106,7 +1106,6 @@ Simulation {
         },
         pc: 137,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1228,7 +1227,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1740,7 +1738,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1749,7 +1746,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1762,7 +1758,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1772,7 +1767,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2a,
             last_state: 0x2a,
         },
@@ -1781,7 +1775,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1794,7 +1787,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1804,7 +1796,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1813,7 +1804,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1823,7 +1813,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1833,7 +1822,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1842,7 +1830,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1851,7 +1838,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1861,7 +1847,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1871,7 +1856,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1880,7 +1864,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1889,7 +1872,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1899,7 +1881,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2a,
             last_state: 0x2a,
         },
@@ -1908,7 +1889,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1918,7 +1898,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1928,7 +1907,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1937,7 +1915,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1946,7 +1923,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1955,7 +1931,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1964,7 +1939,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1973,7 +1947,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1982,7 +1955,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1991,7 +1963,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2000,7 +1971,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2010,7 +1980,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2a,
             last_state: 0x2a,
         },
@@ -2168,6 +2137,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_3_true_false.txt

@@ -1135,7 +1135,6 @@ Simulation {
         },
         pc: 141,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1259,7 +1258,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1771,7 +1769,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1780,7 +1777,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1793,7 +1789,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1803,7 +1798,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1812,7 +1806,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1825,7 +1818,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1835,7 +1827,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1844,7 +1835,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1854,7 +1844,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -1864,7 +1853,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1873,7 +1861,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1882,7 +1869,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1892,7 +1878,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1902,7 +1887,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1911,7 +1895,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1920,7 +1903,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1930,7 +1912,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1939,7 +1920,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1949,7 +1929,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1959,7 +1938,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1968,7 +1946,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1977,7 +1954,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1986,7 +1962,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1995,7 +1970,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2004,7 +1978,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2013,7 +1986,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2022,7 +1994,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2031,7 +2002,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2041,7 +2011,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -2199,6 +2168,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_3_true_true.txt

@@ -1116,7 +1116,6 @@ Simulation {
         },
         pc: 139,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1238,7 +1237,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1750,7 +1748,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1759,7 +1756,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1772,7 +1768,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1782,7 +1777,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1791,7 +1785,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1804,7 +1797,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1814,7 +1806,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1823,7 +1814,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1833,7 +1823,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -1843,7 +1832,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1852,7 +1840,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1861,7 +1848,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1871,7 +1857,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1881,7 +1866,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1890,7 +1874,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1899,7 +1882,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1909,7 +1891,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1918,7 +1899,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1928,7 +1908,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1938,7 +1917,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x2,
             last_state: 0x2,
         },
@@ -1947,7 +1925,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1956,7 +1933,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1965,7 +1941,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1974,7 +1949,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1983,7 +1957,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1992,7 +1965,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2001,7 +1973,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2010,7 +1981,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2020,7 +1990,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -2178,6 +2147,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_4_false_false.txt

@@ -1104,7 +1104,6 @@ Simulation {
         },
         pc: 135,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1228,7 +1227,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1750,7 +1748,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1759,7 +1756,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1772,7 +1768,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1782,7 +1777,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1791,7 +1785,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1804,7 +1797,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1814,7 +1806,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1823,7 +1814,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1833,7 +1823,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -1843,7 +1832,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1852,7 +1840,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1861,7 +1848,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1871,7 +1857,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1881,7 +1866,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1890,7 +1874,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1899,7 +1882,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1909,7 +1891,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1918,7 +1899,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1928,7 +1908,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1938,7 +1917,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1947,7 +1925,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1956,7 +1933,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1965,7 +1941,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1974,7 +1949,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1983,7 +1957,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1992,7 +1965,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2001,7 +1973,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2010,7 +1981,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2020,7 +1990,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -2030,7 +1999,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(68),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -2188,6 +2156,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_4_false_true.txt

@@ -1085,7 +1085,6 @@ Simulation {
         },
         pc: 133,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1207,7 +1206,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1729,7 +1727,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1738,7 +1735,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1751,7 +1747,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1761,7 +1756,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1770,7 +1764,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1783,7 +1776,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1793,7 +1785,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1802,7 +1793,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1812,7 +1802,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -1822,7 +1811,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1831,7 +1819,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1840,7 +1827,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1850,7 +1836,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1860,7 +1845,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1869,7 +1853,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1878,7 +1861,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1888,7 +1870,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -1897,7 +1878,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1907,7 +1887,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1917,7 +1896,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1926,7 +1904,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1935,7 +1912,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1944,7 +1920,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1953,7 +1928,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1962,7 +1936,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1971,7 +1944,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1980,7 +1952,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1989,7 +1960,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1999,7 +1969,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2b,
             last_state: 0x2b,
         },
@@ -2009,7 +1978,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x3,
             last_state: 0x3,
         },
@@ -2167,6 +2135,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_4_true_false.txt

@@ -1114,7 +1114,6 @@ Simulation {
         },
         pc: 137,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1238,7 +1237,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1760,7 +1758,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1769,7 +1766,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1782,7 +1778,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1792,7 +1787,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2c,
             last_state: 0x2c,
         },
@@ -1801,7 +1795,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1814,7 +1807,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1824,7 +1816,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1833,7 +1824,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1843,7 +1833,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x4,
             last_state: 0x4,
         },
@@ -1853,7 +1842,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1862,7 +1850,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1871,7 +1858,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1881,7 +1867,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1891,7 +1876,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1900,7 +1884,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1909,7 +1892,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1919,7 +1901,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2c,
             last_state: 0x2c,
         },
@@ -1928,7 +1909,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1938,7 +1918,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1948,7 +1927,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1957,7 +1935,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1966,7 +1943,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1975,7 +1951,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1984,7 +1959,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1993,7 +1967,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2002,7 +1975,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2011,7 +1983,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2020,7 +1991,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2030,7 +2000,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2c,
             last_state: 0x2c,
         },
@@ -2040,7 +2009,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(68),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2198,6 +2166,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/queue_4_true_true.txt

@@ -1095,7 +1095,6 @@ Simulation {
         },
         pc: 135,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [
                 MemoryData {
@@ -1217,7 +1216,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1739,7 +1737,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1748,7 +1745,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1761,7 +1757,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1771,7 +1766,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2c,
             last_state: 0x2c,
         },
@@ -1780,7 +1774,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1793,7 +1786,6 @@ Simulation {
                     HdlSome(UInt<8>),
                 },
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1803,7 +1795,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1812,7 +1803,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1822,7 +1812,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<3>,
             },
-            maybe_changed: true,
             state: 0x4,
             last_state: 0x4,
         },
@@ -1832,7 +1821,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1841,7 +1829,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1850,7 +1837,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1860,7 +1846,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(14),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x29,
             last_state: 0x29,
         },
@@ -1870,7 +1855,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(15),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1879,7 +1863,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(16),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1888,7 +1871,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(17),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -1898,7 +1880,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(18),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2c,
             last_state: 0x2c,
         },
@@ -1907,7 +1888,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(19),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1917,7 +1897,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(22),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1927,7 +1906,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(25),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1936,7 +1914,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(27),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1945,7 +1922,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(30),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1954,7 +1930,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1963,7 +1938,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1972,7 +1946,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1981,7 +1954,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1990,7 +1962,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1999,7 +1970,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(39),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -2009,7 +1979,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(42),
                 ty: UInt<8>,
             },
-            maybe_changed: true,
             state: 0x2c,
             last_state: 0x2c,
         },
@@ -2019,7 +1988,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(66),
                 ty: UInt<2>,
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -2177,6 +2145,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/ripple_counter.txt

@@ -636,7 +636,6 @@ Simulation {
         },
         pc: 69,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -688,7 +687,7 @@ Simulation {
                 1,
                 0,
                 0,
-                0 (modified),
+                0,
                 0,
                 0,
                 0,
@@ -699,7 +698,7 @@ Simulation {
                 1,
                 0,
                 0,
-                0 (modified),
+                0,
                 0,
                 0,
                 0,
@@ -710,7 +709,7 @@ Simulation {
                 1,
                 0,
                 0,
-                0 (modified),
+                0,
                 0,
                 0,
             ],
@@ -726,7 +725,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1286,7 +1284,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: false,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1296,7 +1293,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(1),
                 ty: UInt<6>,
             },
-            maybe_changed: false,
             state: 0x00,
             last_state: 0x00,
         },
@@ -1305,7 +1301,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1314,7 +1309,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1323,7 +1317,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(4),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1332,7 +1325,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(5),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1341,7 +1333,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(6),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1350,7 +1341,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1359,7 +1349,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(24),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1368,7 +1357,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(33),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1377,7 +1365,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(34),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1386,7 +1373,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(31),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1395,7 +1381,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(32),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1404,7 +1389,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(36),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1413,7 +1397,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(44),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1422,7 +1405,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(45),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1431,7 +1413,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(42),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1440,7 +1421,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(43),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1449,7 +1429,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(47),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1458,7 +1437,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(55),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1467,7 +1445,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(56),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1476,7 +1453,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(53),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1485,7 +1461,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(54),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1792,6 +1767,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/shift_register.txt

@@ -254,7 +254,6 @@ Simulation {
         },
         pc: 34,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -294,7 +293,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -460,7 +458,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x0,
         },
@@ -469,7 +466,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -478,7 +474,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -487,7 +482,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -496,7 +490,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(4),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -505,7 +498,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -514,7 +506,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(9),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -523,7 +514,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(11),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -547,6 +537,5 @@ Simulation {
     }),
     waiting_sensitivity_sets_by_address: {},
     waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_fork_join.txt

@@ -60,7 +60,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -69,12 +68,12 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
                 0,
                 0,
-                49 (modified),
+                0,
-                50 (modified),
+                49,
-                50 (modified),
+                50,
+                50,
             ],
         },
         sim_only_slots: StatePart {
@@ -88,7 +87,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -358,7 +356,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -367,7 +364,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -376,7 +372,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -386,7 +381,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x31,
             last_state: 0x31,
         },
@@ -396,7 +390,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -406,7 +399,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -523,6 +515,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt

@@ -60,7 +60,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -69,12 +68,12 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
                 0,
                 0,
-                49 (modified),
+                0,
-                50 (modified),
+                49,
-                50 (modified),
+                50,
+                50,
             ],
         },
         sim_only_slots: StatePart {
@@ -88,7 +87,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -358,7 +356,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -367,7 +364,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -376,7 +372,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -386,7 +381,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x31,
             last_state: 0x31,
         },
@@ -396,7 +390,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -406,7 +399,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -523,6 +515,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_only_connects.txt

@@ -375,7 +375,6 @@ Simulation {
         },
         pc: 41,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -393,7 +392,7 @@ Simulation {
                 0,
                 1,
                 0,
-                1 (modified),
+                1,
                 0,
                 0,
                 0,
@@ -401,7 +400,7 @@ Simulation {
                 0,
                 1,
                 0,
-                1 (modified),
+                1,
                 0,
             ],
         },
@@ -476,7 +475,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -1254,7 +1252,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1263,7 +1260,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1273,7 +1269,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(0),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "extra": "value",
             },
@@ -1287,7 +1282,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(1),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "extra": "value",
             },
@@ -1301,7 +1295,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(2),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "",
                 "extra": "value",
@@ -1319,7 +1312,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(3),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "baz",
                 "extra": "value",
@@ -1336,7 +1328,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(4),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1345,7 +1336,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(5),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1355,7 +1345,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(6),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "extra": "value",
             },
@@ -1369,7 +1358,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(7),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "",
                 "extra": "value",
@@ -1386,7 +1374,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1395,7 +1382,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(3),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1405,7 +1391,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(4),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "extra": "value",
             },
@@ -1419,7 +1404,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(5),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "",
                 "extra": "value",
@@ -1437,7 +1421,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(8),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "extra": "value",
             },
@@ -1450,7 +1433,6 @@ Simulation {
             kind: BigBool {
                 index: StatePartIndex<BigSlots>(6),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1459,7 +1441,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(12),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1468,7 +1449,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(13),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1478,7 +1458,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(13),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "",
                 "extra": "value",
@@ -1496,7 +1475,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(14),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "baz",
                 "extra": "value",
@@ -1513,7 +1491,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(10),
             },
-            maybe_changed: true,
             state: 0x1,
             last_state: 0x1,
         },
@@ -1522,7 +1499,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(11),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -1532,7 +1508,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(11),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "",
                 "extra": "value",
@@ -1550,7 +1525,6 @@ Simulation {
                 index: StatePartIndex<SimOnlySlots>(12),
                 ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
             },
-            maybe_changed: true,
             state: {
                 "bar": "baz",
                 "extra": "value",
@@ -1770,6 +1744,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_read_past.txt

@@ -512,7 +512,6 @@ Simulation {
         },
         pc: 57,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -531,18 +530,18 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
                 0,
                 0,
-                49 (modified),
+                0,
-                50 (modified),
+                49,
-                50 (modified),
+                50,
-                0 (modified),
+                50,
-                1 (modified),
+                0,
-                0 (modified),
+                1,
-                49 (modified),
+                0,
-                49 (modified),
+                49,
-                50 (modified),
+                49,
+                50,
                 1,
                 0,
                 0,
@@ -592,7 +591,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -9502,7 +9500,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -9511,7 +9508,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -9520,7 +9516,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(2),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x1,
         },
@@ -9530,7 +9525,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(3),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x31,
             last_state: 0x31,
         },
@@ -9540,7 +9534,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(4),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -9550,7 +9543,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(5),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -9559,7 +9551,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(6),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -9568,7 +9559,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(7),
             },
-            maybe_changed: false,
             state: 0x1,
             last_state: 0x1,
         },
@@ -9577,7 +9567,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(8),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -9587,7 +9576,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(9),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x31,
             last_state: 0x31,
         },
@@ -9597,7 +9585,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(10),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x31,
             last_state: 0x31,
         },
@@ -9607,7 +9594,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(11),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x32,
             last_state: 0x32,
         },
@@ -9728,6 +9714,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt

@@ -48,7 +48,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -57,8 +56,8 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
+                0,
-                0 (modified),
+                0,
                 3,
             ],
         },
@@ -73,7 +72,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -312,7 +310,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -321,7 +318,6 @@ Simulation {
             kind: BigAsyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -331,7 +327,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x03,
             last_state: 0x03,
         },
@@ -541,6 +536,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt

@@ -48,7 +48,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -57,8 +56,8 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
+                0,
-                0 (modified),
+                0,
                 3,
             ],
         },
@@ -73,7 +72,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -312,7 +310,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -321,7 +318,6 @@ Simulation {
             kind: BigAsyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -331,7 +327,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x03,
             last_state: 0x03,
         },
@@ -541,6 +536,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt

@@ -48,7 +48,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -57,7 +56,7 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
+                0,
                 0,
                 3,
             ],
@@ -73,7 +72,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -312,7 +310,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -321,7 +318,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -331,7 +327,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x03,
             last_state: 0x03,
         },
@@ -499,6 +494,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt

@@ -48,7 +48,6 @@ Simulation {
         },
         pc: 0,
         memory_write_log: [],
-        assert_failed_log: [],
         memories: StatePart {
             value: [],
         },
@@ -57,7 +56,7 @@ Simulation {
         },
         big_slots: StatePart {
             value: [
-                0 (modified),
+                0,
                 0,
                 3,
             ],
@@ -73,7 +72,6 @@ Simulation {
             ..
         },
     },
-    global_io: {},
     main_module: SimulationModuleState {
         base_targets: [
             Instance {
@@ -312,7 +310,6 @@ Simulation {
             kind: BigClock {
                 index: StatePartIndex<BigSlots>(0),
             },
-            maybe_changed: true,
             state: 0x0,
             last_state: 0x0,
         },
@@ -321,7 +318,6 @@ Simulation {
             kind: BigSyncReset {
                 index: StatePartIndex<BigSlots>(1),
             },
-            maybe_changed: false,
             state: 0x0,
             last_state: 0x0,
         },
@@ -331,7 +327,6 @@ Simulation {
                 index: StatePartIndex<BigSlots>(2),
                 ty: UInt<8>,
             },
-            maybe_changed: false,
             state: 0x03,
             last_state: 0x03,
         },
@@ -499,6 +494,5 @@ Simulation {
             },
         ),
     },
-    asserts: [],
     ..
 }

crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd

@@ -1,221 +0,0 @@
-$timescale 1 ps $end
-$scope module sim_trace_as_string $end
-$var wire 1 J(7*b clk $end
-$scope struct read $end
-$var wire 8 @t0}\ addr $end
-$var wire 1 78"T5 en $end
-$var wire 1 G7v@m clk $end
-$var string 1 F&^FN data $end
-$upscope $end
-$scope struct write $end
-$var wire 8 "fUdW addr $end
-$var wire 1 r1OK) en $end
-$var wire 1 ,ADvU clk $end
-$scope struct data $end
-$var string 1 pD.mP \[0] $end
-$var string 1 !V!em \[1] $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 l8dgD \[0] $end
-$var wire 1 1/sDs \[1] $end
-$upscope $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct \[0] $end
-$scope struct mem $end
-$var string 1 sz>#| \[0] $end
-$var string 1 G._83 \[1] $end
-$upscope $end
-$upscope $end
-$scope struct \[1] $end
-$scope struct mem $end
-$var string 1 2r3#W \[0] $end
-$var string 1 AbGF% \[1] $end
-$upscope $end
-$upscope $end
-$scope struct \[2] $end
-$scope struct mem $end
-$var string 1 .^<$p \[0] $end
-$var string 1 ?s@Dc \[1] $end
-$upscope $end
-$upscope $end
-$scope struct \[3] $end
-$scope struct mem $end
-$var string 1 {*||o \[0] $end
-$var string 1 Bg,vB \[1] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r0 $end
-$var wire 2 .0()- addr $end
-$var wire 1 GEbRA en $end
-$var wire 1 ;`9BK clk $end
-$scope struct data $end
-$var string 1 _Xe"P \[0] $end
-$var string 1 jXrsx \[1] $end
-$upscope $end
-$upscope $end
-$scope struct w1 $end
-$var wire 2 '8u?z addr $end
-$var wire 1 ~o=`& en $end
-$var wire 1 *q>M1 clk $end
-$scope struct data $end
-$var string 1 N\zBe \[0] $end
-$var string 1 c3h8{ \[1] $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 .SYGD \[0] $end
-$var wire 1 />wYd \[1] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-s sz>#|
-s G._83
-s 2r3#W
-s AbGF%
-s .^<$p
-s ?s@Dc
-s {*||o
-s Bg,vB
-0J(7*b
-b0 @t0}\
-078"T5
-0G7v@m
-s[,\x20] F&^FN
-b0 "fUdW
-0r1OK)
-0,ADvU
-s pD.mP
-s !V!em
-0l8dgD
-01/sDs
-b0 .0()-
-0GEbRA
-0;`9BK
-s _Xe"P
-s jXrsx
-b0 '8u?z
-0~o=`&
-0*q>M1
-s N\zBe
-s c3h8{
-0.SYGD
-0/>wYd
-$end
-#500000
-1J(7*b
-1;`9BK
-1*q>M1
-#1000000
-0J(7*b
-1r1OK)
-smem[0][0] pD.mP
-smem[0][1] !V!em
-1l8dgD
-11/sDs
-0;`9BK
-1~o=`&
-0*q>M1
-smem[0][0] N\zBe
-smem[0][1] c3h8{
-1.SYGD
-1/>wYd
-#1500000
-smem[0][0] sz>#|
-smem[0][1] G._83
-1J(7*b
-1;`9BK
-1*q>M1
-#2000000
-0J(7*b
-b1 "fUdW
-smem[1][0] pD.mP
-smem[1][1] !V!em
-0;`9BK
-b1 '8u?z
-0*q>M1
-smem[1][0] N\zBe
-smem[1][1] c3h8{
-#2500000
-smem[1][0] 2r3#W
-smem[1][1] AbGF%
-1J(7*b
-1;`9BK
-1*q>M1
-#3000000
-0J(7*b
-b10 "fUdW
-smem[2][0] pD.mP
-smem[2][1] !V!em
-0;`9BK
-b10 '8u?z
-0*q>M1
-smem[2][0] N\zBe
-smem[2][1] c3h8{
-#3500000
-smem[2][0] .^<$p
-smem[2][1] ?s@Dc
-1J(7*b
-1;`9BK
-1*q>M1
-#4000000
-0J(7*b
-b11 "fUdW
-smem[3][0] pD.mP
-smem[3][1] !V!em
-0;`9BK
-b11 '8u?z
-0*q>M1
-smem[3][0] N\zBe
-smem[3][1] c3h8{
-#4500000
-smem[3][0] {*||o
-smem[3][1] Bg,vB
-1J(7*b
-1;`9BK
-1*q>M1
-#5000000
-0J(7*b
-b1 @t0}\
-178"T5
-s[mem[1][0],\x20mem[1][1]] F&^FN
-b0 "fUdW
-0r1OK)
-s<!!!failed\x20to\x20format!!!> pD.mP
-s<!!!failed\x20to\x20format!!!> !V!em
-b1 .0()-
-1GEbRA
-0;`9BK
-smem[1][0] _Xe"P
-smem[1][1] jXrsx
-b0 '8u?z
-0~o=`&
-0*q>M1
-s<!!!failed\x20to\x20format!!!> N\zBe
-s<!!!failed\x20to\x20format!!!> c3h8{
-#5500000
-1J(7*b
-1;`9BK
-1*q>M1
-#6000000
-0J(7*b
-b1 "fUdW
-1r1OK)
-0;`9BK
-b1 '8u?z
-1~o=`&
-0*q>M1
-#6500000
-s<!!!failed\x20to\x20format!!!> 2r3#W
-s<!!!failed\x20to\x20format!!!> AbGF%
-1J(7*b
-s<!!!failed\x20to\x20format!!!> F&^FN
-1;`9BK
-s<!!!failed\x20to\x20format!!!> _Xe"P
-s<!!!failed\x20to\x20format!!!> jXrsx
-1*q>M1
-#7000000

crates/fayalite/tests/sim/expected/test_formal_counter.txt

@@ -1,855 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 5,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 26,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::enable_assert",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::any_seq_out",
-                                ty: UInt<16>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.rst",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: ".clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: ".rst",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: "<<Global>>::formal_global_clock",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "<<Global>>::formal_reset",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<9>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "<<Global>>::any_seq",
-                                ty: UInt<16>,
-                            },
-                        ],
-                        ..
-                    },
-                    sim_only_slots: StatePartLayout<SimOnlySlots> {
-                        len: 0,
-                        debug_data: [],
-                        layout_data: [],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 0,
-                    debug_data: [],
-                    layout_data: [],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:15:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x4d2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::any_seq_out", ty: UInt<16> },
-                    src: StatePartIndex<BigSlots>(25), // (0x4d2) SlotDebugData { name: "<<Global>>::any_seq", ty: UInt<16> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "<<Global>>::formal_reset", ty: SyncReset },
-                },
-                2: NotU {
-                    dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    width: 1,
-                },
-                3: Const {
-                    dest: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    value: 0x1,
-                },
-                4: And {
-                    dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                5: NotU {
-                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    width: 1,
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                6: Copy {
-                    dest: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                7: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                8: Const {
-                    dest: StatePartIndex<BigSlots>(14), // (0xa) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0xa,
-                },
-                9: CmpLe {
-                    dest: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> },
-                    rhs: StatePartIndex<BigSlots>(14), // (0xa) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                10: Or {
-                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                11: BranchIfZero {
-                    target: 13,
-                    value: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::enable_assert", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                13: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                14: Const {
-                    dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x1,
-                },
-                15: Add {
-                    dest: StatePartIndex<BigSlots>(13), // (0x3) SlotDebugData { name: "", ty: UInt<9> },
-                    lhs: StatePartIndex<BigSlots>(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> },
-                    rhs: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                16: CmpLt {
-                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(13), // (0x3) SlotDebugData { name: "", ty: UInt<9> },
-                    rhs: StatePartIndex<BigSlots>(14), // (0xa) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                17: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(13), // (0x3) SlotDebugData { name: "", ty: UInt<9> },
-                    dest_width: 8,
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                19: BranchIfZero {
-                    target: 21,
-                    value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                20: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(16), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                21: Const {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x0,
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                22: BranchIfNonZero {
-                    target: 24,
-                    value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:7:1
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                24: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "<<Global>>::formal_global_clock", ty: Clock },
-                },
-                25: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
-                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "<<Global>>::formal_reset", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                26: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(5), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
-                },
-                27: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.rst", ty: SyncReset },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                28: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.clk", ty: Clock },
-                },
-                29: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                30: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.rst", ty: SyncReset },
-                },
-                31: BranchIfSmallZero {
-                    target: 36,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                32: BranchIfSmallNonZero {
-                    target: 35,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                33: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> },
-                },
-                34: Branch {
-                    target: 36,
-                },
-                35: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                36: Assert {
-                    clk_triggered: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    pred: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    assert_index: 0,
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                37: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                38: Return,
-            ],
-            ..
-        },
-        pc: 38,
-        memory_write_log: [],
-        assert_failed_log: [],
-        memories: StatePart {
-            value: [],
-        },
-        small_slots: StatePart {
-            value: [
-                0,
-                0,
-                1,
-                0,
-                1,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                2,
-                1,
-                1234,
-                1,
-                0,
-                1,
-                0,
-                1,
-                0,
-                2,
-                3,
-                0,
-                1,
-                3,
-                10,
-                1,
-                3,
-                1,
-                1,
-                0,
-                1,
-                1,
-                0,
-                1,
-                1,
-                1234,
-            ],
-        },
-        sim_only_slots: StatePart {
-            value: [],
-        },
-    },
-    io: Instance {
-        name: <simulator>::formal_counter,
-        instantiated: Module {
-            name: formal_counter,
-            ..
-        },
-    },
-    global_io: {
-        SimIoForGlobal(
-            formal_global_clock,
-        ): CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "<<Global>>::formal_global_clock",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                    sim_only_slots: StatePartLayout<SimOnlySlots> {
-                        len: 0,
-                        debug_data: [],
-                        layout_data: [],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
-                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-            },
-            write: None,
-        },
-        SimIoForGlobal(
-            formal_reset,
-        ): CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "<<Global>>::formal_reset",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                    sim_only_slots: StatePartLayout<SimOnlySlots> {
-                        len: 0,
-                        debug_data: [],
-                        layout_data: [],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
-                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-            },
-            write: None,
-        },
-        SimIoForGlobal(
-            any_seq(
-                UInt<16>,
-            ),
-        ): CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<16>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "<<Global>>::any_seq",
-                                ty: UInt<16>,
-                            },
-                        ],
-                        ..
-                    },
-                    sim_only_slots: StatePartLayout<SimOnlySlots> {
-                        len: 0,
-                        debug_data: [],
-                        layout_data: [],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 5, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 25, len: 1 },
-                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-            },
-            write: None,
-        },
-    },
-    main_module: SimulationModuleState {
-        base_targets: [
-            SimIoForGlobal(
-                formal_global_clock,
-            ),
-            SimIoForGlobal(
-                formal_reset,
-            ),
-            SimIoForGlobal(
-                any_seq(
-                    UInt<16>,
-                ),
-            ),
-            Instance {
-                name: <simulator>::formal_counter,
-                instantiated: Module {
-                    name: formal_counter,
-                    ..
-                },
-            }.count,
-            Instance {
-                name: <simulator>::formal_counter,
-                instantiated: Module {
-                    name: formal_counter,
-                    ..
-                },
-            }.enable_assert,
-            Instance {
-                name: <simulator>::formal_counter,
-                instantiated: Module {
-                    name: formal_counter,
-                    ..
-                },
-            }.any_seq_out,
-        ],
-        uninitialized_ios: {},
-        io_targets: {
-            Instance {
-                name: <simulator>::formal_counter,
-                instantiated: Module {
-                    name: formal_counter,
-                    ..
-                },
-            }.any_seq_out,
-            Instance {
-                name: <simulator>::formal_counter,
-                instantiated: Module {
-                    name: formal_counter,
-                    ..
-                },
-            }.count,
-            Instance {
-                name: <simulator>::formal_counter,
-                instantiated: Module {
-                    name: formal_counter,
-                    ..
-                },
-            }.enable_assert,
-            SimIoForGlobal(
-                any_seq(
-                    UInt<16>,
-                ),
-            ),
-            SimIoForGlobal(
-                formal_global_clock,
-            ),
-            SimIoForGlobal(
-                formal_reset,
-            ),
-        },
-        did_initial_settle: true,
-        clocks_for_past: {},
-    },
-    extern_modules: [],
-    trace_decls: TraceModule {
-        name: "formal_counter",
-        children: [
-            TraceFormalInput {
-                name: "formal_global_clock",
-                child: TraceClock {
-                    location: TraceScalarId(5),
-                    name: "formal_global_clock",
-                    flow: Source,
-                },
-                formal_input: formal_global_clock,
-            },
-            TraceFormalInput {
-                name: "formal_reset",
-                child: TraceSyncReset {
-                    location: TraceScalarId(6),
-                    name: "formal_reset",
-                    flow: Source,
-                },
-                formal_input: formal_reset,
-            },
-            TraceFormalInput {
-                name: "any_seq",
-                child: TraceUInt {
-                    location: TraceScalarId(8),
-                    name: "any_seq",
-                    ty: UInt<16>,
-                    flow: Source,
-                },
-                formal_input: any_seq(
-                    UInt<16>,
-                ),
-            },
-            TraceModuleIO {
-                name: "count",
-                child: TraceUInt {
-                    location: TraceScalarId(0),
-                    name: "count",
-                    ty: UInt<8>,
-                    flow: Sink,
-                },
-                ty: UInt<8>,
-                flow: Sink,
-            },
-            TraceModuleIO {
-                name: "enable_assert",
-                child: TraceBool {
-                    location: TraceScalarId(1),
-                    name: "enable_assert",
-                    flow: Source,
-                },
-                ty: Bool,
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "any_seq_out",
-                child: TraceUInt {
-                    location: TraceScalarId(2),
-                    name: "any_seq_out",
-                    ty: UInt<16>,
-                    flow: Sink,
-                },
-                ty: UInt<16>,
-                flow: Sink,
-            },
-            TraceWire {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            location: TraceScalarId(3),
-                            name: "clk",
-                            flow: Duplex,
-                        },
-                        TraceSyncReset {
-                            location: TraceScalarId(4),
-                            name: "rst",
-                            flow: Duplex,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: SyncReset,
-                    },
-                    flow: Duplex,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-            },
-            TraceReg {
-                name: "count_reg",
-                child: TraceUInt {
-                    location: TraceScalarId(7),
-                    name: "count_reg",
-                    ty: UInt<8>,
-                    flow: Duplex,
-                },
-                ty: UInt<8>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0x02,
-            last_state: 0x01,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            maybe_changed: false,
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: UInt<16>,
-            },
-            maybe_changed: true,
-            state: 0x04d2,
-            last_state: 0x04d2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(3),
-            },
-            maybe_changed: true,
-            state: 0x1,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigSyncReset {
-                index: StatePartIndex<BigSlots>(4),
-            },
-            maybe_changed: true,
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(7),
-            },
-            maybe_changed: true,
-            state: 0x1,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigSyncReset {
-                index: StatePartIndex<BigSlots>(8),
-            },
-            maybe_changed: true,
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(9),
-                ty: UInt<8>,
-            },
-            maybe_changed: true,
-            state: 0x02,
-            last_state: 0x01,
-        },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(25),
-                ty: UInt<16>,
-            },
-            maybe_changed: true,
-            state: 0x04d2,
-            last_state: 0x04d2,
-        },
-    ],
-    trace_memories: {},
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-    event_queue: EventQueue(EventQueueData {
-        instant: 66 μs,
-        events: {},
-    }),
-    waiting_sensitivity_sets_by_address: {},
-    waiting_sensitivity_sets_by_compiled_value: {},
-    asserts: [
-        CompiledAssert {
-            instantiated_module: InstantiatedModule(formal_counter: formal_counter),
-            stmt_formal: assert {
-                clk: Wire(formal_counter::cd: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                }).clk,
-                pred: CmpLeU {
-                    lhs: Reg {
-                        name: formal_counter::count_reg,
-                        ty: UInt<8>,
-                        clock_domain: Wire(formal_counter::cd: Bundle {
-                            /* offset = 0 */
-                            clk: Clock,
-                            /* offset = 1 */
-                            rst: SyncReset,
-                        }),
-                        init: Some(
-                            0x0_u8,
-                        ),
-                        ..
-                    },
-                    rhs: 0xA_u8,
-                    literal_bits: Err(
-                        NotALiteralExpr,
-                    ),
-                },
-                en: BitAndB {
-                    lhs: true,
-                    rhs: NotB {
-                        arg: CastSyncResetToBool {
-                            arg: formal_reset,
-                            literal_bits: Err(
-                                NotALiteralExpr,
-                            ),
-                        },
-                        literal_bits: Err(
-                            NotALiteralExpr,
-                        ),
-                    },
-                    literal_bits: Err(
-                        NotALiteralExpr,
-                    ),
-                },
-                text: "",
-                ..
-            },
-        },
-    ],
-    ..
-}