diff --git a/crates/fayalite-proc-macros-impl/src/fold.rs b/crates/fayalite-proc-macros-impl/src/fold.rs index 50423b5..22e7b82 100644 --- a/crates/fayalite-proc-macros-impl/src/fold.rs +++ b/crates/fayalite-proc-macros-impl/src/fold.rs @@ -257,6 +257,5 @@ no_op_fold!(syn::Token![let]); no_op_fold!(syn::Token![mut]); no_op_fold!(syn::Token![static]); no_op_fold!(syn::Token![struct]); -no_op_fold!(syn::Token![type]); no_op_fold!(syn::Token![where]); no_op_fold!(usize); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index f7ad68d..97fa3ff 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -3,9 +3,8 @@ use crate::{ Errors, HdlAttr, PairsIterExt, hdl_type_common::{ - CustomDebugOptions, CustomDebugTrait, ItemOptions, MakeHdlTypeExpr, MaybeParsed, - ParsedField, ParsedFieldsNamed, ParsedGenerics, SplitForImpl, TypesParser, WrappedInConst, - common_derives, create_struct_debug_impl, get_target, + ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedField, ParsedFieldsNamed, ParsedGenerics, + SplitForImpl, TypesParser, WrappedInConst, common_derives, get_target, }, kw, }; @@ -31,7 +30,6 @@ pub(crate) struct ParsedBundle { pub(crate) fields: MaybeParsed, pub(crate) field_flips: Vec>>, pub(crate) mask_type_ident: Ident, - pub(crate) mask_type_name: String, pub(crate) mask_type_match_variant_ident: Ident, pub(crate) mask_type_sim_value_ident: Ident, pub(crate) match_variant_ident: Ident, @@ -90,8 +88,6 @@ impl ParsedBundle { no_runtime_generics: _, cmp_eq: _, ref get, - custom_debug: _, - custom_sim_display: _, } = options.body; if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on structs"); @@ -135,7 +131,6 @@ impl ParsedBundle { fields, field_flips, mask_type_ident: format_ident!("__{}__MaskType", ident), - mask_type_name: format!("MaskType<{}>", ident), mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident), mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident), match_variant_ident: format_ident!("__{}__MatchVariant", ident), @@ -453,7 +448,6 @@ impl ToTokens for ParsedBundle { fields, field_flips, mask_type_ident, - mask_type_name, mask_type_match_variant_ident, mask_type_sim_value_ident, match_variant_ident, @@ -470,20 +464,11 @@ impl ToTokens for ParsedBundle { no_runtime_generics, cmp_eq, get: _, - custom_debug: _, - custom_sim_display, } = &options.body; - let CustomDebugOptions { - type_: custom_debug_type, - sim: custom_debug_sim, - mask_type: custom_debug_mask_type, - mask_sim: custom_debug_mask_sim, - } = options.body.custom_debug(); let target = get_target(target, ident); - let struct_name = ident.to_string(); let mut item_attrs = attrs.clone(); - item_attrs.push(common_derives(span, false)); - let type_struct = ItemStruct { + item_attrs.push(common_derives(span)); + ItemStruct { attrs: item_attrs, vis: vis.clone(), struct_token: *struct_token, @@ -491,8 +476,8 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(fields.clone().into()), semi_token: None, - }; - type_struct.to_tokens(tokens); + } + .to_tokens(tokens); let (impl_generics, type_generics, where_clause) = generics.split_for_impl(); if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(fields), None) = (generics, fields, no_runtime_generics) @@ -518,9 +503,6 @@ impl ToTokens for ParsedBundle { } let mut wrapped_in_const = WrappedInConst::new(tokens, span); let tokens = wrapped_in_const.inner(); - if custom_debug_type.is_none() { - create_struct_debug_impl(&type_struct, &struct_name, None).to_tokens(tokens); - } let builder = Builder { vis: vis.clone(), struct_token: *struct_token, @@ -548,9 +530,9 @@ impl ToTokens for ParsedBundle { mask_type_builder.to_tokens(tokens); let unfilled_mask_type_builder_ty = mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); - let mask_type_struct = ItemStruct { + ItemStruct { attrs: vec![ - common_derives(span, false), + common_derives(span), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -561,20 +543,17 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_fields.clone()), semi_token: None, - }; - mask_type_struct.to_tokens(tokens); - if custom_debug_mask_type.is_none() { - create_struct_debug_impl(&mask_type_struct, mask_type_name, None).to_tokens(tokens); } + .to_tokens(tokens); let mut mask_type_match_variant_fields = mask_type_fields.clone(); for Field { ty, .. } in &mut mask_type_match_variant_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::expr::Expr<#ty> }; } - let mask_type_match_variant_struct = ItemStruct { + ItemStruct { attrs: vec![ - common_derives(span, false), + common_derives(span), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -585,19 +564,17 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_match_variant_fields), semi_token: None, - }; - mask_type_match_variant_struct.to_tokens(tokens); - create_struct_debug_impl(&mask_type_match_variant_struct, mask_type_name, None) - .to_tokens(tokens); + } + .to_tokens(tokens); let mut match_variant_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut match_variant_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::expr::Expr<#ty> }; } - let match_variant_struct = ItemStruct { + ItemStruct { attrs: vec![ - common_derives(span, false), + common_derives(span), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -608,19 +585,19 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(match_variant_fields), semi_token: None, - }; - match_variant_struct.to_tokens(tokens); - create_struct_debug_impl(&match_variant_struct, &struct_name, None).to_tokens(tokens); + } + .to_tokens(tokens); let mut mask_type_sim_value_fields = mask_type_fields; for Field { ty, .. } in &mut mask_type_sim_value_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::sim::value::SimValue<#ty> }; } - let mask_type_sim_value_struct = ItemStruct { + ItemStruct { attrs: vec![ parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( + ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }, @@ -634,34 +611,19 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_sim_value_fields), semi_token: None, - }; - mask_type_sim_value_struct.to_tokens(tokens); - if custom_debug_mask_sim.is_none() { - create_struct_debug_impl( - &mask_type_struct, - mask_type_name, - Some(CustomDebugTrait { - trait_path: &parse_quote_spanned! {span=> - ::fayalite::ty::SimValueDebug - }, - fn_name: &format_ident!("sim_value_debug", span = span), - this_arg: &parse_quote_spanned! {span=> - value: &::SimValue - }, - }), - ) - .to_tokens(tokens); } + .to_tokens(tokens); let mut sim_value_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut sim_value_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::sim::value::SimValue<#ty> }; } - let sim_value_struct = ItemStruct { + ItemStruct { attrs: vec![ parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( + ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }, @@ -675,36 +637,8 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(sim_value_fields), semi_token: None, - }; - sim_value_struct.to_tokens(tokens); - if custom_debug_sim.is_none() { - create_struct_debug_impl( - &type_struct, - &struct_name, - Some(CustomDebugTrait { - trait_path: &parse_quote_spanned! {span=> - ::fayalite::ty::SimValueDebug - }, - fn_name: &format_ident!("sim_value_debug", span = span), - this_arg: &parse_quote_spanned! {span=> - value: &::SimValue - }, - }), - ) - .to_tokens(tokens); - } - if custom_sim_display.is_some() { - quote_spanned! {span=> - #[automatically_derived] - impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics - #where_clause - { - fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f) - } - } - }.to_tokens(tokens); } + .to_tokens(tokens); let this_token = Ident::new("__this", span); let fields_token = Ident::new("__fields", span); let self_token = Token![self](span); @@ -886,14 +820,6 @@ impl ToTokens for ParsedBundle { } } #[automatically_derived] - impl #impl_generics ::fayalite::__std::fmt::Debug for #mask_type_sim_value_ident #type_generics - #where_clause - { - fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - <#mask_type_ident #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) - } - } - #[automatically_derived] impl #impl_generics ::fayalite::expr::ValueType for #mask_type_sim_value_ident #type_generics #where_clause { @@ -1054,14 +980,6 @@ impl ToTokens for ParsedBundle { } } #[automatically_derived] - impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics - #where_clause - { - fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) - } - } - #[automatically_derived] impl #impl_generics ::fayalite::expr::ValueType for #sim_value_ident #type_generics #where_clause { @@ -1223,7 +1141,7 @@ impl ToTokens for ParsedBundle { valueless_eq_body = quote_spanned! {span=> let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); let __rhs = ::fayalite::expr::ValueType::ty(&__rhs); - #(#fields_valueless_eq)&* + #(#fields_valueless_eq)|* }; valueless_ne_body = quote_spanned! {span=> let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs index e9f013b..ae0f8f4 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs @@ -3,9 +3,8 @@ use crate::{ Errors, HdlAttr, PairsIterExt, hdl_type_common::{ - CustomDebugOptions, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, - SplitForImpl, TypesParser, WrappedInConst, common_derives, create_struct_debug_impl, - get_target, + ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, SplitForImpl, + TypesParser, WrappedInConst, common_derives, get_target, }, kw, }; @@ -159,32 +158,15 @@ impl ParsedEnum { custom_bounds, no_static: _, no_runtime_generics: _, - cmp_eq: _, + cmp_eq, ref get, - custom_debug: _, - custom_sim_display: _, } = options.body; + if let Some((cmp_eq,)) = cmp_eq { + errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums"); + } if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on enums"); } - let CustomDebugOptions { - type_: _, - sim: _, - mask_type, - mask_sim, - } = options.body.custom_debug(); - if let Some((mask_type,)) = mask_type { - errors.error( - mask_type, - "#[hdl(custom_debug(mask_type)] is not allowed on enums", - ); - } - if let Some((mask_sim,)) = mask_sim { - errors.error( - mask_sim, - "#[hdl(custom_debug(mask_sim)] is not allowed on enums", - ); - } attrs.retain(|attr| { if attr.path().is_ident("repr") { errors.error(attr, "#[repr] is not supported on #[hdl] enums"); @@ -246,21 +228,12 @@ impl ToTokens for ParsedEnum { custom_bounds: _, no_static, no_runtime_generics, - cmp_eq, + cmp_eq: _, // TODO: implement cmp_eq for enums get: _, - custom_debug: _, - custom_sim_display, } = &options.body; - let CustomDebugOptions { - type_: custom_debug_type, - sim: custom_debug_sim, - mask_type: _, - mask_sim: _, - } = options.body.custom_debug(); let target = get_target(target, ident); - let enum_name = ident.to_string(); let mut struct_attrs = attrs.clone(); - struct_attrs.push(common_derives(span, false)); + struct_attrs.push(common_derives(span)); struct_attrs.push(parse_quote_spanned! {span=> #[allow(non_snake_case)] }); @@ -300,7 +273,7 @@ impl ToTokens for ParsedEnum { } }, )); - let type_struct = ItemStruct { + ItemStruct { attrs: struct_attrs, vis: vis.clone(), struct_token: Token![struct](enum_token.span), @@ -315,8 +288,8 @@ impl ToTokens for ParsedEnum { }) }, semi_token: None, - }; - type_struct.to_tokens(tokens); + } + .to_tokens(tokens); let (impl_generics, type_generics, where_clause) = generics.split_for_impl(); if let (MaybeParsed::Parsed(generics), None) = (generics, no_runtime_generics) { generics.make_runtime_generics(tokens, vis, ident, &target, |context| { @@ -400,9 +373,6 @@ impl ToTokens for ParsedEnum { } .to_tokens(tokens); } - if custom_debug_type.is_none() { - create_struct_debug_impl(&type_struct, &enum_name, None).to_tokens(tokens); - } let mut enum_attrs = attrs.clone(); enum_attrs.push(parse_quote_spanned! {span=> #[allow(dead_code, non_camel_case_types)] @@ -483,6 +453,7 @@ impl ToTokens for ParsedEnum { let mut enum_attrs = attrs.clone(); enum_attrs.push(parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( + ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }); @@ -867,240 +838,6 @@ impl ToTokens for ParsedEnum { }, )), ); - if custom_debug_sim.is_none() { - let debug_match_arms = Vec::from_iter( - variants - .iter() - .map( - |ParsedVariant { - attrs: _, - options: _, - ident, - field, - }| { - let variant_name = ident.to_string(); - if let Some(_) = field { - quote_spanned! {span=> - #sim_value_ident::#ident(field, _) => { - f.debug_tuple(#variant_name).field(field).finish() - } - } - } else { - quote_spanned! {span=> - #sim_value_ident::#ident(_) => { - f.write_str(#variant_name) - } - } - } - }, - ) - .chain(sim_value_unknown_variant_name.as_ref().map( - |sim_value_unknown_variant_name| { - let sim_value_unknown_variant_name_str = - sim_value_unknown_variant_name.to_string(); - quote_spanned! {span=> - #sim_value_ident::#sim_value_unknown_variant_name(_) => { - f.write_str(#sim_value_unknown_variant_name_str) - } - } - }, - )), - ); - quote_spanned! {span=> - #[automatically_derived] - impl #impl_generics ::fayalite::ty::SimValueDebug for #target #type_generics - #where_clause - { - fn sim_value_debug( - value: &::SimValue, - f: &mut ::fayalite::__std::fmt::Formatter<'_>, - ) -> ::fayalite::__std::fmt::Result { - match value { - #(#debug_match_arms)* - } - } - } - } - .to_tokens(tokens); - } - if custom_sim_display.is_some() { - quote_spanned! {span=> - #[automatically_derived] - impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics - #where_clause - { - fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f) - } - } - }.to_tokens(tokens); - } - if let Some((cmp_eq,)) = cmp_eq { - let mut cmp_eq_where_clause = - Generics::from(generics) - .where_clause - .unwrap_or_else(|| syn::WhereClause { - where_token: Token![where](span), - predicates: Punctuated::new(), - }); - let mut variants_value_eq = vec![]; - let mut variants_expr_eq = vec![]; - let mut fields_valueless_eq = vec![]; - for ( - variant_index, - ParsedVariant { - attrs: _, - options: variant_options, - ident: variant_ident, - field, - }, - ) in variants.iter().enumerate() - { - let VariantOptions {} = variant_options.body; - if let Some(ParsedVariantField { - paren_token: _, - attrs: _, - options: field_options, - ty: field_ty, - comma_token: _, - }) = field - { - let FieldOptions {} = field_options.body; - cmp_eq_where_clause - .predicates - .push(parse_quote_spanned! {cmp_eq.span=> - #field_ty: ::fayalite::expr::HdlPartialEqImpl<#field_ty> - }); - variants_value_eq.push(quote_spanned! {span=> - (#sim_value_ident::#variant_ident(__lhs_field, _), #sim_value_ident::#variant_ident(__rhs_field, _)) => { - ::fayalite::expr::HdlPartialEqImpl::cmp_value_eq( - __lhs.#variant_ident, - ::fayalite::__std::borrow::Cow::Borrowed(__lhs_field), - __rhs.#variant_ident, - ::fayalite::__std::borrow::Cow::Borrowed(__rhs_field), - ) - } - }); - variants_expr_eq.push(quote_spanned! {span=> - { - let (#match_variant_ident::#variant_ident(__lhs), __scope) = - ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( - ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter) - .expect("known to have enough variants"), - ) - else { - ::fayalite::__std::unreachable!(); - }; - let (#match_variant_ident::#variant_ident(__rhs), __scope) = - ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( - ::fayalite::__std::iter::Iterator::nth( - &mut ::fayalite::module::match_(__rhs), - #variant_index, - ) - .expect("known to have variant"), - ) - else { - ::fayalite::__std::unreachable!(); - }; - ::fayalite::module::connect(__retval, ::fayalite::expr::HdlPartialEqImpl::cmp_expr_eq(__lhs, __rhs)); - } - }); - fields_valueless_eq.push(quote_spanned! {span=> - ::fayalite::expr::HdlPartialEqImpl::cmp_valueless_eq( - ::fayalite::expr::Valueless::new(__lhs.#variant_ident), - ::fayalite::expr::Valueless::new(__rhs.#variant_ident), - ) - }); - } else { - variants_value_eq.push(quote_spanned! {span=> - (#sim_value_ident::#variant_ident(_), #sim_value_ident::#variant_ident(_)) => true, - }); - variants_expr_eq.push(quote_spanned! {span=> - { - let (#match_variant_ident::#variant_ident, __scope) = - ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( - ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter) - .expect("known to have enough variants"), - ) - else { - ::fayalite::__std::unreachable!(); - }; - let (#match_variant_ident::#variant_ident, __scope) = - ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( - ::fayalite::__std::iter::Iterator::nth( - &mut ::fayalite::module::match_(__rhs), - #variant_index, - ) - .expect("known to have variant"), - ) - else { - ::fayalite::__std::unreachable!(); - }; - ::fayalite::module::connect(__retval, true); - } - }); - } - } - if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name { - variants_value_eq.push(quote_spanned! {span=> - (#sim_value_ident::#sim_value_unknown_variant_name(__lhs_unknown), #sim_value_ident::#sim_value_unknown_variant_name(__rhs_unknown)) => { - __lhs_unknown == __rhs_unknown - } - }); - } - let valueless_eq_body = if fields_valueless_eq.is_empty() { - quote_spanned! {span=> - ::fayalite::expr::Valueless::new(::fayalite::int::Bool) - } - } else { - quote_spanned! {span=> - let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); - let __rhs = ::fayalite::expr::ValueType::ty(&__rhs); - #(#fields_valueless_eq)&* - } - }; - let cmp_expr_eq_wire_name = format!("{ident}_cmp_eq"); - quote_spanned! {span=> - #[automatically_derived] - impl #impl_generics ::fayalite::expr::HdlPartialEqImpl for #target #type_generics - #cmp_eq_where_clause - { - #[track_caller] - fn cmp_value_eq( - __lhs: Self, - __lhs_value: ::fayalite::__std::borrow::Cow<'_, ::SimValue>, - __rhs: Self, - __rhs_value: ::fayalite::__std::borrow::Cow<'_, ::SimValue>, - ) -> ::fayalite::__std::primitive::bool { - match (&*__lhs_value, &*__rhs_value) { - #(#variants_value_eq)* - _ => false, - } - } - - #[track_caller] - fn cmp_expr_eq( - __lhs: ::fayalite::expr::Expr, - __rhs: ::fayalite::expr::Expr, - ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> { - let __retval = ::fayalite::module::wire(::fayalite::module::ImplicitName(#cmp_expr_eq_wire_name), ::fayalite::int::Bool); - ::fayalite::module::connect(__retval, false); - let mut __lhs_match_variant_iter = ::fayalite::module::match_(__lhs); - #(#variants_expr_eq)* - __retval - } - - #[track_caller] - fn cmp_valueless_eq( - __lhs: ::fayalite::expr::Valueless, - __rhs: ::fayalite::expr::Valueless, - ) -> ::fayalite::expr::Valueless<::fayalite::int::Bool> { - #valueless_eq_body - } - } - } - .to_tokens(tokens); - } let variants_len = variants.len(); quote_spanned! {span=> #[automatically_derived] @@ -1197,14 +934,6 @@ impl ToTokens for ParsedEnum { } } #[automatically_derived] - impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics - #where_clause - { - fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) - } - } - #[automatically_derived] impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics> for #sim_value_ident #type_generics #where_clause diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs index 556c15b..0fa2222 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs @@ -215,8 +215,6 @@ impl ParsedTypeAlias { no_runtime_generics, cmp_eq, get: _, - ref custom_debug, - custom_sim_display, } = options.body; if let Some((no_static,)) = no_static { errors.error(no_static, "no_static is not valid on type aliases"); @@ -236,15 +234,6 @@ impl ParsedTypeAlias { if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); } - if let Some((custom_debug, _, _)) = custom_debug { - errors.error(custom_debug, "custom_debug is not valid on type aliases"); - } - if let Some((custom_sim_display,)) = custom_sim_display { - errors.error( - custom_sim_display, - "custom_sim_display is not valid on type aliases", - ); - } if let Some((custom_bounds,)) = custom_bounds { errors.error( custom_bounds, @@ -298,8 +287,6 @@ impl ParsedTypeAlias { no_runtime_generics: _, cmp_eq, ref mut get, - ref custom_debug, - custom_sim_display, } = options.body; if let Some(get) = get.take() { return Self::parse_phantom_const_accessor( @@ -324,15 +311,6 @@ impl ParsedTypeAlias { if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); } - if let Some((custom_debug, _, _)) = custom_debug { - errors.error(custom_debug, "custom_debug is not valid on type aliases"); - } - if let Some((custom_sim_display,)) = custom_sim_display { - errors.error( - custom_sim_display, - "custom_sim_display is not valid on type aliases", - ); - } let generics = if custom_bounds.is_some() { MaybeParsed::Unrecognized(generics) } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) { @@ -378,8 +356,6 @@ impl ToTokens for ParsedTypeAlias { no_runtime_generics, cmp_eq: _, get: _, - custom_debug: _, - custom_sim_display: _, } = &options.body; let target = get_target(target, ident); let mut type_attrs = attrs.clone(); @@ -426,8 +402,6 @@ impl ToTokens for ParsedTypeAlias { no_runtime_generics: _, cmp_eq: _, get: _, - custom_debug: _, - custom_sim_display: _, } = &options.body; let span = ident.span(); let mut type_attrs = attrs.clone(); @@ -453,7 +427,7 @@ impl ToTokens for ParsedTypeAlias { format_ident!("__{}__GenericsAccumulation", ident); ItemStruct { attrs: vec![ - common_derives(span, true), + common_derives(span), parse_quote_spanned! {span=> #[allow(non_camel_case_types)] }, diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index 18cffc6..3a0e5e9 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -7,10 +7,10 @@ use std::{collections::HashMap, fmt, mem}; use syn::{ AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup, ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed, - FieldsUnnamed, FnArg, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, - ItemStruct, Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, - Turbofish, Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, - TypeTuple, Visibility, WhereClause, WherePredicate, + FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct, + Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish, + Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple, + Visibility, WhereClause, WherePredicate, parse::{Parse, ParseStream}, parse_quote, parse_quote_spanned, punctuated::{Pair, Punctuated}, @@ -18,17 +18,6 @@ use syn::{ token::{Brace, Bracket, Paren}, }; -crate::options! { - #[options = CustomDebugOptions] - #[no_ident_fragment] - pub(crate) enum CustomDebugOption { - Type(type_), - Sim(sim), - MaskType(mask_type), - MaskSim(mask_sim), - } -} - crate::options! { #[options = ItemOptions] pub(crate) enum ItemOption { @@ -39,8 +28,6 @@ crate::options! { NoRuntimeGenerics(no_runtime_generics), CmpEq(cmp_eq), Get(get, Expr), - CustomDebug(custom_debug, CustomDebugOptions), - CustomSimDisplay(custom_sim_display), } } @@ -54,36 +41,8 @@ impl ItemOptions { { self.no_static = Some((kw::no_static(custom_bounds.span),)); } - if let Some((kw, _, custom_debug)) = &mut self.custom_debug { - if let CustomDebugOptions { - type_: None, - sim: None, - mask_type: None, - mask_sim: None, - } = custom_debug - { - *custom_debug = CustomDebugOptions { - type_: Some((kw::type_(kw.span),)), - sim: Some((kw::sim(kw.span),)), - mask_type: None, - mask_sim: None, - }; - } - } Ok(()) } - pub(crate) fn custom_debug(&self) -> &CustomDebugOptions { - self.custom_debug.as_ref().map(|v| &v.2).unwrap_or( - const { - &CustomDebugOptions { - type_: None, - sim: None, - mask_type: None, - mask_sim: None, - } - }, - ) - } } pub(crate) struct WrappedInConst<'a> { @@ -125,17 +84,10 @@ pub(crate) fn get_target(target: &Option<(kw::target, Paren, Path)>, item_ident: } } -pub(crate) fn common_derives(span: Span, include_debug: bool) -> Attribute { - let debug = include_debug - .then(|| { - quote_spanned! {span=> - ::fayalite::__std::fmt::Debug - } - }) - .into_iter(); +pub(crate) fn common_derives(span: Span) -> Attribute { parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - #(#debug,)* + ::fayalite::__std::fmt::Debug, ::fayalite::__std::cmp::Eq, ::fayalite::__std::cmp::PartialEq, ::fayalite::__std::hash::Hash, @@ -3023,7 +2975,7 @@ impl ParsedGenerics { let span = ident.span(); ItemStruct { attrs: vec![ - common_derives(span, true), + common_derives(span), parse_quote_spanned! {span=> #[allow(non_camel_case_types)] }, @@ -4781,109 +4733,3 @@ impl ParsedVisibility { .map(|ord| if ord.is_lt() { self } else { other }) } } - -pub(crate) struct CustomDebugTrait<'a> { - pub(crate) trait_path: &'a Path, - pub(crate) fn_name: &'a Ident, - pub(crate) this_arg: &'a FnArg, -} - -#[must_use] -pub(crate) fn create_struct_debug_impl( - item_struct: &ItemStruct, - debug_struct_name: &str, - custom_debug_trait: Option>, -) -> TokenStream { - let ident = &item_struct.ident; - let span = ident.span(); - let (impl_generics, type_generics, where_clause) = item_struct.generics.split_for_impl(); - let trait_path; - let fn_name; - let this_arg; - let CustomDebugTrait { - trait_path, - fn_name, - this_arg, - } = match custom_debug_trait { - Some(v) => v, - None => { - trait_path = parse_quote_spanned! {span=> - ::fayalite::__std::fmt::Debug - }; - fn_name = parse_quote_spanned! {span=> - fmt - }; - this_arg = parse_quote_spanned! {span=> - &self - }; - CustomDebugTrait { - trait_path: &trait_path, - fn_name: &fn_name, - this_arg: &this_arg, - } - } - }; - let this_arg_name = match this_arg { - FnArg::Receiver(this_arg) => this_arg.self_token.to_token_stream(), - FnArg::Typed(this_arg) => match &*this_arg.pat { - syn::Pat::Ident(pat_ident) => pat_ident.ident.to_token_stream(), - _ => unreachable!(), - }, - }; - match &item_struct.fields { - Fields::Named(fields) => { - let field_idents = fields - .named - .iter() - .map(|v| v.ident.as_ref().expect("known to have field name")); - let field_names = field_idents.clone().map(|v| v.to_string()); - quote_spanned! {span=> - #[automatically_derived] - impl #impl_generics #trait_path for #ident #type_generics - #where_clause - { - fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - let _ = #this_arg_name; - f.debug_struct(#debug_struct_name) - #(.field(#field_names, &#this_arg_name.#field_idents))* - .finish() - } - } - } - } - Fields::Unnamed(fields) => { - let field_members = fields - .unnamed - .iter() - .enumerate() - .map(|(index, _)| syn::Index { - index: index as _, - span, - }); - quote_spanned! {span=> - #[automatically_derived] - impl #impl_generics #trait_path for #ident #type_generics - #where_clause - { - fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - let _ = #this_arg_name; - f.debug_tuple(#debug_struct_name) - #(.field(&#this_arg_name.#field_members))* - .finish() - } - } - } - } - Fields::Unit => quote_spanned! {ident.span()=> - #[automatically_derived] - impl #impl_generics #trait_path for #ident #type_generics - #where_clause - { - fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { - let _ = #this_arg_name; - f.write_str(#debug_struct_name) - } - } - }, - } -} diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs index 905cb05..152053c 100644 --- a/crates/fayalite-proc-macros-impl/src/lib.rs +++ b/crates/fayalite-proc-macros-impl/src/lib.rs @@ -42,7 +42,6 @@ pub(crate) trait CustomToken: mod kw { pub(crate) use syn::token::Extern as extern_; - pub(crate) use syn::token::Type as type_; macro_rules! custom_keyword { ($kw:ident) => { @@ -76,8 +75,6 @@ mod kw { custom_keyword!(cmp_eq); custom_keyword!(connect_inexact); custom_keyword!(custom_bounds); - custom_keyword!(custom_debug); - custom_keyword!(custom_sim_display); custom_keyword!(flip); custom_keyword!(get); custom_keyword!(hdl); @@ -86,8 +83,6 @@ mod kw { custom_keyword!(input); custom_keyword!(instance); custom_keyword!(m); - custom_keyword!(mask_sim); - custom_keyword!(mask_type); custom_keyword!(memory); custom_keyword!(memory_array); custom_keyword!(memory_with_init); diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs index 605f662..ca06c0b 100644 --- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs +++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs @@ -1096,9 +1096,11 @@ impl Visitor<'_> { let (#(#bindings,)*) = { type __MatchTy = ::SimValue; let __match_value = #expr; - // use method syntax to deduce what type to convert to - let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value) - .__fayalite_match_sim_value(); + let __match_value = { + use ::fayalite::sim::value::match_sim_value::*; + // use method syntax to deduce the correct trait to call + ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() + }; #let_token #pat #eq_token __match_value #semi_token (#(#bindings_idents,)*) }; @@ -1170,9 +1172,11 @@ impl Visitor<'_> { { type __MatchTy = ::SimValue; let __match_value = #expr; - // use method syntax to deduce what type to convert to - let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value) - .__fayalite_match_sim_value(); + let __match_value = { + use ::fayalite::sim::value::match_sim_value::*; + // use method syntax to deduce the correct trait to call + ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() + }; #match_token __match_value { #(#arms)* } diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs index 065e5de..8d70d21 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs @@ -95,11 +95,11 @@ //! } //! //! #[hdl] -//! fn destructure_inner(v: as Type>::SimValue) { +//! fn destructure_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { //! #[hdl(sim)] //! let MyStruct:: { //! a, -//! mut b, +//! b, //! c, //! } = v; //! @@ -107,38 +107,5 @@ //! let _: SimValue> = a; //! let _: SimValue = b; //! let _: SimValue = c; -//! *b = false; // can modify b since mut was used -//! } -//! -//! #[hdl] -//! fn destructure_inner_ref<'a, T: Type>(v: &'a as Type>::SimValue) { -//! #[hdl(sim)] -//! let MyStruct:: { -//! a, -//! b, -//! c, -//! } = v; -//! -//! // that gives these types: -//! let _: &'a SimValue> = a; -//! let _: &'a SimValue = b; -//! let _: &'a SimValue = c; -//! } -//! -//! #[hdl] -//! fn destructure_inner_mut<'a, T: Type>(v: &'a mut as Type>::SimValue) { -//! #[hdl(sim)] -//! let MyStruct:: { -//! a, -//! b, -//! c, -//! } = v; -//! -//! **b = true; // you can modify v by modifying b which borrows from it -//! -//! // that gives these types: -//! let _: &'a mut SimValue> = a; -//! let _: &'a mut SimValue = b; -//! let _: &'a mut SimValue = c; //! } //! ``` diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs index 9e2d41d..accd3d7 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs @@ -72,47 +72,15 @@ //! } //! //! #[hdl] -//! fn match_inner_move(v: as Type>::SimValue) -> String { +//! fn match_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { //! #[hdl(sim)] //! match v { -//! MyEnum::::A => String::from("got A"), -//! MyEnum::::B(mut b) => { +//! MyEnum::::A => println!("got A"), +//! MyEnum::::B(b) => { //! let _: SimValue = b; // b has this type -//! let text = format!("got B({b})"); -//! *b = true; // can modify b since mut was used -//! text -//! } -//! _ => String::from("something else"), -//! } -//! } -//! -//! #[hdl] -//! fn match_inner_ref<'a, T: Type>(v: &'a as Type>::SimValue) -> u32 { -//! #[hdl(sim)] -//! match v { -//! MyEnum::::A => 1, -//! MyEnum::::B(b) => { -//! let _: &'a SimValue = b; // b has this type //! println!("got B({b})"); -//! 5 //! } -//! _ => 42, -//! } -//! } -//! -//! #[hdl] -//! fn match_inner_mut<'a, T: Type>(v: &'a mut as Type>::SimValue) -> Option<&'a mut SimValue> { -//! #[hdl(sim)] -//! match v { -//! MyEnum::::A => None, -//! MyEnum::::B(b) => { -//! println!("got B({b})"); -//! **b = true; // you can modify v by modifying b which borrows from it -//! let _: &'a mut SimValue = b; // b has this type -//! None -//! } -//! MyEnum::::C(v) => Some(v), // you can return matched values -//! _ => None, // HDL enums can have invalid discriminants, so we need this extra match arm +//! _ => println!("something else"), //! } //! } //! ``` diff --git a/crates/fayalite/src/annotations.rs b/crates/fayalite/src/annotations.rs index 252a0ce..4ca84dd 100644 --- a/crates/fayalite/src/annotations.rs +++ b/crates/fayalite/src/annotations.rs @@ -238,10 +238,7 @@ impl TargetedAnnotation { } #[track_caller] pub fn assert_valid_target(target: Interned) { - assert!( - target.is_valid_annotation_target(), - "not a valid annotation target: {target:?}", - ); + assert!(target.is_static(), "can't annotate non-static targets"); } pub fn target(&self) -> Interned { self.target diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs index fa754fd..6ca6809 100644 --- a/crates/fayalite/src/array.rs +++ b/crates/fayalite/src/array.rs @@ -13,13 +13,13 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantWithoutScope, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, TypeWithDeref, + OpaqueSimValueWritten, StaticType, Type, TypeProperties, TypeWithDeref, serde_impls::SerdeCanonicalType, }, util::ConstUsize, }; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error}; -use std::{borrow::Cow, fmt, iter::FusedIterator, ops::Index}; +use std::{borrow::Cow, iter::FusedIterator, ops::Index}; #[derive(Copy, Clone, PartialEq, Eq, Hash)] pub struct ArrayType { @@ -28,8 +28,8 @@ pub struct ArrayType { type_properties: TypeProperties, } -impl fmt::Debug for ArrayType { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { +impl std::fmt::Debug for ArrayType { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { write!(f, "Array<{:?}, {}>", self.element, self.len()) } } @@ -182,15 +182,6 @@ impl, Len: Size, State: Visitor + ?Sized> Visit } } -impl SimValueDebug for ArrayType { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl Type for ArrayType { type BaseType = Array; type MaskType = ArrayType; diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs index 5fad35c..1471f3a 100644 --- a/crates/fayalite/src/bundle.rs +++ b/crates/fayalite/src/bundle.rs @@ -14,8 +14,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantWithoutScope, OpaqueSimValue, OpaqueSimValueSize, - OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, - StaticType, Type, TypeProperties, TypeWithDeref, impl_match_variant_as_self, + OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, + TypeProperties, TypeWithDeref, impl_match_variant_as_self, }, util::HashMap, }; @@ -271,15 +271,6 @@ impl Type for Bundle { } } -impl SimValueDebug for Bundle { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - pub trait BundleType: Type { type Builder: Default; fn fields(&self) -> Interned<[BundleField]>; @@ -480,14 +471,6 @@ macro_rules! impl_tuples { #[var($var)] })*] } - impl<$($T: Type,)*> SimValueDebug for ($($T,)*) { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } - } impl<$($T: Type,)*> Type for ($($T,)*) { type BaseType = Bundle; type MaskType = ($($T::MaskType,)*); @@ -790,15 +773,6 @@ impl_tuples! { ] } -impl SimValueDebug for PhantomData { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl Type for PhantomData { type BaseType = Bundle; type MaskType = (); diff --git a/crates/fayalite/src/clock.rs b/crates/fayalite/src/clock.rs index 0e6d145..168142b 100644 --- a/crates/fayalite/src/clock.rs +++ b/crates/fayalite/src/clock.rs @@ -1,6 +1,5 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information - use crate::{ expr::{Expr, ValueType}, hdl, @@ -10,12 +9,10 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, - impl_match_variant_as_self, + OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self, }, }; use bitvec::{bits, order::Lsb0}; -use std::fmt; #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)] pub struct Clock; @@ -72,15 +69,6 @@ impl Type for Clock { } } -impl SimValueDebug for Clock { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl Clock { pub fn type_properties(self) -> TypeProperties { Self::TYPE_PROPERTIES diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs index f6af578..a04f67a 100644 --- a/crates/fayalite/src/enum_.rs +++ b/crates/fayalite/src/enum_.rs @@ -2,7 +2,7 @@ // See Notices.txt for copyright information use crate::{ - expr::{Expr, ToExpr, ValueType, ops::VariantAccess}, + expr::{Expr, HdlPartialEq, HdlPartialEqImpl, ToExpr, ValueType, ops::VariantAccess}, hdl, int::{Bool, UIntValue}, intern::{Intern, Interned}, @@ -10,18 +10,18 @@ use crate::{ EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope, connect, enum_match_variants_helper, incomplete_wire, wire, }, - sim::value::{SimValue, ToSimValue, ToSimValueWithType}, + sim::value::SimValue, source_location::SourceLocation, ty::{ CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, OpaqueSimValueSize, - OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, - StaticType, Type, TypeProperties, + OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, + TypeProperties, }, util::HashMap, }; use bitvec::{order::Lsb0, slice::BitSlice, view::BitView}; use serde::{Deserialize, Serialize}; -use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc}; +use std::{borrow::Cow, convert::Infallible, fmt, iter::FusedIterator, sync::Arc}; #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] pub struct EnumVariant { @@ -410,15 +410,6 @@ impl Type for Enum { } } -impl SimValueDebug for Enum { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - #[derive(Clone, PartialEq, Eq, Hash, Debug, Default)] pub struct EnumPaddingSimValue { bits: Option, @@ -732,12 +723,95 @@ pub fn enum_type_to_sim_builder(v: T) -> T::SimBuilder { v.into() } -#[hdl(cmp_eq)] +#[hdl] pub enum HdlOption { HdlNone, HdlSome(T), } +impl, Rhs: Type> HdlPartialEqImpl> + for HdlOption +{ + fn cmp_value_eq( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: HdlOption, + rhs_value: Cow<'_, as Type>::SimValue>, + ) -> bool { + type SimValueMatch = ::SimValue; + match (&*lhs_value, &*rhs_value) { + (SimValueMatch::::HdlNone(_), SimValueMatch::>::HdlNone(_)) => { + true + } + (SimValueMatch::::HdlSome(..), SimValueMatch::>::HdlNone(_)) + | (SimValueMatch::::HdlNone(_), SimValueMatch::>::HdlSome(..)) => { + false + } + ( + SimValueMatch::::HdlSome(l, _), + SimValueMatch::>::HdlSome(r, _), + ) => HdlPartialEqImpl::cmp_value_eq( + lhs.HdlSome, + Cow::Borrowed(&**l), + rhs.HdlSome, + Cow::Borrowed(&**r), + ), + } + } + + #[hdl] + fn cmp_expr_eq(lhs: Expr, rhs: Expr>) -> Expr { + #[hdl] + let cmp_eq = wire(); + #[hdl] + match lhs { + HdlSome(lhs) => + { + #[hdl] + match rhs { + HdlSome(rhs) => connect(cmp_eq, lhs.cmp_eq(rhs)), + HdlNone => connect(cmp_eq, false), + } + } + HdlNone => + { + #[hdl] + match rhs { + HdlSome(_) => connect(cmp_eq, false), + HdlNone => connect(cmp_eq, true), + } + } + } + cmp_eq + } + + #[hdl] + fn cmp_expr_ne(lhs: Expr, rhs: Expr>) -> Expr { + #[hdl] + let cmp_ne = wire(); + #[hdl] + match lhs { + HdlSome(lhs) => + { + #[hdl] + match rhs { + HdlSome(rhs) => connect(cmp_ne, lhs.cmp_ne(rhs)), + HdlNone => connect(cmp_ne, true), + } + } + HdlNone => + { + #[hdl] + match rhs { + HdlSome(_) => connect(cmp_ne, true), + HdlNone => connect(cmp_ne, false), + } + } + } + cmp_ne + } +} + #[allow(non_snake_case)] pub fn HdlNone() -> Expr> { HdlOption[T::TYPE].HdlNone() @@ -749,123 +823,6 @@ pub fn HdlSome(value: impl ToExpr) -> Expr> { HdlOption[value.ty()].HdlSome(value) } -impl From>> for Option> { - #[hdl] - fn from(value: SimValue>) -> Self { - #[hdl(sim)] - match value { - HdlSome(v) => Some(v), - HdlNone => None, - } - } -} - -impl<'a, T: Type> From<&'a SimValue>> for Option<&'a SimValue> { - #[hdl] - fn from(value: &'a SimValue>) -> Self { - #[hdl(sim)] - match value { - HdlSome(v) => Some(v), - HdlNone => None, - } - } -} - -impl<'a, T: Type> From<&'a mut SimValue>> for Option<&'a mut SimValue> { - #[hdl] - fn from(value: &'a mut SimValue>) -> Self { - #[hdl(sim)] - match value { - HdlSome(v) => Some(v), - HdlNone => None, - } - } -} - -impl>> ValueType for Option { - type Type = HdlOption; - type ValueCategory = T::ValueCategory; - - fn ty(&self) -> Self::Type { - StaticType::TYPE - } -} - -impl> ToSimValueWithType> for Option { - #[hdl] - fn to_sim_value_with_type(&self, ty: HdlOption) -> SimValue> { - match self { - Some(v) => - { - #[hdl(sim)] - ty.HdlSome(v) - } - None => - { - #[hdl(sim)] - ty.HdlNone() - } - } - } - #[hdl] - fn into_sim_value_with_type(self, ty: HdlOption) -> SimValue> { - match self { - Some(v) => - { - #[hdl(sim)] - ty.HdlSome(v) - } - None => - { - #[hdl(sim)] - ty.HdlNone() - } - } - } -} - -impl>> ToSimValue for Option { - #[hdl] - fn to_sim_value(&self) -> SimValue { - match self { - Some(v) => - { - #[hdl(sim)] - HdlSome(v) - } - None => - { - #[hdl(sim)] - HdlNone() - } - } - } - #[hdl] - fn into_sim_value(self) -> SimValue { - match self { - Some(v) => - { - #[hdl(sim)] - HdlSome(v) - } - None => - { - #[hdl(sim)] - HdlNone() - } - } - } -} - -impl>> ToExpr for Option { - fn to_expr(&self) -> Expr { - match self { - Some(v) => HdlSome(v), - None => HdlNone(), - } - } -} - impl HdlOption { #[track_caller] pub fn try_map( diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs index eb4bf0f..00a0cee 100644 --- a/crates/fayalite/src/expr.rs +++ b/crates/fayalite/src/expr.rs @@ -6,7 +6,6 @@ use crate::{ bundle::{Bundle, BundleType}, enum_::{Enum, EnumType}, expr::target::{GetTarget, Target}, - formal::FormalInput, int::{Bool, DynSize, IntType, SIntValue, Size, SizeType, UInt, UIntType, UIntValue}, intern::{Intern, Interned}, memory::{DynPortType, MemPort, PortType}, @@ -18,7 +17,7 @@ use crate::{ reg::Reg, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, sim::value::{SimValue, ToSimValue, ToSimValueWithType}, - ty::{CanonicalType, OpaqueSimValue, StaticType, TraceAsString, Type, TypeWithDeref}, + ty::{CanonicalType, OpaqueSimValue, StaticType, Type, TypeWithDeref}, util::{ConstBool, ConstUsize}, wire::Wire, }; @@ -219,8 +218,6 @@ expr_enum! { SliceSInt(ops::SliceSInt), CastToBits(ops::CastToBits), CastBitsTo(ops::CastBitsTo), - ToTraceAsString(ops::ToTraceAsString), - TraceAsStringAsInner(ops::TraceAsStringAsInner), ModuleIO(ModuleIO), Instance(Instance), Wire(Wire), @@ -228,8 +225,6 @@ expr_enum! { RegSync(Reg), RegAsync(Reg), MemPort(MemPort), - FormalInput(FormalInput), - SimIoForGlobal(ops::SimIoForGlobal), } } @@ -394,35 +389,6 @@ impl Expr { __flow: this.__flow, } } - #[track_caller] - pub fn as_trace_as_string(this: Self, ty: TraceAsString) -> Expr> { - assert_eq!(this.ty(), ty.inner_ty()); - ops::ToTraceAsString::new(Expr::canonical(this), ty).to_expr() - } -} - -impl Expr { - pub fn unwrap_transparent_types(mut this: Self) -> Expr { - loop { - match this.ty() { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) - | CanonicalType::Array(_) - | CanonicalType::Enum(_) - | CanonicalType::Bundle(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => return this, - CanonicalType::TraceAsString(_) => { - this = *Expr::::from_canonical(this); - } - } - } - } } impl ToLiteralBits for Expr { @@ -1726,204 +1692,3 @@ impl<'a, T: Type> ToSimValueInner<'a> for &'a SimValue { Cow::Borrowed(&**this) } } - -pub trait ToTraceAsString: ValueType { - type Output: ValueType, ValueCategory = Self::ValueCategory>; - fn to_trace_as_string_with_ty(&self, ty: TraceAsString) -> Self::Output; - fn into_trace_as_string_with_ty(self, ty: TraceAsString) -> Self::Output - where - Self: Sized; - fn to_trace_as_string(&self) -> Self::Output; - fn into_trace_as_string(self) -> Self::Output - where - Self: Sized; -} - -impl< - T: ?Sized - + ValueType - + ToTraceAsStringImpl<::Type, ::ValueCategory>, -> ToTraceAsString for T -{ - type Output = T::ImplOutput; - fn to_trace_as_string_with_ty(&self, ty: TraceAsString) -> Self::Output { - Self::to_trace_as_string_with_ty_impl(self, ty) - } - fn into_trace_as_string_with_ty(self, ty: TraceAsString) -> Self::Output - where - Self: Sized, - { - Self::into_trace_as_string_with_ty_impl(self, ty) - } - fn to_trace_as_string(&self) -> Self::Output { - Self::to_trace_as_string_impl(self) - } - fn into_trace_as_string(self) -> Self::Output - where - Self: Sized, - { - Self::into_trace_as_string_impl(self) - } -} - -pub trait ToTraceAsStringImpl { - type ImplOutput: ValueType, ValueCategory = C>; - fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput; - fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput - where - Self: Sized; - fn to_trace_as_string_with_ty_impl(this: &Self, ty: TraceAsString) -> Self::ImplOutput; - fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput - where - Self: Sized; -} - -impl - ToTraceAsStringImpl for T -{ - type ImplOutput = crate::ty::TraceAsStringSimValue; - - fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { - crate::ty::TraceAsStringSimValue::new(this) - } - - fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput - where - Self: Sized, - { - crate::ty::TraceAsStringSimValue::new(this) - } - - fn to_trace_as_string_with_ty_impl( - this: &Self, - ty: TraceAsString, - ) -> Self::ImplOutput { - crate::ty::TraceAsStringSimValue::new_with_ty(this, ty) - } - - fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput - where - Self: Sized, - { - crate::ty::TraceAsStringSimValue::new_with_ty(this, ty) - } -} - -impl - ToTraceAsStringImpl for T -{ - type ImplOutput = SimValue>; - - fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { - crate::ty::TraceAsStringSimValue::new(this).into_sim_value() - } - - fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput - where - Self: Sized, - { - crate::ty::TraceAsStringSimValue::new(this).into_sim_value() - } - - fn to_trace_as_string_with_ty_impl( - this: &Self, - ty: TraceAsString, - ) -> Self::ImplOutput { - crate::ty::TraceAsStringSimValue::new_with_ty(this, ty).into_sim_value() - } - - fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput - where - Self: Sized, - { - crate::ty::TraceAsStringSimValue::new_with_ty(this, ty).into_sim_value() - } -} - -impl ToTraceAsStringImpl for T { - type ImplOutput = Expr>; - - fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { - let this = this.to_expr(); - ops::ToTraceAsString::new(Expr::canonical(this), TraceAsString::new(this.ty())).to_expr() - } - - fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput - where - Self: Sized, - { - let this = this.to_expr(); - ops::ToTraceAsString::new(Expr::canonical(this), TraceAsString::new(this.ty())).to_expr() - } - - fn to_trace_as_string_with_ty_impl( - this: &Self, - ty: TraceAsString, - ) -> Self::ImplOutput { - let this = this.to_expr(); - ops::ToTraceAsString::new( - Expr::canonical(this), - ty.with_new_inner_ty(this.ty().intern_sized()), - ) - .to_expr() - } - - fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput - where - Self: Sized, - { - let this = this.to_expr(); - ops::ToTraceAsString::new( - Expr::canonical(this), - ty.with_new_inner_ty(this.ty().intern_sized()), - ) - .to_expr() - } -} - -impl ToTraceAsStringImpl - for T -{ - type ImplOutput = Valueless>; - - fn to_trace_as_string_impl(this: &Self) -> Self::ImplOutput { - Valueless::new(TraceAsString::new(this.ty())) - } - - fn into_trace_as_string_impl(this: Self) -> Self::ImplOutput - where - Self: Sized, - { - Valueless::new(TraceAsString::new(this.ty())) - } - - fn to_trace_as_string_with_ty_impl( - this: &Self, - ty: TraceAsString, - ) -> Self::ImplOutput { - Valueless::new(ty.with_new_inner_ty(this.ty().intern_sized())) - } - - fn into_trace_as_string_with_ty_impl(this: Self, ty: TraceAsString) -> Self::ImplOutput - where - Self: Sized, - { - Valueless::new(ty.with_new_inner_ty(this.ty().intern_sized())) - } -} - -impl ToLiteralBits for FormalInput { - fn to_literal_bits(&self) -> Result, NotALiteralExpr> { - Err(NotALiteralExpr) - } -} - -impl ToExpr for FormalInput { - fn to_expr(&self) -> Expr { - Expr { - __enum: ExprEnum::FormalInput(*self).intern_sized(), - __ty: self.ty(), - __flow: self.flow(), - } - } -} diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs index 5d335a5..f4cfebd 100644 --- a/crates/fayalite/src/expr/ops.rs +++ b/crates/fayalite/src/expr/ops.rs @@ -12,12 +12,10 @@ use crate::{ ToExpr, ToLiteralBits, ToSimValueInner, ToValueless, ValueType, Valueless, target::{ GetTarget, Target, TargetPathArrayElement, TargetPathBundleField, - TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString, - TargetPathTraceAsStringInner, + TargetPathDynArrayElement, TargetPathElement, }, value_category::ValueCategoryExpr, }, - formal::FormalInput, int::{ Bool, BoolOrIntType, DynSize, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue, @@ -29,7 +27,7 @@ use crate::{ ToSyncReset, }, sim::value::{SimValue, ToSimValue}, - ty::{CanonicalType, StaticType, TraceAsString, Type}, + ty::{CanonicalType, StaticType, Type}, util::ConstUsize, }; use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView}; @@ -46,9 +44,6 @@ use std::{ }, }; -#[cfg(test)] -mod test_ops_impls; - macro_rules! make_impls { ( $([$($args:tt)*])? @@ -588,6 +583,9 @@ macro_rules! make_impls { #[cfg(test)] pub(crate) use make_impls; +#[cfg(test)] +mod test_ops_impls; + macro_rules! impl_simple_binary_op_trait { ( [$($LLifetimes:tt)*][$($LBounds:tt)*] ($($L:tt)*), @@ -4696,255 +4694,3 @@ impl, A> FromIterator for Expr { This::expr_from_iter(iter) } } - -#[derive(Copy, Clone, PartialEq, Eq, Hash)] -pub struct ToTraceAsString { - inner: Expr, - ty: TraceAsString, - literal_bits: Result, NotALiteralExpr>, - target: Option>, -} - -impl fmt::Debug for ToTraceAsString { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - inner, - ty: _, - literal_bits: _, - target: _, - } = self; - f.debug_struct("ToTraceAsString") - .field("inner", inner) - .finish_non_exhaustive() - } -} - -impl ToTraceAsString { - pub fn new(inner: Expr, ty: TraceAsString) -> Self { - assert_eq!(inner.ty(), ty.inner_ty().canonical()); - let literal_bits = inner.to_literal_bits(); - let target = inner.target().map(|base| { - Intern::intern_sized( - base.join(TargetPathElement::intern_sized( - TargetPathToTraceAsString { - ty: ty.canonical_trace_as_string(), - } - .into(), - )) - .canonicalized(), - ) - }); - Self { - inner, - ty, - literal_bits, - target, - } - } - pub fn inner(self) -> Expr { - self.inner - } -} - -impl GetTarget for ToTraceAsString { - fn target(&self) -> Option> { - self.target - } -} - -impl ToLiteralBits for ToTraceAsString { - fn to_literal_bits(&self) -> Result, NotALiteralExpr> { - self.literal_bits - } -} - -impl ValueType for ToTraceAsString { - type Type = TraceAsString; - type ValueCategory = ValueCategoryExpr; - - fn ty(&self) -> Self::Type { - self.ty - } -} - -impl ToExpr for ToTraceAsString { - fn to_expr(&self) -> Expr { - Expr { - __enum: ExprEnum::ToTraceAsString(ToTraceAsString { - inner: self.inner, - ty: self.ty.canonical_trace_as_string(), - literal_bits: self.literal_bits, - target: self.target, - }) - .intern(), - __ty: self.ty, - __flow: Expr::flow(self.inner), - } - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash)] -pub struct TraceAsStringAsInner { - arg: Expr>, - ty: T, - literal_bits: Result, NotALiteralExpr>, - target: Option>, -} - -impl fmt::Debug for TraceAsStringAsInner { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - arg, - ty: _, - literal_bits: _, - target: _, - } = self; - f.debug_struct("TraceAsStringAsInner") - .field("arg", arg) - .finish_non_exhaustive() - } -} - -impl TraceAsStringAsInner { - pub fn from_arg_and_ty(arg: Expr>, ty: T) -> Self { - assert_eq!(arg.ty().inner_ty(), ty.canonical()); - let literal_bits = arg.to_literal_bits(); - let target = arg.target().map(|base| { - Intern::intern_sized( - base.join(TargetPathElement::intern_sized( - TargetPathTraceAsStringInner {}.into(), - )) - .canonicalized(), - ) - }); - Self { - arg, - ty, - literal_bits, - target, - } - } - pub fn new(arg: Expr>) -> Self { - Self::from_arg_and_ty( - Expr { - __enum: arg.__enum, - __ty: arg.__ty.canonical_trace_as_string(), - __flow: arg.__flow, - }, - arg.ty().inner_ty(), - ) - } - pub fn arg(self) -> Expr> { - self.arg - } - pub fn arg_typed(self) -> Expr> { - Expr { - __enum: self.arg.__enum, - __ty: TraceAsString::from_canonical_trace_as_string(self.arg.__ty), - __flow: self.arg.__flow, - } - } -} - -impl GetTarget for TraceAsStringAsInner { - fn target(&self) -> Option> { - self.target - } -} - -impl ToLiteralBits for TraceAsStringAsInner { - fn to_literal_bits(&self) -> Result, NotALiteralExpr> { - self.literal_bits - } -} - -impl ValueType for TraceAsStringAsInner { - type Type = T; - type ValueCategory = ValueCategoryExpr; - - fn ty(&self) -> Self::Type { - self.ty - } -} - -impl ToExpr for TraceAsStringAsInner { - fn to_expr(&self) -> Expr { - Expr { - __enum: ExprEnum::TraceAsStringAsInner(TraceAsStringAsInner { - arg: self.arg, - ty: self.ty.canonical(), - literal_bits: self.literal_bits, - target: self.target, - }) - .intern(), - __ty: self.ty, - __flow: Expr::flow(self.arg), - } - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash)] -/// The [`Simulation::io()`] equivalent for a global signal, this is a flipped version of a global signal -/// that allows you to e.g. use [`Simulation::write()`] to write to [`formal_global_clock()`]. -/// -/// [`Simulation::io()`]: crate::sim::Simulation::io -/// [`Simulation::write()`]: crate::sim::Simulation::write -/// [`formal_global_clock()`]: crate::formal::formal_global_clock -pub struct SimIoForGlobal { - global: FormalInput, -} - -impl fmt::Debug for SimIoForGlobal { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_tuple("SimIoForGlobal").field(&self.global).finish() - } -} - -impl SimIoForGlobal { - pub fn new(global: FormalInput) -> Self { - Self { global } - } - pub fn global(self) -> FormalInput { - self.global - } - pub(crate) fn must_connect_to(self) -> bool { - true - } - pub fn flow(self) -> Flow { - self.global.flow().flip() - } - pub(crate) fn source_location(self) -> crate::source_location::SourceLocation { - self.global.source_location() - } -} - -impl GetTarget for SimIoForGlobal { - fn target(&self) -> Option> { - Some(Target::from(*self).intern_sized()) - } -} - -impl ToLiteralBits for SimIoForGlobal { - fn to_literal_bits(&self) -> Result, NotALiteralExpr> { - Err(NotALiteralExpr) - } -} - -impl ValueType for SimIoForGlobal { - type Type = CanonicalType; - type ValueCategory = ValueCategoryExpr; - - fn ty(&self) -> Self::Type { - self.global.ty() - } -} - -impl ToExpr for SimIoForGlobal { - fn to_expr(&self) -> Expr { - Expr { - __enum: ExprEnum::SimIoForGlobal(*self).intern(), - __ty: self.ty(), - __flow: self.flow(), - } - } -} diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs index d7775ec..95d8e0f 100644 --- a/crates/fayalite/src/expr/target.rs +++ b/crates/fayalite/src/expr/target.rs @@ -4,14 +4,13 @@ use crate::{ array::Array, bundle::{Bundle, BundleField}, expr::{Expr, Flow, ToExpr, ValueType, value_category::ValueCategoryExpr}, - formal::FormalInput, intern::{Intern, Interned}, memory::{DynPortType, MemPort}, module::{Instance, ModuleIO, TargetName}, reg::Reg, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, source_location::SourceLocation, - ty::{CanonicalType, TraceAsString, Type}, + ty::{CanonicalType, Type}, wire::Wire, }; use std::fmt; @@ -47,33 +46,11 @@ impl fmt::Display for TargetPathDynArrayElement { } } -#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] -pub struct TargetPathTraceAsStringInner {} - -impl fmt::Display for TargetPathTraceAsStringInner { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!(f, ".") - } -} - -#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] -pub struct TargetPathToTraceAsString { - pub ty: TraceAsString, -} - -impl fmt::Display for TargetPathToTraceAsString { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - write!(f, ".to_trace_as_string(...)") - } -} - #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] pub enum TargetPathElement { BundleField(TargetPathBundleField), ArrayElement(TargetPathArrayElement), DynArrayElement(TargetPathDynArrayElement), - TraceAsStringInner(TargetPathTraceAsStringInner), - ToTraceAsString(TargetPathToTraceAsString), } impl From for TargetPathElement { @@ -94,26 +71,12 @@ impl From for TargetPathElement { } } -impl From for TargetPathElement { - fn from(value: TargetPathTraceAsStringInner) -> Self { - Self::TraceAsStringInner(value) - } -} - -impl From for TargetPathElement { - fn from(value: TargetPathToTraceAsString) -> Self { - Self::ToTraceAsString(value) - } -} - impl fmt::Display for TargetPathElement { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self { Self::BundleField(v) => v.fmt(f), Self::ArrayElement(v) => v.fmt(f), Self::DynArrayElement(v) => v.fmt(f), - Self::TraceAsStringInner(v) => v.fmt(f), - Self::ToTraceAsString(v) => v.fmt(f), } } } @@ -137,15 +100,6 @@ impl TargetPathElement { let parent_ty = Array::::from_canonical(parent.canonical_ty()); parent_ty.element() } - Self::TraceAsStringInner(_) => { - let parent_ty = - TraceAsString::::from_canonical(parent.canonical_ty()); - parent_ty.inner_ty() - } - &Self::ToTraceAsString(TargetPathToTraceAsString { ty }) => { - assert_eq!(parent.canonical_ty(), ty.inner_ty()); - ty.canonical() - } } } pub fn flow(&self, parent: Interned) -> Flow { @@ -157,18 +111,13 @@ impl TargetPathElement { .expect("field name is known to be a valid field of parent type"); parent.flow().flip_if(field.flipped) } - Self::ArrayElement(_) - | Self::DynArrayElement(_) - | Self::TraceAsStringInner(_) - | Self::ToTraceAsString(_) => parent.flow(), + Self::ArrayElement(_) => parent.flow(), + Self::DynArrayElement(_) => parent.flow(), } } pub fn is_static(&self) -> bool { match self { - Self::BundleField(_) - | Self::ArrayElement(_) - | Self::TraceAsStringInner(_) - | Self::ToTraceAsString(_) => true, + Self::BundleField(_) | Self::ArrayElement(_) => true, Self::DynArrayElement(_) => false, } } @@ -296,14 +245,6 @@ impl_target_base! { #[is = is_instance] #[to = instance] Instance(Instance), - #[from = from] - #[is = is_formal_input] - #[to = formal_input] - FormalInput(FormalInput), - #[from = from] - #[is = is_sim_io_for_global] - #[to = sim_io_for_global] - SimIoForGlobal(crate::expr::ops::SimIoForGlobal), } } @@ -352,8 +293,6 @@ impl TargetBase { TargetBase::RegAsync(v) => TargetName(v.scoped_name(), None), TargetBase::Wire(v) => TargetName(v.scoped_name(), None), TargetBase::Instance(v) => TargetName(v.scoped_name(), None), - TargetBase::FormalInput(v) => TargetName(v.scoped_name(), None), - TargetBase::SimIoForGlobal(v) => TargetName(v.global().scoped_name(), None), } } pub fn canonical_ty(&self) -> CanonicalType { @@ -365,21 +304,6 @@ impl TargetBase { TargetBase::RegAsync(v) => v.ty(), TargetBase::Wire(v) => v.ty(), TargetBase::Instance(v) => v.ty().canonical(), - TargetBase::FormalInput(v) => v.ty(), - TargetBase::SimIoForGlobal(v) => v.ty(), - } - } - pub fn is_valid_annotation_target(&self) -> bool { - match self { - Self::ModuleIO(_) => true, - Self::MemPort(_) => true, - Self::Reg(_) => true, - Self::RegSync(_) => true, - Self::RegAsync(_) => true, - Self::Wire(_) => true, - Self::Instance(_) => true, - Self::FormalInput(_) => false, - Self::SimIoForGlobal(_) => false, } } } @@ -390,7 +314,6 @@ pub struct TargetChild { path_element: Interned, canonical_ty: CanonicalType, flow: Flow, - canonicalized_if_different: Option>, } impl fmt::Debug for TargetChild { @@ -400,7 +323,6 @@ impl fmt::Debug for TargetChild { path_element, canonical_ty: _, flow: _, - canonicalized_if_different: _, } = self; parent.fmt(f)?; fmt::Display::fmt(path_element, f) @@ -414,7 +336,6 @@ impl fmt::Display for TargetChild { path_element, canonical_ty: _, flow: _, - canonicalized_if_different: _, } = self; parent.fmt(f)?; path_element.fmt(f) @@ -422,69 +343,14 @@ impl fmt::Display for TargetChild { } impl TargetChild { - fn new_helper( - parent: Interned, - path_element: Interned, - canonicalized_if_different: Option>, - ) -> Self { + pub fn new(parent: Interned, path_element: Interned) -> Self { Self { parent, path_element, canonical_ty: path_element.canonical_ty(parent), flow: path_element.flow(parent), - canonicalized_if_different, } } - fn make_canonicalized_if_different( - parent: Interned, - path_element: Interned, - ) -> Option> { - use TargetPathElement::*; - match *path_element { - BundleField(_) => {} - ArrayElement(_) => {} - DynArrayElement(_) => {} - TraceAsStringInner(_) => { - if let Some(child) = parent.canonicalized().child() { - match *child.path_element() { - BundleField(_) - | ArrayElement(_) - | DynArrayElement(_) - | TraceAsStringInner(_) => {} - ToTraceAsString(_) => return Some(child.parent()), - } - } - } - ToTraceAsString(TargetPathToTraceAsString { ty }) => { - if let Some(child) = parent.canonicalized().child() { - match *child.path_element() { - BundleField(_) | ArrayElement(_) | DynArrayElement(_) - | ToTraceAsString(_) => {} - TraceAsStringInner(_) => { - if ty.canonical() == child.parent().canonical_ty() { - return Some(child.parent()); - } - } - } - } - } - } - Some( - Target::Child(Self::new_helper( - parent.canonicalized_if_different()?, - path_element, - None, - )) - .intern_sized(), - ) - } - pub fn new(parent: Interned, path_element: Interned) -> Self { - Self::new_helper( - parent, - path_element, - Self::make_canonicalized_if_different(parent, path_element), - ) - } pub fn parent(self) -> Interned { self.parent } @@ -497,19 +363,6 @@ impl TargetChild { pub fn flow(self) -> Flow { self.flow } - pub fn is_canonicalized(self) -> bool { - self.canonicalized_if_different.is_none() - } - pub fn canonicalized_if_different(self) -> Option> { - self.canonicalized_if_different - } - #[must_use] - pub fn canonicalized(self) -> Target { - match self.canonicalized_if_different { - Some(v) => *v, - None => Target::Child(self), - } - } pub fn bundle_field(self) -> Option { if let TargetPathElement::BundleField(TargetPathBundleField { name }) = *self.path_element { let parent_ty = Bundle::from_canonical(self.parent.canonical_ty()); @@ -574,16 +427,6 @@ impl Target { } } } - pub fn is_valid_annotation_target(&self) -> bool { - let mut target = self; - loop { - match target { - Self::Base(target_base) => return target_base.is_valid_annotation_target(), - Self::Child(v) if !v.path_element().is_static() => return false, - Self::Child(v) => target = &v.parent, - } - } - } #[must_use] pub fn join(&self, path_element: Interned) -> Self { TargetChild::new(self.intern(), path_element).into() @@ -600,82 +443,6 @@ impl Target { Target::Child(v) => v.canonical_ty(), } } - pub fn is_canonicalized(self) -> bool { - match self { - Self::Base(_) => true, - Self::Child(child) => child.is_canonicalized(), - } - } - pub fn canonicalized_if_different(self) -> Option> { - match self { - Self::Base(_) => None, - Self::Child(child) => child.canonicalized_if_different(), - } - } - #[must_use] - pub fn canonicalized(self) -> Target { - match self.canonicalized_if_different() { - Some(v) => *v, - None => self, - } - } - #[must_use] - pub fn canonicalized_interned(this: Interned) -> Interned { - this.canonicalized_if_different().unwrap_or(this) - } - #[must_use] - pub fn unwrap_transparent_types(mut self) -> Target { - loop { - self = self.canonicalized(); - match self.canonical_ty() { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) - | CanonicalType::Array(_) - | CanonicalType::Enum(_) - | CanonicalType::Bundle(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => return self, - CanonicalType::TraceAsString(_) => { - if let Self::Child(child) = self - && let TargetPathElement::ToTraceAsString(_) = *child.path_element() - { - self = *child.parent(); - } else { - self = self.join(TargetPathElement::intern_sized( - TargetPathTraceAsStringInner {}.into(), - )); - } - } - } - } - } - #[must_use] - pub fn unwrap_transparent_types_interned(this: Interned) -> Interned { - let retval = this.unwrap_transparent_types(); - if retval != *this { - retval.intern_sized() - } else { - this - } - } - #[must_use] - pub fn without_trailing_transparent_path_elements(mut self) -> Target { - use TargetPathElement::*; - loop { - match self { - Self::Base(_) => return self, - Self::Child(child) => match *child.path_element() { - BundleField(_) | ArrayElement(_) | DynArrayElement(_) => return self, - TraceAsStringInner(_) | ToTraceAsString(_) => self = *child.parent(), - }, - } - } - } } impl fmt::Display for Target { @@ -700,18 +467,6 @@ pub trait GetTarget { fn target(&self) -> Option>; } -impl GetTarget for Target { - fn target(&self) -> Option> { - Some(self.intern()) - } -} - -impl GetTarget for TargetBase { - fn target(&self) -> Option> { - Some(Target::Base(self.intern()).intern_sized()) - } -} - impl GetTarget for bool { fn target(&self) -> Option> { None diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs index 60cc0d1..383bd95 100644 --- a/crates/fayalite/src/firrtl.rs +++ b/crates/fayalite/src/firrtl.rs @@ -2,42 +2,46 @@ // See Notices.txt for copyright information #![allow(clippy::type_complexity)] use crate::{ - annotations::{Annotation, IntoAnnotations, TargetedAnnotation}, + annotations::{ + Annotation, BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation, + DocStringAnnotation, DontTouchAnnotation, SVAttributeAnnotation, TargetedAnnotation, + }, + array::Array, build::{ToArgs, WriteArgs}, - bundle::{BundleField, BundleType}, - enum_::{EnumType, EnumVariant}, + bundle::{Bundle, BundleField, BundleType}, + clock::Clock, + enum_::{Enum, EnumType, EnumVariant}, expr::{ - ExprEnum, + CastBitsTo, Expr, ExprEnum, ToExpr, ValueType, ops::{self, VariantAccess}, target::{ Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement, - TargetPathTraceAsStringInner, }, }, - formal::{FormalInput, FormalInputKind, FormalKind}, - int::IntType, + formal::FormalKind, + int::{Bool, DynSize, IntType, SIntValue, UInt, UIntValue}, intern::{Intern, Interned}, - memory::{PortKind, PortName}, + memory::{Mem, PortKind, PortName, ReadUnderWrite}, module::{ AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter, - ExternModuleParameterValue, ModuleBody, ModuleIO, NameId, NameOptId, NormalModuleBody, - ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, + ExternModuleParameterValue, Module, ModuleBody, ModuleIO, NameId, NameOptId, + NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, transform::{ simplify_enums::{SimplifyEnumsError, SimplifyEnumsKind, simplify_enums}, simplify_memories::simplify_memories, - visit::Folder, }, }, - prelude::*, - reset::ResetType, - ty::OpaqueSimValueSize, + reset::{AsyncReset, Reset, ResetType, SyncReset}, + source_location::SourceLocation, + ty::{CanonicalType, OpaqueSimValueSize, Type}, util::{ BitSliceWriteWithBase, DebugAsRawString, GenericConstBool, HashMap, HashSet, const_str_array_is_strictly_ascending, }, vendor::xilinx::XilinxAnnotation, }; +use bitvec::slice::BitSlice; use clap::value_parser; use num_traits::Signed; use serde::{Deserialize, Serialize}; @@ -45,7 +49,6 @@ use std::{ cell::{Cell, RefCell}, cmp::Ordering, collections::{BTreeMap, VecDeque}, - convert::Infallible, error::Error, ffi::OsString, fmt::{self, Write}, @@ -55,7 +58,6 @@ use std::{ ops::{ControlFlow, Range}, path::{Path, PathBuf}, rc::Rc, - sync::OnceLock, }; #[derive(Clone, Debug)] @@ -375,90 +377,6 @@ impl DefinitionsMap { } } -#[derive(Default)] -struct BlockDefinitionsCache { - array_literal_exprs: - RefCell, bool), String>>, - bundle_literal_exprs: RefCell>, - uninit_exprs: RefCell>, - cast_bundle_to_bits_exprs: RefCell>, - cast_enum_to_bits_exprs: RefCell>, - cast_array_to_bits_exprs: RefCell>, - cast_bits_to_bundle_exprs: RefCell>, - cast_bits_to_enum_exprs: RefCell>, - cast_bits_to_array_exprs: RefCell>, - cast_bits_to_phantom_const_exprs: RefCell>, - per_module_formal_inputs: RefCell>, -} - -struct BlockDefinitions<'a> { - rc_definitions: RcDefinitions, - parent: Option<&'a BlockDefinitions<'a>>, - cache: BlockDefinitionsCache, -} - -impl<'a> BlockDefinitions<'a> { - fn new(parent: &'a BlockDefinitions<'a>) -> Self { - Self { - rc_definitions: RcDefinitions::default(), - parent: Some(parent), - cache: Default::default(), - } - } - fn module() -> Self { - Self { - rc_definitions: RcDefinitions::default(), - parent: None, - cache: Default::default(), - } - } - fn get_or_write_definition( - &self, - key: K, - field: impl Fn(&BlockDefinitionsCache) -> &RefCell>, - write_definition: impl FnOnce(BlockDefinitionsWriter<'_, '_>, &K) -> Result, - ) -> Result { - let mut current = self; - loop { - let field = field(¤t.cache).borrow(); - if let Some(retval) = field.get(&key) { - return Ok(retval.clone()); - } - let Some(parent) = current.parent else { - break; - }; - current = parent; - } - let retval = write_definition(BlockDefinitionsWriter { definitions: self }, &key)?; - Ok(field(&self.cache) - .borrow_mut() - .entry(key) - .or_insert(retval) - .clone()) - } - fn write_out(&self, indent: Indent<'_>, out: &mut String) { - self.rc_definitions.write_and_clear(indent, out); - } -} - -struct BlockDefinitionsWriter<'a, 'b> { - definitions: &'b BlockDefinitions<'a>, -} - -impl BlockDefinitionsWriter<'_, '_> { - fn add_definition_line(&self, v: impl fmt::Display) { - self.definitions.rc_definitions.add_definition_line(v); - } -} - -impl<'a> std::ops::Deref for BlockDefinitionsWriter<'a, '_> { - type Target = BlockDefinitions<'a>; - - fn deref(&self) -> &Self::Target { - &self.definitions - } -} - struct EnumDef { variants: RefCell, body: String, @@ -553,7 +471,7 @@ impl TypeState { Ok(self.enum_def(ty)?.1.variants.borrow_mut().get(name)) } fn ty(&self, ty: T) -> Result { - Ok(match ty.canonical().unwrap_transparent_types() { + Ok(match ty.canonical() { CanonicalType::Bundle(ty) => self.bundle_ty(ty)?.to_string(), CanonicalType::Enum(ty) => self.enum_ty(ty)?.to_string(), CanonicalType::Array(ty) => { @@ -572,25 +490,23 @@ impl TypeState { CanonicalType::DynSimOnly(_) => { return Err(FirrtlError::SimOnlyValuesAreNotPermitted); } - CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), }) } } struct ModuleState { - module: Interned>, ns: Namespace, + definitions: RcDefinitions, match_arm_values: HashMap, Ident>, - block_definitions: Rc>, } -impl ModuleState { - fn new(module: Interned>) -> Self { +impl Default for ModuleState { + fn default() -> Self { + let definitions = RcDefinitions::default(); Self { - module, ns: Default::default(), + definitions, match_arm_values: Default::default(), - block_definitions: Rc::new(BlockDefinitions::module()), } } } @@ -826,15 +742,6 @@ struct FirrtlAnnotation { target: AnnotationTarget, } -struct ResetSourceLocation; - -impl Folder for ResetSourceLocation { - type Error = Infallible; - fn fold_source_location(&mut self, _v: SourceLocation) -> Result { - Ok(SourceLocation::builtin()) - } -} - struct Exporter<'a> { file_backend: &'a mut dyn WrappedFileBackendTrait, indent: Indent<'a>, @@ -967,7 +874,7 @@ impl<'a> Exporter<'a> { &mut self, value: Expr, to_ty: ToTy, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { let from_ty = value.ty(); @@ -1002,7 +909,7 @@ impl<'a> Exporter<'a> { &mut self, firrtl_cast_fn: Option<&str>, value: Expr, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { let value = self.expr(Expr::canonical(value), definitions, const_ty)?; @@ -1016,7 +923,7 @@ impl<'a> Exporter<'a> { &mut self, base: Expr, range: Range, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { let base_width = base.ty().width(); @@ -1034,95 +941,73 @@ impl<'a> Exporter<'a> { fn array_literal_expr( &mut self, expr: ops::ArrayLiteral, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { - definitions.get_or_write_definition( - (expr, const_ty), - |c| &c.array_literal_exprs, - |definitions, &(expr, const_ty)| { - let ident = self.module.ns.make_new("_array_literal_expr"); - let ty_str = self.type_state.ty(expr.ty())?; - let const_ = if const_ty { "const " } else { "" }; - definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_str}")); - for (index, element) in expr.element_values().into_iter().enumerate() { - let element = self.expr(Expr::canonical(element), &definitions, const_ty)?; - definitions - .add_definition_line(format_args!("connect {ident}[{index}], {element}")); - } - if expr.element_values().is_empty() { - definitions.add_definition_line(format_args!("invalidate {ident}")); - } - Ok(ident.to_string()) - }, - ) + let ident = self.module.ns.make_new("_array_literal_expr"); + let ty_str = self.type_state.ty(expr.ty())?; + let const_ = if const_ty { "const " } else { "" }; + definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_str}")); + for (index, element) in expr.element_values().into_iter().enumerate() { + let element = self.expr(Expr::canonical(element), definitions, const_ty)?; + definitions.add_definition_line(format_args!("connect {ident}[{index}], {element}")); + } + if expr.element_values().is_empty() { + definitions.add_definition_line(format_args!("invalidate {ident}")); + } + Ok(ident.to_string()) } fn bundle_literal_expr( &mut self, expr: ops::BundleLiteral, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { - definitions.get_or_write_definition( - (expr, const_ty), - |c| &c.bundle_literal_exprs, - |definitions, &(expr, const_ty)| { - let ident = self.module.ns.make_new("_bundle_literal_expr"); - let ty = expr.ty(); - let (ty_ident, bundle_ns) = self.type_state.bundle_def(ty)?; - let const_ = if const_ty { "const " } else { "" }; - definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_ident}")); - for ( - field_value, - BundleField { - name, - flipped, - ty: _, - }, - ) in expr.field_values().into_iter().zip(ty.fields()) - { - debug_assert!( - !flipped, - "can't have bundle literal with flipped field -- \ - this should have been caught in BundleLiteral::new_unchecked" - ); - let name = bundle_ns.borrow_mut().get(name); - let field_value = - self.expr(Expr::canonical(field_value), &definitions, const_ty)?; - definitions - .add_definition_line(format_args!("connect {ident}.{name}, {field_value}")); - } - if ty.fields().is_empty() { - definitions.add_definition_line(format_args!("invalidate {ident}")); - } - Ok(ident.to_string()) + let ident = self.module.ns.make_new("_bundle_literal_expr"); + let ty = expr.ty(); + let (ty_ident, bundle_ns) = self.type_state.bundle_def(ty)?; + let const_ = if const_ty { "const " } else { "" }; + definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_ident}")); + for ( + field_value, + BundleField { + name, + flipped, + ty: _, }, - ) + ) in expr.field_values().into_iter().zip(ty.fields()) + { + debug_assert!( + !flipped, + "can't have bundle literal with flipped field -- this should have been caught in BundleLiteral::new_unchecked" + ); + let name = bundle_ns.borrow_mut().get(name); + let field_value = self.expr(Expr::canonical(field_value), definitions, const_ty)?; + definitions.add_definition_line(format_args!("connect {ident}.{name}, {field_value}")); + } + if ty.fields().is_empty() { + definitions.add_definition_line(format_args!("invalidate {ident}")); + } + Ok(ident.to_string()) } fn uninit_expr( &mut self, expr: ops::Uninit, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { - definitions.get_or_write_definition( - (expr, const_ty), - |c| &c.uninit_exprs, - |definitions, &(expr, const_ty)| { - let ident = self.module.ns.make_new("_uninit_expr"); - let ty = expr.ty(); - let ty_ident = self.type_state.ty(ty)?; - let const_ = if const_ty { "const " } else { "" }; - definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_ident}")); - definitions.add_definition_line(format_args!("invalidate {ident}")); - Ok(ident.to_string()) - }, - ) + let ident = self.module.ns.make_new("_uninit_expr"); + let ty = expr.ty(); + let ty_ident = self.type_state.ty(ty)?; + let const_ = if const_ty { "const " } else { "" }; + definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_ident}")); + definitions.add_definition_line(format_args!("invalidate {ident}")); + Ok(ident.to_string()) } fn enum_literal_expr( &mut self, expr: ops::EnumLiteral, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { let variant_expr = expr @@ -1135,201 +1020,178 @@ impl<'a> Exporter<'a> { &mut self, value_str: String, ty: Bundle, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_bundle_to_bits_exprs, - |definitions, &(ref value_str, ty)| { - if ty.fields().is_empty() { - return Ok("UInt<0>(0)".into()); - } - if let [field] = *ty.fields() { - let field_ident = self.type_state.get_bundle_field(ty, field.name)?; - return self.expr_cast_to_bits( - format!("{value_str}.{field_ident}"), - field.ty, - &definitions, - extra_indent, - ); - } - let flattened_bundle_ty = Bundle::new(Interned::from_iter(ty.fields().iter().map( - |&BundleField { - name, - flipped: _, - ty: field_ty, - }| BundleField { - name, - flipped: false, - ty: UInt[field_ty.bit_width()].canonical(), - }, - ))); - let (flattened_ty_ident, _) = self.type_state.bundle_def(flattened_bundle_ty)?; - let ident = self.module.ns.make_new("_cast_bundle_to_bits_expr"); - definitions.add_definition_line(format_args!( - "{extra_indent}wire {ident}: {flattened_ty_ident}" - )); - let mut cat_expr = None; - for field in ty.fields() { - let field_ident = self.type_state.get_bundle_field(ty, field.name)?; - let flattened_field_ident = self - .type_state - .get_bundle_field(flattened_bundle_ty, field.name)?; - let field_bits = self.expr_cast_to_bits( - format!("{value_str}.{field_ident}"), - field.ty, - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {ident}.{flattened_field_ident}, {field_bits}" - )); - cat_expr = Some(if let Some(cat_expr) = cat_expr { - format!("cat({ident}.{flattened_field_ident}, {cat_expr})") - } else { - format!("{ident}.{flattened_field_ident}") - }); - } - let retval = self.module.ns.make_new("_cast_to_bits_expr"); - definitions.add_definition_line(format_args!( - "{extra_indent}wire {retval}: UInt<{}>", - ty.type_properties().bit_width - )); - let cat_expr = cat_expr.expect("bundle already checked to have fields"); - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, {cat_expr}" - )); - Ok(retval.to_string()) + if ty.fields().is_empty() { + return Ok("UInt<0>(0)".into()); + } + if let [field] = *ty.fields() { + let field_ident = self.type_state.get_bundle_field(ty, field.name)?; + return self.expr_cast_to_bits( + format!("{value_str}.{field_ident}"), + field.ty, + definitions, + extra_indent, + ); + } + let flattened_bundle_ty = Bundle::new(Interned::from_iter(ty.fields().iter().map( + |&BundleField { + name, + flipped: _, + ty: field_ty, + }| BundleField { + name, + flipped: false, + ty: UInt[field_ty.bit_width()].canonical(), }, - ) + ))); + let (flattened_ty_ident, _) = self.type_state.bundle_def(flattened_bundle_ty)?; + let ident = self.module.ns.make_new("_cast_bundle_to_bits_expr"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {ident}: {flattened_ty_ident}" + )); + let mut cat_expr = None; + for field in ty.fields() { + let field_ident = self.type_state.get_bundle_field(ty, field.name)?; + let flattened_field_ident = self + .type_state + .get_bundle_field(flattened_bundle_ty, field.name)?; + let field_bits = self.expr_cast_to_bits( + format!("{value_str}.{field_ident}"), + field.ty, + definitions, + extra_indent, + )?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {ident}.{flattened_field_ident}, {field_bits}" + )); + cat_expr = Some(if let Some(cat_expr) = cat_expr { + format!("cat({ident}.{flattened_field_ident}, {cat_expr})") + } else { + format!("{ident}.{flattened_field_ident}") + }); + } + let retval = self.module.ns.make_new("_cast_to_bits_expr"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {retval}: UInt<{}>", + ty.type_properties().bit_width + )); + let cat_expr = cat_expr.expect("bundle already checked to have fields"); + definitions.add_definition_line(format_args!("{extra_indent}connect {retval}, {cat_expr}")); + Ok(retval.to_string()) } fn expr_cast_enum_to_bits( &mut self, value_str: String, ty: Enum, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_enum_to_bits_exprs, - |definitions, &(ref value_str, ty)| { - if ty.variants().is_empty() { - return Ok("UInt<0>(0)".into()); - } - let retval = self.module.ns.make_new("_cast_enum_to_bits_expr"); + if ty.variants().is_empty() { + return Ok("UInt<0>(0)".into()); + } + let retval = self.module.ns.make_new("_cast_enum_to_bits_expr"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {retval}: UInt<{}>", + ty.type_properties().bit_width + )); + definitions.add_definition_line(format_args!("{extra_indent}match {value_str}:")); + let _match_arms_indent = extra_indent.push(); + for (variant_index, variant) in ty.variants().into_iter().enumerate() { + if let Some(variant_ty) = variant.ty { + let variant_value = self + .module + .ns + .make_new(&format!("_cast_enum_to_bits_expr_{}", variant.name)); definitions.add_definition_line(format_args!( - "{extra_indent}wire {retval}: UInt<{}>", - ty.type_properties().bit_width + "{extra_indent}{}({variant_value}):", + self.type_state.get_enum_variant(ty, variant.name)?, )); - definitions.add_definition_line(format_args!("{extra_indent}match {value_str}:")); - let _match_arms_indent = extra_indent.push(); - for (variant_index, variant) in ty.variants().into_iter().enumerate() { - if let Some(variant_ty) = variant.ty { - let variant_value = self - .module - .ns - .make_new(&format!("_cast_enum_to_bits_expr_{}", variant.name)); - definitions.add_definition_line(format_args!( - "{extra_indent}{}({variant_value}):", - self.type_state.get_enum_variant(ty, variant.name)?, - )); - let _match_arm_indent = extra_indent.push(); - let variant_bits = self.expr_cast_to_bits( - variant_value.to_string(), - variant_ty, - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, \ - pad(cat({variant_bits}, UInt<{}>({variant_index})), {})", - ty.discriminant_bit_width(), - ty.type_properties().bit_width, - )); - } else { - definitions.add_definition_line(format_args!( - "{extra_indent}{}:", - self.type_state.get_enum_variant(ty, variant.name)?, - )); - let _match_arm_indent = extra_indent.push(); - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, UInt<{}>({variant_index})", - ty.type_properties().bit_width, - )); - } - } - Ok(retval.to_string()) - }, - ) + let _match_arm_indent = extra_indent.push(); + let variant_bits = self.expr_cast_to_bits( + variant_value.to_string(), + variant_ty, + definitions, + extra_indent, + )?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}, pad(cat({variant_bits}, UInt<{}>({variant_index})), {})", + ty.discriminant_bit_width(), + ty.type_properties().bit_width, + )); + } else { + definitions.add_definition_line(format_args!( + "{extra_indent}{}:", + self.type_state.get_enum_variant(ty, variant.name)?, + )); + let _match_arm_indent = extra_indent.push(); + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}, UInt<{}>({variant_index})", + ty.type_properties().bit_width, + )); + } + } + Ok(retval.to_string()) } fn expr_cast_array_to_bits( &mut self, value_str: String, ty: Array, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_array_to_bits_exprs, - |definitions, &(ref value_str, ty)| { - if ty.is_empty() { - return Ok("UInt<0>(0)".into()); - } - if ty.len() == 1 { - return self.expr_cast_to_bits( - value_str.clone() + "[0]", - ty.element(), - &definitions, - extra_indent, - ); - } - let element_width = ty.element().bit_width(); - let ident = self.module.ns.make_new("_cast_array_to_bits_expr"); - definitions.add_definition_line(format_args!( - "{extra_indent}wire {ident}: UInt<{element_width}>[{}]", - ty.len(), - )); - let mut cat_expr = None; - for index in 0..ty.len() { - let element_bits = self.expr_cast_to_bits( - format!("{value_str}[{index}]"), - ty.element(), - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {ident}[{index}], {element_bits}" - )); - cat_expr = Some(if let Some(cat_expr) = cat_expr { - format!("cat({ident}[{index}], {cat_expr})") - } else { - format!("{ident}[{index}]") - }); - } - let retval = self.module.ns.make_new("_cast_to_bits_expr"); - definitions.add_definition_line(format_args!( - "{extra_indent}wire {retval}: UInt<{}>", - ty.type_properties().bit_width - )); - let cat_expr = cat_expr.expect("array already checked to have elements"); - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, {cat_expr}" - )); - Ok(retval.to_string()) - }, - ) + if ty.is_empty() { + return Ok("UInt<0>(0)".into()); + } + if ty.len() == 1 { + return self.expr_cast_to_bits( + value_str + "[0]", + ty.element(), + definitions, + extra_indent, + ); + } + let element_width = ty.element().bit_width(); + let ident = self.module.ns.make_new("_cast_array_to_bits_expr"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {ident}: UInt<{element_width}>[{}]", + ty.len(), + )); + let mut cat_expr = None; + for index in 0..ty.len() { + let element_bits = self.expr_cast_to_bits( + format!("{value_str}[{index}]"), + ty.element(), + definitions, + extra_indent, + )?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {ident}[{index}], {element_bits}" + )); + cat_expr = Some(if let Some(cat_expr) = cat_expr { + format!("cat({ident}[{index}], {cat_expr})") + } else { + format!("{ident}[{index}]") + }); + } + let retval = self.module.ns.make_new("_cast_to_bits_expr"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {retval}: UInt<{}>", + ty.type_properties().bit_width + )); + let cat_expr = cat_expr.expect("array already checked to have elements"); + definitions.add_definition_line(format_args!("{extra_indent}connect {retval}, {cat_expr}")); + Ok(retval.to_string()) } fn expr_cast_to_bits( &mut self, value_str: String, ty: CanonicalType, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - match ty.unwrap_transparent_types() { + match ty { CanonicalType::Bundle(ty) => { self.expr_cast_bundle_to_bits(value_str, ty, definitions, extra_indent) } @@ -1348,240 +1210,204 @@ impl<'a> Exporter<'a> { | CanonicalType::Reset(_) => Ok(format!("asUInt({value_str})")), CanonicalType::PhantomConst(_) => Ok("UInt<0>(0)".into()), CanonicalType::DynSimOnly(_) => Err(FirrtlError::SimOnlyValuesAreNotPermitted.into()), - CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), } } fn expr_cast_bits_to_bundle( &mut self, value_str: String, ty: Bundle, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_bits_to_bundle_exprs, - |definitions, &(ref value_str, ty)| { - let (ty_ident, _) = self.type_state.bundle_def(ty)?; - let retval = self.module.ns.make_new("_cast_bits_to_bundle_expr"); - definitions - .add_definition_line(format_args!("{extra_indent}wire {retval}: {ty_ident}")); - if ty.fields().is_empty() { - definitions - .add_definition_line(format_args!("{extra_indent}invalidate {retval}")); - return Ok(retval.to_string()); - } - let flattened_bundle_ty = Bundle::new(Interned::from_iter(ty.fields().iter().map( - |&BundleField { - name, - flipped: _, - ty: field_ty, - }| BundleField { - name, - flipped: false, - ty: UInt[field_ty.bit_width()].canonical(), - }, - ))); - let (flattened_ty_ident, _) = self.type_state.bundle_def(flattened_bundle_ty)?; - let flattened_ident = self - .module - .ns - .make_new("_cast_bits_to_bundle_expr_flattened"); + let (ty_ident, _) = self.type_state.bundle_def(ty)?; + let retval = self.module.ns.make_new("_cast_bits_to_bundle_expr"); + definitions.add_definition_line(format_args!("{extra_indent}wire {retval}: {ty_ident}")); + if ty.fields().is_empty() { + definitions.add_definition_line(format_args!("{extra_indent}invalidate {retval}")); + return Ok(retval.to_string()); + } + let flattened_bundle_ty = Bundle::new(Interned::from_iter(ty.fields().iter().map( + |&BundleField { + name, + flipped: _, + ty: field_ty, + }| BundleField { + name, + flipped: false, + ty: UInt[field_ty.bit_width()].canonical(), + }, + ))); + let (flattened_ty_ident, _) = self.type_state.bundle_def(flattened_bundle_ty)?; + let flattened_ident = self + .module + .ns + .make_new("_cast_bits_to_bundle_expr_flattened"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {flattened_ident}: {flattened_ty_ident}" + )); + for ( + field, + OpaqueSimValueSize { + bit_width: field_offset, + sim_only_values_len: _, + }, + ) in ty.fields().into_iter().zip(ty.field_offsets()) + { + let flattened_field_ident = self + .type_state + .get_bundle_field(flattened_bundle_ty, field.name)?; + let field_ident = self.type_state.get_bundle_field(ty, field.name)?; + if let Some(field_bit_width_minus_one) = field.ty.bit_width().checked_sub(1usize) { definitions.add_definition_line(format_args!( - "{extra_indent}wire {flattened_ident}: {flattened_ty_ident}" + "{extra_indent}connect {flattened_ident}.{flattened_field_ident}, bits({value_str}, {}, {field_offset})", + field_offset + field_bit_width_minus_one )); - for ( - field, - OpaqueSimValueSize { - bit_width: field_offset, - sim_only_values_len: _, - }, - ) in ty.fields().into_iter().zip(ty.field_offsets()) - { - let flattened_field_ident = self - .type_state - .get_bundle_field(flattened_bundle_ty, field.name)?; - let field_ident = self.type_state.get_bundle_field(ty, field.name)?; - if let Some(field_bit_width_minus_one) = - field.ty.bit_width().checked_sub(1usize) - { - definitions.add_definition_line(format_args!( - "{extra_indent}connect {flattened_ident}.{flattened_field_ident}, \ - bits({value_str}, {}, {field_offset})", - field_offset + field_bit_width_minus_one - )); - } else { - definitions.add_definition_line(format_args!( + } else { + definitions.add_definition_line(format_args!( "{extra_indent}connect {flattened_ident}.{flattened_field_ident}, UInt<0>(0)" )); - } - let field_value = self.expr_cast_bits_to( - format!("{flattened_ident}.{flattened_field_ident}"), - field.ty, - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}.{field_ident}, {field_value}" - )); - } - Ok(retval.to_string()) - }, - ) + } + let field_value = self.expr_cast_bits_to( + format!("{flattened_ident}.{flattened_field_ident}"), + field.ty, + definitions, + extra_indent, + )?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}.{field_ident}, {field_value}" + )); + } + Ok(retval.to_string()) } fn expr_cast_bits_to_enum( &mut self, value_str: String, ty: Enum, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_bits_to_enum_exprs, - |definitions, &(ref value_str, ty)| { - let (ty_ident, enum_def) = self.type_state.enum_def(ty)?; - let retval = self.module.ns.make_new("_cast_bits_to_enum_expr"); + let (ty_ident, enum_def) = self.type_state.enum_def(ty)?; + let retval = self.module.ns.make_new("_cast_bits_to_enum_expr"); + definitions.add_definition_line(format_args!("{extra_indent}wire {retval}: {ty_ident}")); + if ty.variants().is_empty() { + definitions.add_definition_line(format_args!("{extra_indent}invalidate {retval}")); + return Ok(retval.to_string()); + } + if let [variant] = *ty.variants() { + let enum_variant = self.type_state.get_enum_variant(ty, variant.name)?; + if let Some(variant_ty) = variant.ty { + let variant_value = + self.expr_cast_bits_to(value_str, variant_ty, definitions, extra_indent)?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}, {}({enum_variant}, {variant_value})", + enum_def.body + )); + } else { + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}, {}({enum_variant})", + enum_def.body + )); + } + return Ok(retval.to_string()); + } + let discriminant_bit_width = ty.discriminant_bit_width(); + let body_bit_width = ty.type_properties().bit_width - discriminant_bit_width; + let body_ident = self.module.ns.make_new("_cast_bits_to_enum_expr_body"); + let body_value = if body_bit_width != 0 { + definitions.add_definition_line(format_args!( + "{extra_indent}wire {body_ident}: UInt<{body_bit_width}>" + )); + definitions.add_definition_line(format_args!( + "{extra_indent}connect {body_ident}, head({value_str}, {body_bit_width})" + )); + body_ident.to_string() + } else { + "UInt<0>(0)".into() + }; + for (variant_index, variant) in ty.variants().into_iter().enumerate() { + let when_cond = format!( + "eq(UInt<{discriminant_bit_width}>({variant_index}), tail({value_str}, {body_bit_width}))" + ); + if variant_index == ty.variants().len() - 1 { + definitions.add_definition_line(format_args!("{extra_indent}else:")); + } else if variant_index == 0 { + definitions.add_definition_line(format_args!("{extra_indent}when {when_cond}:")); + } else { definitions - .add_definition_line(format_args!("{extra_indent}wire {retval}: {ty_ident}")); - if ty.variants().is_empty() { - definitions - .add_definition_line(format_args!("{extra_indent}invalidate {retval}")); - return Ok(retval.to_string()); - } - if let [variant] = *ty.variants() { - let enum_variant = self.type_state.get_enum_variant(ty, variant.name)?; - if let Some(variant_ty) = variant.ty { - let variant_value = self.expr_cast_bits_to( - value_str.clone(), - variant_ty, - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, {}({enum_variant}, {variant_value})", - enum_def.body - )); - } else { - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, {}({enum_variant})", - enum_def.body - )); - } - return Ok(retval.to_string()); - } - let discriminant_bit_width = ty.discriminant_bit_width(); - let body_bit_width = ty.type_properties().bit_width - discriminant_bit_width; - let body_ident = self.module.ns.make_new("_cast_bits_to_enum_expr_body"); - let body_value = if body_bit_width != 0 { - definitions.add_definition_line(format_args!( - "{extra_indent}wire {body_ident}: UInt<{body_bit_width}>" - )); - definitions.add_definition_line(format_args!( - "{extra_indent}connect {body_ident}, head({value_str}, {body_bit_width})" - )); - body_ident.to_string() - } else { - "UInt<0>(0)".into() - }; - for (variant_index, variant) in ty.variants().into_iter().enumerate() { - let when_cond = format!( - "eq(UInt<{discriminant_bit_width}>({variant_index}), \ - tail({value_str}, {body_bit_width}))" - ); - if variant_index == ty.variants().len() - 1 { - definitions.add_definition_line(format_args!("{extra_indent}else:")); - } else if variant_index == 0 { - definitions - .add_definition_line(format_args!("{extra_indent}when {when_cond}:")); - } else { - definitions.add_definition_line(format_args!( - "{extra_indent}else when {when_cond}:" - )); - } - let when_pushed_indent = extra_indent.push(); - let enum_variant = self.type_state.get_enum_variant(ty, variant.name)?; - if let Some(variant_ty) = variant.ty { - let variant_value = self.expr_cast_bits_to( - body_value.clone(), - variant_ty, - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, {}({enum_variant}, {variant_value})", - enum_def.body - )); - } else { - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}, {}({enum_variant})", - enum_def.body - )); - } - drop(when_pushed_indent); - } - Ok(retval.to_string()) - }, - ) + .add_definition_line(format_args!("{extra_indent}else when {when_cond}:")); + } + let when_pushed_indent = extra_indent.push(); + let enum_variant = self.type_state.get_enum_variant(ty, variant.name)?; + if let Some(variant_ty) = variant.ty { + let variant_value = self.expr_cast_bits_to( + body_value.clone(), + variant_ty, + definitions, + extra_indent, + )?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}, {}({enum_variant}, {variant_value})", + enum_def.body + )); + } else { + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}, {}({enum_variant})", + enum_def.body + )); + } + drop(when_pushed_indent); + } + Ok(retval.to_string()) } fn expr_cast_bits_to_array( &mut self, value_str: String, ty: Array, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_bits_to_array_exprs, - |definitions, &(ref value_str, ty)| { - let retval = self.module.ns.make_new("_cast_bits_to_array_expr"); - let array_ty = self.type_state.ty(ty)?; - definitions - .add_definition_line(format_args!("{extra_indent}wire {retval}: {array_ty}")); - let element_bit_width = ty.element().bit_width(); - if ty.is_empty() || element_bit_width == 0 { - definitions - .add_definition_line(format_args!("{extra_indent}invalidate {retval}")); - return Ok(retval.to_string()); - } - let flattened_ident = self - .module - .ns - .make_new("_cast_bits_to_array_expr_flattened"); - definitions.add_definition_line(format_args!( - "{extra_indent}wire {flattened_ident}: UInt<{element_bit_width}>[{}]", - ty.len(), - )); - for index in 0..ty.len() { - definitions.add_definition_line(format_args!( - "{extra_indent}connect {flattened_ident}[{index}], \ - bits({value_str}, {}, {})", - element_bit_width * index + element_bit_width - 1, - element_bit_width * index, - )); - let element_value = self.expr_cast_bits_to( - format!("{flattened_ident}[{index}]"), - ty.element(), - &definitions, - extra_indent, - )?; - definitions.add_definition_line(format_args!( - "{extra_indent}connect {retval}[{index}], {element_value}" - )); - } - Ok(retval.to_string()) - }, - ) + let retval = self.module.ns.make_new("_cast_bits_to_array_expr"); + let array_ty = self.type_state.ty(ty)?; + definitions.add_definition_line(format_args!("{extra_indent}wire {retval}: {array_ty}")); + let element_bit_width = ty.element().bit_width(); + if ty.is_empty() || element_bit_width == 0 { + definitions.add_definition_line(format_args!("{extra_indent}invalidate {retval}")); + return Ok(retval.to_string()); + } + let flattened_ident = self + .module + .ns + .make_new("_cast_bits_to_array_expr_flattened"); + definitions.add_definition_line(format_args!( + "{extra_indent}wire {flattened_ident}: UInt<{element_bit_width}>[{}]", + ty.len(), + )); + for index in 0..ty.len() { + definitions.add_definition_line(format_args!( + "{extra_indent}connect {flattened_ident}[{index}], bits({value_str}, {}, {})", + element_bit_width * index + element_bit_width - 1, + element_bit_width * index, + )); + let element_value = self.expr_cast_bits_to( + format!("{flattened_ident}[{index}]"), + ty.element(), + definitions, + extra_indent, + )?; + definitions.add_definition_line(format_args!( + "{extra_indent}connect {retval}[{index}], {element_value}" + )); + } + Ok(retval.to_string()) } fn expr_cast_bits_to( &mut self, value_str: String, ty: CanonicalType, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, extra_indent: Indent<'_>, ) -> Result { - match ty.unwrap_transparent_types() { + match ty { CanonicalType::Bundle(ty) => { self.expr_cast_bits_to_bundle(value_str, ty, definitions, extra_indent) } @@ -1598,27 +1424,20 @@ impl<'a> Exporter<'a> { CanonicalType::AsyncReset(_) => Ok(format!("asAsyncReset({value_str})")), CanonicalType::SyncReset(_) => Ok(value_str), CanonicalType::Reset(_) => unreachable!("Reset is not bit castable to"), - CanonicalType::PhantomConst(ty) => definitions.get_or_write_definition( - (value_str, ty), - |c| &c.cast_bits_to_phantom_const_exprs, - |definitions, &(ref _value_str, _ty)| { - let retval = self.module.ns.make_new("_cast_bits_to_phantom_const_expr"); - definitions - .add_definition_line(format_args!("{extra_indent}wire {retval}: {{}}")); - definitions - .add_definition_line(format_args!("{extra_indent}invalidate {retval}")); - Ok(retval.to_string()) - }, - ), + CanonicalType::PhantomConst(_) => { + let retval = self.module.ns.make_new("_cast_bits_to_phantom_const_expr"); + definitions.add_definition_line(format_args!("{extra_indent}wire {retval}: {{}}")); + definitions.add_definition_line(format_args!("{extra_indent}invalidate {retval}")); + return Ok(retval.to_string()); + } CanonicalType::DynSimOnly(_) => Err(FirrtlError::SimOnlyValuesAreNotPermitted.into()), - CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), } } fn expr_unary( &mut self, func: &str, arg: Expr, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { Ok(format!( @@ -1631,7 +1450,7 @@ impl<'a> Exporter<'a> { func: &str, lhs: Expr, rhs: Expr, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { Ok(format!( @@ -1640,144 +1459,10 @@ impl<'a> Exporter<'a> { rhs = self.expr(Expr::canonical(rhs), definitions, const_ty)?, )) } - #[hdl] - fn expr_formal_input(&mut self, formal_input: FormalInput, const_ty: bool) -> Result { - let definitions = self.module.block_definitions.clone(); - definitions.get_or_write_definition( - (formal_input, const_ty), - |c| &c.per_module_formal_inputs, - |definitions, &(formal_input, const_ty)| match formal_input.kind() { - FormalInputKind::FormalGlobalClock => { - let reg = Reg::new_unchecked( - ScopedNameId(self.module.module.name_id().into(), formal_input.name_id()), - formal_input.source_location(), - Bool, - #[hdl] - ClockDomain { - clk: false.to_clock(), - rst: false.to_sync_reset(), - }, - None, - ); - let module_name = self.global_ns.get(self.module.module.name_id()); - self.targeted_annotations( - module_name, - vec![], - &Vec::from_iter( - [ - SVAttributeAnnotation { - text: "gclk".intern(), - } - .into_annotations(), - DontTouchAnnotation.into_annotations(), - ] - .into_annotations() - .map(|a| { - TargetedAnnotation::new( - Target::from(reg.canonical()).intern_sized(), - a, - ) - }), - ), - )?; - definitions.add_definition_line(self.reg(reg.canonical(), &definitions)?); - self.expr( - Expr::canonical(reg.to_expr().to_clock()), - &definitions, - const_ty, - ) - } - FormalInputKind::FormalReset => { - #[hdl_module(extern)] - fn formal_reset() { - #[hdl] - let rst: SyncReset = m.output(); - m.annotate_module(BlackBoxInlineAnnotation { - path: "fayalite_formal_reset.v".intern(), - text: r"module __fayalite_formal_reset(output rst); - assign rst = $initstate; -endmodule -" - .intern(), - }); - m.verilog_name("__fayalite_formal_reset"); - } - static MOD: OnceLock>> = OnceLock::new(); - let formal_reset = Instance::new_unchecked( - ScopedNameId(self.module.module.name_id().into(), formal_input.name_id()), - *MOD.get_or_init(|| { - let module = formal_reset(); - let Ok(module) = ResetSourceLocation.fold_module(*module); - module.intern_sized() - }), - formal_input.source_location(), - ); - definitions.add_definition_line(self.instance(formal_reset.canonical())?); - self.expr( - Expr::canonical(formal_reset.to_expr().rst), - &definitions, - const_ty, - ) - } - FormalInputKind::AnyConst - | FormalInputKind::AnySeq - | FormalInputKind::AllConst - | FormalInputKind::AllSeq => { - match formal_input.ty() { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) => {} - _ => panic!( - "{}() -- unsupported type: {formal_input:#?}", - formal_input.name() - ), - } - if formal_input.ty().size().is_empty() { - return self.expr(formal_input.ty().uninit(), &definitions, const_ty); - } - let reg = Reg::new_unchecked( - ScopedNameId(self.module.module.name_id().into(), formal_input.name_id()), - formal_input.source_location(), - formal_input.ty(), - #[hdl] - ClockDomain { - clk: false.to_clock(), - rst: false.to_sync_reset(), - }, - None, - ); - let module_name = self.global_ns.get(self.module.module.name_id()); - self.targeted_annotations( - module_name, - vec![], - &Vec::from_iter( - [ - SVAttributeAnnotation { - text: match formal_input.kind() { - FormalInputKind::AnyConst => "anyconst".intern(), - FormalInputKind::AnySeq => "anyseq".intern(), - FormalInputKind::AllConst => "allconst".intern(), - FormalInputKind::AllSeq => "allseq".intern(), - _ => unreachable!(), - }, - } - .into_annotations(), - DontTouchAnnotation.into_annotations(), - ] - .into_annotations() - .map(|a| TargetedAnnotation::new(Target::from(reg).intern_sized(), a)), - ), - )?; - definitions.add_definition_line(self.reg(reg, &definitions)?); - self.expr(Expr::canonical(reg.to_expr()), &definitions, const_ty) - } - }, - ) - } fn expr( &mut self, expr: Expr, - definitions: &BlockDefinitions<'_>, + definitions: &RcDefinitions, const_ty: bool, ) -> Result { match *Expr::expr_enum(expr) { @@ -2113,10 +1798,6 @@ endmodule write!(out, "[{index}]").unwrap(); Ok(out) } - ExprEnum::ToTraceAsString(expr) => self.expr(expr.inner(), definitions, const_ty), - ExprEnum::TraceAsStringAsInner(expr) => { - self.expr(Expr::canonical(expr.arg()), definitions, const_ty) - } ExprEnum::ModuleIO(expr) => Ok(self.module.ns.get(expr.name_id()).to_string()), ExprEnum::Instance(expr) => { assert!(!const_ty, "not a constant"); @@ -2144,10 +1825,6 @@ endmodule let port_name = Ident::from(expr.port_name()); Ok(format!("{mem_name}.{port_name}")) } - ExprEnum::FormalInput(expr) => self.expr_formal_input(expr, const_ty), - ExprEnum::SimIoForGlobal(_) => { - unreachable!("Module is known to not contain SimIoForGlobal from validation") - } } } fn write_mem_init( @@ -2262,9 +1939,6 @@ endmodule TargetBase::RegAsync(v) => self.module.ns.get(v.name_id()), TargetBase::Wire(v) => self.module.ns.get(v.name_id()), TargetBase::Instance(v) => self.module.ns.get(v.name_id()), - TargetBase::FormalInput(_) | TargetBase::SimIoForGlobal(_) => { - unreachable!("base.is_valid_annotation_target() is known to be false") - } }; Ok(AnnotationTargetRef { base, segments }) } @@ -2283,10 +1957,6 @@ endmodule .segments .push(AnnotationTargetRefSegment::Index { index }), TargetPathElement::DynArrayElement(_) => unreachable!(), - TargetPathElement::ToTraceAsString(_) - | TargetPathElement::TraceAsStringInner(_) => { - // ignored - } } Ok(retval) } @@ -2376,60 +2046,47 @@ endmodule drop(memory_indent); Ok(body) } - fn reg( + fn stmt_reg( &mut self, - reg: Reg, - definitions: &BlockDefinitions<'_>, - ) -> Result { + stmt_reg: StmtReg, + module_name: Ident, + definitions: &RcDefinitions, + body: &mut String, + ) -> Result<()> { + let StmtReg { annotations, reg } = stmt_reg; + let indent = self.indent; + self.targeted_annotations(module_name, vec![], &annotations)?; let name = self.module.ns.get(reg.name_id()); let ty = self.type_state.ty(reg.ty())?; let clk = self.expr(Expr::canonical(reg.clock_domain().clk), definitions, false)?; if let Some(init) = reg.init() { let rst = self.expr(Expr::canonical(reg.clock_domain().rst), definitions, false)?; let init = self.expr(init, definitions, false)?; - Ok(format!( - "regreset {name}: {ty}, {clk}, {rst}, {init}{}", + writeln!( + body, + "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}", FileInfo::new(reg.source_location()), - )) + ) + .unwrap(); } else { - Ok(format!( - "reg {name}: {ty}, {clk}{}", + writeln!( + body, + "{indent}reg {name}: {ty}, {clk}{}", FileInfo::new(reg.source_location()), - )) + ) + .unwrap(); } - } - fn stmt_reg( - &mut self, - stmt_reg: StmtReg, - module_name: Ident, - definitions: &BlockDefinitions<'_>, - body: &mut String, - ) -> Result<()> { - let StmtReg { annotations, reg } = stmt_reg; - let indent = self.indent; - self.targeted_annotations(module_name, vec![], &annotations)?; - writeln!(body, "{indent}{}", self.reg(reg, definitions)?).unwrap(); Ok(()) } - fn instance(&mut self, instance: Instance) -> Result { - let name = self.module.ns.get(instance.name_id()); - let instantiated = instance.instantiated(); - self.add_module(instantiated); - let module_name = self.global_ns.get(instantiated.name_id()); - Ok(format!( - "inst {name} of {module_name}{}", - FileInfo::new(instance.source_location()), - )) - } fn block( &mut self, module: Interned>, block: Block, _block_indent: &PushIndent<'_>, - parent_definitions: &BlockDefinitions, + definitions: Option, ) -> Result { let indent = self.indent; - let definitions = BlockDefinitions::new(parent_definitions); + let definitions = definitions.unwrap_or_default(); let mut body = String::new(); let mut out = String::new(); let Block { memories, stmts } = block; @@ -2506,7 +2163,7 @@ endmodule .unwrap(); pushed_indent = indent.push(); let then_block_str = - self.block(module, then_block, &pushed_indent, &definitions)?; + self.block(module, then_block, &pushed_indent, None)?; if !then_block_str.is_empty() { body.push_str(&then_block_str); } else { @@ -2524,8 +2181,7 @@ endmodule break; } } - let else_block = - self.block(module, else_block, &pushed_indent, &definitions)?; + let else_block = self.block(module, else_block, &pushed_indent, None)?; drop(pushed_indent); if !else_block.is_empty() { writeln!(body, "{indent}else:").unwrap(); @@ -2568,8 +2224,7 @@ endmodule }; body.push_str(":\n"); let match_arm_indent = indent.push(); - let block = - self.block(module, match_arm_block, &match_arm_indent, &definitions)?; + let block = self.block(module, match_arm_block, &match_arm_indent, None)?; if !block.is_empty() { body.push_str(&block); } else { @@ -2607,18 +2262,26 @@ endmodule instance, })) => { self.targeted_annotations(module_name, vec![], &annotations)?; - writeln!(body, "{indent}{}", self.instance(instance)?).unwrap(); + let name = self.module.ns.get(instance.name_id()); + let instantiated = instance.instantiated(); + self.add_module(instantiated); + let module_name = self.global_ns.get(instantiated.name_id()); + writeln!( + body, + "{indent}inst {name} of {module_name}{}", + FileInfo::new(instance.source_location()), + ) + .unwrap(); } } - definitions.write_out(indent, &mut out); + definitions.write_and_clear(indent, &mut out); out.push_str(&body); body.clear(); } Ok(out) } fn module(&mut self, module: Interned>) -> Result { - self.module = ModuleState::new(module); - let module_definitions = self.module.block_definitions.clone(); + self.module = ModuleState::default(); let indent = self.indent; let module_name = self.global_ns.get(module.name_id()); let mut body = String::new(); @@ -2687,10 +2350,12 @@ endmodule "extmodule" } ModuleBody::Normal(NormalModuleBody { body: top_block }) => { - let body_str = - self.block(module, top_block, &module_indent, &module_definitions)?; - module_definitions.write_out(indent, &mut body); - body.push_str(&body_str); + body.push_str(&self.block( + module, + top_block, + &module_indent, + Some(self.module.definitions.clone()), + )?); "module" } }; @@ -3037,7 +2702,7 @@ fn export_impl( seen_modules: HashSet::default(), unwritten_modules: VecDeque::new(), global_ns, - module: ModuleState::new(top_module), + module: ModuleState::default(), type_state: TypeState::default(), circuit_name, annotations: vec![], @@ -3546,8 +3211,6 @@ impl ScalarizeTreeNode { TargetPathElement::DynArrayElement(_) => { unreachable!("annotations are only on static targets"); } - TargetPathElement::ToTraceAsString(_) - | TargetPathElement::TraceAsStringInner(_) => parent, } } } @@ -3674,13 +3337,6 @@ impl ScalarizeTreeBuilder { CanonicalType::DynSimOnly(_) => { return Err(ScalarizedModuleABIError::SimOnlyValuesAreNotPermitted); } - CanonicalType::TraceAsString(_) => self.build( - target - .join(TargetPathElement::intern_sized( - TargetPathTraceAsStringInner {}.into(), - )) - .intern_sized(), - )?, }) } } diff --git a/crates/fayalite/src/formal.rs b/crates/fayalite/src/formal.rs index 77ef808..17d3122 100644 --- a/crates/fayalite/src/formal.rs +++ b/crates/fayalite/src/formal.rs @@ -1,189 +1,11 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information use crate::{ - expr::target::{GetTarget, Target}, int::BoolOrIntType, - intern::{Intern, Interned}, - module::{NameId, NameIdOrGlobal, ScopedNameId}, + intern::{Intern, Interned, Memoize}, prelude::*, }; -use std::{fmt, sync::OnceLock}; - -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] -pub enum FormalInputKind { - FormalGlobalClock, - FormalReset, - AnyConst, - AnySeq, - AllConst, - AllSeq, -} - -impl FormalInputKind { - pub fn fixed_ty(self) -> Option { - match self { - Self::FormalGlobalClock => Some(Clock.into()), - Self::FormalReset => Some(SyncReset.into()), - Self::AnyConst => None, - Self::AnySeq => None, - Self::AllConst => None, - Self::AllSeq => None, - } - } - pub fn fixed_id(self) -> Option { - struct Cache { - formal_global_clock: crate::module::Id, - formal_reset: crate::module::Id, - } - static CACHE: OnceLock = OnceLock::new(); - let cache = || { - CACHE.get_or_init( - #[cold] - || Cache { - formal_global_clock: crate::module::Id::new(), - formal_reset: crate::module::Id::new(), - }, - ) - }; - match self { - Self::FormalGlobalClock => Some(cache().formal_global_clock), - Self::FormalReset => Some(cache().formal_reset), - Self::AnyConst => None, - Self::AnySeq => None, - Self::AllConst => None, - Self::AllSeq => None, - } - } - pub fn fixed_source_location(self) -> Option { - match self { - Self::FormalGlobalClock | Self::FormalReset => Some(SourceLocation::builtin()), - Self::AnyConst | Self::AnySeq | Self::AllConst | Self::AllSeq => None, - } - } - pub fn name(self) -> &'static str { - match self { - Self::FormalGlobalClock => "formal_global_clock", - Self::FormalReset => "formal_reset", - Self::AnyConst => "any_const", - Self::AnySeq => "any_seq", - Self::AllConst => "all_const", - Self::AllSeq => "all_seq", - } - } - pub fn interned_name(self) -> Interned { - macro_rules! impl_interned_name { - ($($variant:ident,)*) => { - match self { - $(Self::$variant => { - static CACHE: OnceLock> = OnceLock::new(); - *CACHE.get_or_init(|| Self::$variant.name().intern()) - })* - } - }; - } - impl_interned_name! { - FormalGlobalClock, - FormalReset, - AnyConst, - AnySeq, - AllConst, - AllSeq, - } - } -} - -#[derive(Clone, PartialEq, Eq, Hash)] -struct FormalInputData { - kind: FormalInputKind, - name_id: NameId, - ty: CanonicalType, - source_location: SourceLocation, -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash)] -pub struct FormalInput(Interned); - -impl fmt::Debug for FormalInput { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - if self.kind().fixed_ty().is_some() { - f.write_str(&self.name()) - } else { - f.debug_tuple(&self.name()).field(&self.0.ty).finish() - } - } -} - -impl FormalInput { - #[track_caller] - pub fn new( - kind: FormalInputKind, - name_id: NameId, - ty: CanonicalType, - source_location: SourceLocation, - ) -> Self { - let NameId(name, id) = name_id; - assert_eq!(kind.interned_name(), name); - if let Some(fixed_ty) = kind.fixed_ty() { - assert_eq!(ty, fixed_ty); - } else { - assert!( - ty.is_castable_from_bits(), - "{name} type must be castable from bits. got:\n{ty:#?}", - ); - } - if let Some(fixed_source_location) = kind.fixed_source_location() { - assert_eq!(source_location, fixed_source_location); - } - if let Some(fixed_id) = kind.fixed_id() { - assert_eq!(id, fixed_id); - } - Self( - FormalInputData { - kind, - name_id, - ty, - source_location, - } - .intern_sized(), - ) - } - pub fn kind(self) -> FormalInputKind { - self.0.kind - } - pub fn name(self) -> Interned { - self.0.name_id.0 - } - pub fn name_id(self) -> NameId { - self.0.name_id - } - pub fn scoped_name(self) -> ScopedNameId { - ScopedNameId(NameIdOrGlobal::Global, self.name_id()) - } - pub fn source_location(self) -> SourceLocation { - self.0.source_location - } - pub(crate) fn must_connect_to(self) -> bool { - false - } - pub(crate) fn flow(self) -> crate::expr::Flow { - crate::expr::Flow::Source - } -} - -impl ValueType for FormalInput { - type Type = CanonicalType; - type ValueCategory = crate::expr::value_category::ValueCategoryExpr; - - fn ty(&self) -> Self::Type { - self.0.ty - } -} - -impl GetTarget for FormalInput { - fn target(&self) -> Option> { - Some(Target::from(*self).intern_sized()) - } -} +use std::sync::OnceLock; #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)] pub enum FormalKind { @@ -316,76 +138,110 @@ make_formal!( hdl_cover ); +pub trait MakeFormalExpr: Type {} + +impl MakeFormalExpr for T {} + #[hdl] pub fn formal_global_clock() -> Expr { - static CACHE: OnceLock> = OnceLock::new(); - *CACHE.get_or_init(|| { - let kind = FormalInputKind::FormalGlobalClock; - Expr::from_canonical( - FormalInput::new( - kind, - NameId( - kind.interned_name(), - kind.fixed_id().expect("known to have a fixed Id"), - ), - Clock.into(), - kind.fixed_source_location() - .expect("known to have a fixed SourceLocation"), - ) - .to_expr(), - ) - }) + #[hdl_module(extern)] + fn formal_global_clock() { + #[hdl] + let clk: Clock = m.output(); + m.annotate_module(BlackBoxInlineAnnotation { + path: "fayalite_formal_global_clock.v".intern(), + text: r"module __fayalite_formal_global_clock(output clk); + (* gclk *) + reg clk; +endmodule +" + .intern(), + }); + m.verilog_name("__fayalite_formal_global_clock"); + } + #[hdl] + let formal_global_clock = instance(formal_global_clock()); + formal_global_clock.clk } #[hdl] pub fn formal_reset() -> Expr { - static CACHE: OnceLock> = OnceLock::new(); - *CACHE.get_or_init(|| { - let kind = FormalInputKind::FormalReset; - Expr::from_canonical( - FormalInput::new( - kind, - NameId( - kind.interned_name(), - kind.fixed_id().expect("known to have a fixed Id"), - ), - SyncReset.into(), - kind.fixed_source_location() - .expect("known to have a fixed SourceLocation"), - ) - .to_expr(), - ) - }) + #[hdl_module(extern)] + fn formal_reset() { + #[hdl] + let rst: SyncReset = m.output(); + m.annotate_module(BlackBoxInlineAnnotation { + path: "fayalite_formal_reset.v".intern(), + text: r"module __fayalite_formal_reset(output rst); + assign rst = $initstate; +endmodule +" + .intern(), + }); + m.verilog_name("__fayalite_formal_reset"); + } + static MOD: OnceLock>> = OnceLock::new(); + #[hdl] + let formal_reset = instance(*MOD.get_or_init(formal_reset)); + formal_reset.rst } macro_rules! make_any_const_fn { - ($ident:ident, $ident_with_loc:ident, $verilog_attribute:literal, $kind:ident) => { - #[track_caller] + ($ident:ident, $verilog_attribute:literal) => { #[hdl] pub fn $ident(ty: T) -> Expr { - $ident_with_loc(ty, SourceLocation::caller()) - } - #[track_caller] - #[hdl] - pub fn $ident_with_loc( - ty: T, - source_location: SourceLocation, - ) -> Expr { - let kind = FormalInputKind::$kind; - Expr::from_canonical( - FormalInput::new( - kind, - NameId(kind.interned_name(), crate::module::Id::new()), - ty.canonical(), - source_location, - ) - .to_expr(), - ) + #[hdl_module(extern)] + pub(super) fn $ident(ty: T) { + #[hdl] + let out: T = m.output(ty); + let width = ty.width(); + let verilog_bitslice = if width == 1 { + String::new() + } else { + format!(" [{}:0]", width - 1) + }; + m.annotate_module(BlackBoxInlineAnnotation { + path: Intern::intern_owned(format!( + "fayalite_{}_{width}.v", + stringify!($ident), + )), + text: Intern::intern_owned(format!( + r"module __fayalite_{}_{width}(output{verilog_bitslice} out); + (* {} *) + reg{verilog_bitslice} out; +endmodule +", + stringify!($ident), + $verilog_attribute, + )), + }); + m.verilog_name(format!("__fayalite_{}_{width}", stringify!($ident))); + } + #[derive(Copy, Clone, PartialEq, Eq, Hash)] + struct TheMemoize(T); + impl Memoize for TheMemoize { + type Input = (); + type InputOwned = (); + type Output = Option>>>; + fn inner(self, _input: &Self::Input) -> Self::Output { + if self.0.width() == 0 { + None + } else { + Some($ident(self.0)) + } + } + } + let Some(module) = TheMemoize(ty).get_owned(()) else { + return 0_hdl_u0.cast_bits_to(ty); + }; + #[hdl] + let $ident = instance(module); + $ident.out } }; } -make_any_const_fn!(any_const, any_const_with_loc, "anyconst", AnyConst); -make_any_const_fn!(any_seq, any_seq_with_loc, "anyseq", AnySeq); -make_any_const_fn!(all_const, all_const_with_loc, "allconst", AllConst); -make_any_const_fn!(all_seq, all_seq_with_loc, "allseq", AllSeq); +make_any_const_fn!(any_const, "anyconst"); +make_any_const_fn!(any_seq, "anyseq"); +make_any_const_fn!(all_const, "allconst"); +make_any_const_fn!(all_seq, "allseq"); diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs index 15f8ed1..c461306 100644 --- a/crates/fayalite/src/int.rs +++ b/crates/fayalite/src/int.rs @@ -15,8 +15,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, FillInDefaultedGenerics, OpaqueSimValueSize, OpaqueSimValueSlice, - OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, SimValueDisplay, StaticType, - Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, util::{ConstBool, ConstUsize, GenericConstBool, GenericConstUsize, interned_bit, slice_range}, }; @@ -1019,24 +1019,6 @@ macro_rules! impl_int { } } - impl SimValueDebug for $name { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } - } - - impl SimValueDisplay for $name { - fn sim_value_display( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Display::fmt(value, f) - } - } - impl Default for $name { fn default() -> Self { Self::TYPE @@ -1277,9 +1259,6 @@ macro_rules! impl_int { pub fn bitvec_mut(&mut self) -> &mut BitVec { Arc::make_mut(&mut self.bits) } - pub fn arc_bitvec_mut(&mut self) -> &mut Arc { - &mut self.bits - } } }; } @@ -1920,15 +1899,6 @@ impl Type for Bool { } } -impl SimValueDebug for Bool { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl StaticType for Bool { const TYPE: Self = Bool; const MASK_TYPE: Self::MaskType = Bool; diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs index edf2e25..acf2fec 100644 --- a/crates/fayalite/src/int/uint_in_range.rs +++ b/crates/fayalite/src/int/uint_in_range.rs @@ -14,7 +14,7 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, - SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self, + StaticType, Type, TypeProperties, impl_match_variant_as_self, }, }; use bitvec::{order::Lsb0, view::BitView}; @@ -94,15 +94,6 @@ impl Type for UIntInRangeMaskType { } } -impl SimValueDebug for UIntInRangeMaskType { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl BundleType for UIntInRangeMaskType { type Builder = NoBuilder; @@ -348,15 +339,6 @@ macro_rules! define_uint_in_range_type { } } - impl SimValueDebug for $UIntInRangeType { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } - } - impl fmt::Debug for $UIntInRangeType { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { value, range } = self; diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs index 89cc53d..b78aa59 100644 --- a/crates/fayalite/src/intern.rs +++ b/crates/fayalite/src/intern.rs @@ -682,62 +682,27 @@ impl, U: ?Sized> AsRef for Inter #[derive(Clone, Debug)] pub struct InternedSliceIter { - iter: std::iter::Cloned>, -} - -impl Default for InternedSliceIter { - fn default() -> Self { - Self { - iter: [].iter().cloned(), - } - } + slice: Interned<[T]>, + index: std::ops::Range, } impl Iterator for InternedSliceIter { type Item = T; fn next(&mut self) -> Option { - self.iter.next() + self.index.next().map(|index| self.slice[index].clone()) } fn size_hint(&self) -> (usize, Option) { - self.iter.size_hint() - } - - fn count(self) -> usize { - self.iter.count() - } - - fn last(mut self) -> Option { - self.next_back() - } - - fn nth(&mut self, n: usize) -> Option { - self.iter.nth(n) - } - - fn fold(self, init: B, f: F) -> B - where - F: FnMut(B, Self::Item) -> B, - { - self.iter.fold(init, f) + self.index.size_hint() } } impl DoubleEndedIterator for InternedSliceIter { fn next_back(&mut self) -> Option { - self.iter.next_back() - } - - fn nth_back(&mut self, n: usize) -> Option { - self.iter.nth_back(n) - } - - fn rfold(self, init: B, f: F) -> B - where - F: FnMut(B, Self::Item) -> B, - { - self.iter.rfold(init, f) + self.index + .next_back() + .map(|index| self.slice[index].clone()) } } @@ -751,7 +716,8 @@ impl IntoIterator for Interned<[T]> { fn into_iter(self) -> Self::IntoIter { InternedSliceIter { - iter: Interned::into_inner(self).iter().cloned(), + index: 0..self.len(), + slice: self, } } } diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs index b3af13c..83e7437 100644 --- a/crates/fayalite/src/memory.rs +++ b/crates/fayalite/src/memory.rs @@ -1093,7 +1093,6 @@ pub fn splat_mask(ty: T, value: Expr) -> Expr> { .to_expr(), )), CanonicalType::PhantomConst(_) => Expr::from_canonical(Expr::canonical(().to_expr())), - CanonicalType::TraceAsString(ty) => Expr::from_canonical(splat_mask(ty.inner_ty(), value)), } } diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs index 2535694..d959182 100644 --- a/crates/fayalite/src/module.rs +++ b/crates/fayalite/src/module.rs @@ -8,7 +8,7 @@ use crate::{ clock::{Clock, ClockDomain}, enum_::{Enum, EnumMatchVariantsIter, EnumType}, expr::{ - Expr, ExprEnum, Flow, ToExpr, ValueType, + Expr, Flow, ToExpr, ValueType, ops::VariantAccess, target::{ GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, @@ -20,7 +20,6 @@ use crate::{ int::{Bool, DynSize, Size}, intern::{Intern, Interned}, memory::{Mem, MemBuilder, MemBuilderTarget, PortName}, - module::transform::visit::{Visit, Visitor}, platform::PlatformIOBuilder, reg::Reg, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, @@ -727,57 +726,7 @@ impl fmt::Display for NameId { } #[derive(Copy, Clone, Eq, PartialEq, Hash)] -pub enum NameIdOrGlobal { - Global, - NameId(NameId), -} - -impl NameIdOrGlobal { - pub fn name_id(self) -> Option { - match self { - Self::Global => None, - Self::NameId(v) => Some(v), - } - } - #[track_caller] - pub fn assert_is_name_id(self) { - match self { - Self::Global => panic!("expected a NameId, got NameIdOrGlobal::Global"), - Self::NameId(_) => {} - } - } - #[track_caller] - pub fn unwrap_name_id(self) -> NameId { - match self { - Self::Global => panic!("expected a NameId, got NameIdOrGlobal::Global"), - Self::NameId(v) => v, - } - } -} - -impl fmt::Debug for NameIdOrGlobal { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Display::fmt(self, f) - } -} - -impl fmt::Display for NameIdOrGlobal { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self { - Self::Global => f.write_str("<>"), - Self::NameId(name_id) => fmt::Display::fmt(name_id, f), - } - } -} - -impl From for NameIdOrGlobal { - fn from(value: NameId) -> Self { - Self::NameId(value) - } -} - -#[derive(Copy, Clone, Eq, PartialEq, Hash)] -pub struct ScopedNameId(pub NameIdOrGlobal, pub NameId); +pub struct ScopedNameId(pub NameId, pub NameId); impl fmt::Debug for ScopedNameId { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { @@ -855,7 +804,7 @@ impl Instance { self.containing_module_name_id().0 } pub fn containing_module_name_id(self) -> NameId { - self.scoped_name.0.unwrap_name_id() + self.scoped_name.0 } pub fn name(self) -> Interned { self.name_id().0 @@ -872,13 +821,11 @@ impl Instance { pub fn source_location(self) -> SourceLocation { self.source_location } - #[track_caller] pub fn new_unchecked( scoped_name: ScopedNameId, instantiated: Interned>, source_location: SourceLocation, ) -> Self { - scoped_name.0.assert_is_name_id(); Self { scoped_name, instantiated, @@ -1164,10 +1111,7 @@ fn validate_clock_for_past( let mut target = clock_for_past; while let Target::Child(child) = target { match *child.path_element() { - TargetPathElement::BundleField(_) - | TargetPathElement::ArrayElement(_) - | TargetPathElement::ToTraceAsString(_) - | TargetPathElement::TraceAsStringInner(_) => {} + TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} TargetPathElement::DynArrayElement(_) => { panic!( "clock_for_past: clock must be a static target (you can't use `Expr` array indexes):\n{clock_for_past:?}" @@ -1591,7 +1535,6 @@ impl TargetState { } } fn new(target: Interned, declared_in_block: usize) -> Self { - let target = Target::unwrap_transparent_types_interned(target); Self { target, inner: match target.canonical_ty() { @@ -1643,71 +1586,17 @@ impl TargetState { declared_in_block, written_in_blocks: RefCell::default(), }, - CanonicalType::TraceAsString(_) => { - unreachable!("handled by Target::unwrap_transparent_types_interned") - } }, } } } -struct VisibleExprsStack { - buf: Vec>, - len: usize, -} - -impl VisibleExprsStack { - fn top(&mut self) -> &mut HashSet { - &mut self.buf[self.len - 1] - } - fn slice(&self) -> &[HashSet] { - &self.buf[..self.len] - } - fn contains(&self, v: &ExprEnum) -> bool { - self.slice().iter().any(|i| i.contains(v)) - } - fn push_empty(&mut self) { - #[cold] - fn push_empty_cold(stack: &mut VisibleExprsStack) { - stack.buf.push(HashSet::default()); - assert_eq!(stack.buf.len(), stack.len) - } - self.len += 1; - if self.len > self.buf.len() { - push_empty_cold(self) - } - } - fn pop(&mut self) { - let Some(new_len) = self.len.checked_sub(1) else { - unreachable!("visible exprs stack underflow"); - }; - self.buf[new_len].clear(); - self.len = new_len; - } -} - -impl Default for VisibleExprsStack { - fn default() -> Self { - Self { - buf: Vec::new(), - len: 0, - } - } -} - struct AssertValidityState { module: Module, blocks: Vec, - visible_exprs: VisibleExprsStack, target_states: HashMap, TargetState>, } -enum GetTargetStatesError { - NotFound, - IsGlobal, - FoundSimIoForGlobal(crate::expr::ops::SimIoForGlobal), -} - impl AssertValidityState { fn make_block_index(&mut self, block: Block) -> usize { let retval = self.blocks.len(); @@ -1716,79 +1605,48 @@ impl AssertValidityState { } fn get_target_states<'a>( &'a self, - target: Target, + target: &Target, process_target_state: &dyn Fn(&'a TargetState, bool), - ) -> Result<(), GetTargetStatesError> { - let mut target = target.unwrap_transparent_types(); - loop { - break match target { - Target::Base(target_base) => { - let target_state = self.get_base_state(target_base)?; - process_target_state(target_state, false); - Ok(()) - } - Target::Child(target_child) => match *target_child.path_element() { - TargetPathElement::BundleField(_) - | TargetPathElement::ArrayElement(_) - | TargetPathElement::DynArrayElement(_) => self.get_target_states( - *target_child.parent(), - &|target_state, exact_target_unknown| { - let TargetStateInner::Decomposed { subtargets } = &target_state.inner - else { - unreachable!( - "TargetState::new makes TargetState tree match the Target type" - ); - }; - match *target_child.path_element() { - TargetPathElement::BundleField(_) => process_target_state( - subtargets - .get(&target_child.path_element()) - .expect("bundle fields filled in by TargetState::new"), - exact_target_unknown, - ), - TargetPathElement::ArrayElement(_) => process_target_state( - subtargets - .get(&target_child.path_element()) - .expect("array elements filled in by TargetState::new"), - exact_target_unknown, - ), - TargetPathElement::DynArrayElement(_) => { - for target_state in subtargets.values() { - process_target_state(target_state, true); - } - } - TargetPathElement::TraceAsStringInner(_) - | TargetPathElement::ToTraceAsString(_) => unreachable!(), + ) -> Result<(), ()> { + match target { + Target::Base(target_base) => { + let target_state = self.get_base_state(*target_base)?; + process_target_state(target_state, false); + Ok(()) + } + Target::Child(target_child) => self.get_target_states( + &target_child.parent(), + &|target_state, exact_target_unknown| { + let TargetStateInner::Decomposed { subtargets } = &target_state.inner else { + unreachable!( + "TargetState::new makes TargetState tree match the Target type" + ); + }; + match *target_child.path_element() { + TargetPathElement::BundleField(_) => process_target_state( + subtargets + .get(&target_child.path_element()) + .expect("bundle fields filled in by TargetState::new"), + exact_target_unknown, + ), + TargetPathElement::ArrayElement(_) => process_target_state( + subtargets + .get(&target_child.path_element()) + .expect("array elements filled in by TargetState::new"), + exact_target_unknown, + ), + TargetPathElement::DynArrayElement(_) => { + for target_state in subtargets.values() { + process_target_state(target_state, true); } - }, - ), - TargetPathElement::TraceAsStringInner(_) - | TargetPathElement::ToTraceAsString(_) => { - target = *target_child.parent(); - continue; + } } }, - }; + ), } } - fn get_base_state( - &self, - target_base: Interned, - ) -> Result<&TargetState, GetTargetStatesError> { - match *target_base { - TargetBase::ModuleIO(_) - | TargetBase::MemPort(_) - | TargetBase::Reg(_) - | TargetBase::RegSync(_) - | TargetBase::RegAsync(_) - | TargetBase::Wire(_) - | TargetBase::Instance(_) => self - .target_states - .get(&target_base) - .ok_or(GetTargetStatesError::NotFound), - TargetBase::FormalInput(_) => Err(GetTargetStatesError::IsGlobal), - TargetBase::SimIoForGlobal(v) => Err(GetTargetStatesError::FoundSimIoForGlobal(v)), - } + fn get_base_state(&self, target_base: Interned) -> Result<&TargetState, ()> { + self.target_states.get(&target_base).ok_or(()) } #[track_caller] fn insert_new_base(&mut self, target_base: Interned, declared_in_block: usize) { @@ -1835,7 +1693,6 @@ impl AssertValidityState { &TargetPathElement::BundleField(_) => { let field = sub_target_state .target - .without_trailing_transparent_path_elements() .child() .expect("known to be a child") .bundle_field() @@ -1859,8 +1716,6 @@ impl AssertValidityState { TargetPathElement::DynArrayElement { .. } => { Self::set_connect_target_written(sub_target_state, is_lhs, block, true); } - TargetPathElement::TraceAsStringInner(_) - | TargetPathElement::ToTraceAsString(_) => unreachable!("never added"), } } } @@ -1878,33 +1733,19 @@ impl AssertValidityState { debug_assert!(!is_lhs, "the ModuleBuilder asserts lhs.target().is_some()"); return; }; - let result = self.get_target_states(*target, &|target_state, exact_target_unknown| { + let result = self.get_target_states(&target, &|target_state, exact_target_unknown| { Self::set_connect_target_written(target_state, is_lhs, block, exact_target_unknown); }); - match result { - Ok(()) => {} - Err(GetTargetStatesError::NotFound) => { - if is_lhs { - panic!( - "at {source_location}: tried to connect to not-yet-defined item: {target}" - ); - } else { - panic!( - "at {source_location}: tried to connect from not-yet-defined item: {target}" - ); - } - } - Err(GetTargetStatesError::IsGlobal) => { - // no error - } - Err(GetTargetStatesError::FoundSimIoForGlobal(v)) => { + if result.is_err() { + if is_lhs { + panic!("at {source_location}: tried to connect to not-yet-defined item: {target}"); + } else { panic!( - "at {source_location}: fayalite::expr::ops::SimIoForGlobal is not allowed in Modules: {v:?}" - ) + "at {source_location}: tried to connect from not-yet-defined item: {target}" + ); } } } - #[track_caller] fn process_conditional_sub_blocks( &mut self, parent_block: usize, @@ -1918,40 +1759,17 @@ impl AssertValidityState { } } #[track_caller] - fn assert_expr_validity(&mut self, expr: Expr, source_location: SourceLocation) { - let mut visitor = AssertExprValidity { state: self }; - match visitor.visit_expr(&expr) { - Ok(()) => {} - Err(e) => match e { - InvalidExpr::ExprIsNotVisible(expr) => { - if let Some(target) = expr.target() { - panic!( - "at {source_location}: expression isn't visible here, it's defined:\n\ - at {}: {expr:?}", - target.base().source_location(), - ); - } else { - panic!("at {source_location}: expression isn't visible here: {expr:?}"); - } - } - }, - } - } - #[track_caller] fn assert_subtree_validity(&mut self, block: usize) { - self.visible_exprs.push_empty(); let module = self.module; if block == 0 { for module_io in &*module.module_io { self.insert_new_base(TargetBase::intern_sized(module_io.module_io.into()), block); - self.visible_exprs.top().insert(module_io.module_io.into()); } } let Block { memories, stmts } = self.blocks[block]; for m in memories { for port in m.ports() { self.insert_new_base(TargetBase::intern_sized(port.into()), block); - self.visible_exprs.top().insert(port.into()); } } for stmt in stmts { @@ -1965,104 +1783,44 @@ impl AssertValidityState { } = connect; self.set_connect_side_written(lhs, source_location, true, block); self.set_connect_side_written(rhs, source_location, false, block); - self.assert_expr_validity(lhs, source_location); - self.assert_expr_validity(rhs, source_location); - } - Stmt::Formal(formal) => { - let StmtFormal { - kind: _, - clk, - pred, - en, - text: _, - source_location, - } = formal; - self.assert_expr_validity(clk, source_location); - self.assert_expr_validity(pred, source_location); - self.assert_expr_validity(en, source_location); } + Stmt::Formal(_) => {} Stmt::If(if_stmt) => { - let StmtIf { - cond, - source_location, - blocks: sub_blocks, - } = if_stmt; - self.assert_expr_validity(cond, source_location); - let sub_blocks = sub_blocks.map(|block| self.make_block_index(block)); + let sub_blocks = if_stmt.blocks.map(|block| self.make_block_index(block)); self.process_conditional_sub_blocks(block, sub_blocks) } Stmt::Match(match_stmt) => { match_stmt.assert_validity(); - let StmtMatch { - expr, - source_location, - blocks: sub_blocks, - } = match_stmt; - self.assert_expr_validity(expr, source_location); let sub_blocks = Vec::from_iter( - sub_blocks + match_stmt + .blocks .into_iter() .map(|block| self.make_block_index(block)), ); - self.visible_exprs.push_empty(); - let visible_exprs_top = self.visible_exprs.top(); - for variant_index in 0..expr.ty().variants().len() { - visible_exprs_top - .insert(::new_by_index(expr, variant_index).into()); - } - self.process_conditional_sub_blocks(block, sub_blocks.iter().copied()); - self.visible_exprs.pop(); + self.process_conditional_sub_blocks(block, sub_blocks.iter().copied()) } Stmt::Declaration(StmtDeclaration::Wire(StmtWire { annotations: _, wire, - })) => { - self.insert_new_base(TargetBase::intern_sized(wire.into()), block); - self.visible_exprs.top().insert(wire.into()); - } + })) => self.insert_new_base(TargetBase::intern_sized(wire.into()), block), Stmt::Declaration(StmtDeclaration::Reg(StmtReg { annotations: _, reg, - })) => { - self.assert_expr_validity(reg.clock_domain(), reg.source_location()); - if let Some(init) = reg.init() { - self.assert_expr_validity(init, reg.source_location()); - } - self.insert_new_base(TargetBase::intern_sized(reg.into()), block); - self.visible_exprs.top().insert(reg.into()); - } + })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block), Stmt::Declaration(StmtDeclaration::RegSync(StmtReg { annotations: _, reg, - })) => { - self.assert_expr_validity(reg.clock_domain(), reg.source_location()); - if let Some(init) = reg.init() { - self.assert_expr_validity(init, reg.source_location()); - } - self.insert_new_base(TargetBase::intern_sized(reg.into()), block); - self.visible_exprs.top().insert(reg.into()); - } + })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block), Stmt::Declaration(StmtDeclaration::RegAsync(StmtReg { annotations: _, reg, - })) => { - self.assert_expr_validity(reg.clock_domain(), reg.source_location()); - if let Some(init) = reg.init() { - self.assert_expr_validity(init, reg.source_location()); - } - self.insert_new_base(TargetBase::intern_sized(reg.into()), block); - self.visible_exprs.top().insert(reg.into()); - } + })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block), Stmt::Declaration(StmtDeclaration::Instance(StmtInstance { annotations: _, instance, - })) => { - self.insert_new_base(TargetBase::intern_sized(instance.into()), block); - self.visible_exprs.top().insert(instance.into()); - } + })) => self.insert_new_base(TargetBase::intern_sized(instance.into()), block), } } - self.visible_exprs.pop(); } #[track_caller] fn assert_validity(&mut self) { @@ -2091,142 +1849,6 @@ impl AssertValidityState { } } -struct AssertExprValidity<'a> { - state: &'a mut AssertValidityState, -} - -enum InvalidExpr { - ExprIsNotVisible(Expr), -} - -impl transform::visit::Visitor for AssertExprValidity<'_> { - type Error = InvalidExpr; - fn visit_expr_enum(&mut self, v: &ExprEnum) -> Result<(), Self::Error> { - match v { - ExprEnum::UIntLiteral(_) - | ExprEnum::SIntLiteral(_) - | ExprEnum::BoolLiteral(_) - | ExprEnum::PhantomConst(_) - | ExprEnum::BundleLiteral(_) - | ExprEnum::ArrayLiteral(_) - | ExprEnum::EnumLiteral(_) - | ExprEnum::Uninit(_) - | ExprEnum::NotU(_) - | ExprEnum::NotS(_) - | ExprEnum::NotB(_) - | ExprEnum::Neg(_) - | ExprEnum::BitAndU(_) - | ExprEnum::BitAndS(_) - | ExprEnum::BitAndB(_) - | ExprEnum::BitOrU(_) - | ExprEnum::BitOrS(_) - | ExprEnum::BitOrB(_) - | ExprEnum::BitXorU(_) - | ExprEnum::BitXorS(_) - | ExprEnum::BitXorB(_) - | ExprEnum::AddU(_) - | ExprEnum::AddS(_) - | ExprEnum::SubU(_) - | ExprEnum::SubS(_) - | ExprEnum::MulU(_) - | ExprEnum::MulS(_) - | ExprEnum::DivU(_) - | ExprEnum::DivS(_) - | ExprEnum::RemU(_) - | ExprEnum::RemS(_) - | ExprEnum::DynShlU(_) - | ExprEnum::DynShlS(_) - | ExprEnum::DynShrU(_) - | ExprEnum::DynShrS(_) - | ExprEnum::FixedShlU(_) - | ExprEnum::FixedShlS(_) - | ExprEnum::FixedShrU(_) - | ExprEnum::FixedShrS(_) - | ExprEnum::CmpLtB(_) - | ExprEnum::CmpLeB(_) - | ExprEnum::CmpGtB(_) - | ExprEnum::CmpGeB(_) - | ExprEnum::CmpEqB(_) - | ExprEnum::CmpNeB(_) - | ExprEnum::CmpLtU(_) - | ExprEnum::CmpLeU(_) - | ExprEnum::CmpGtU(_) - | ExprEnum::CmpGeU(_) - | ExprEnum::CmpEqU(_) - | ExprEnum::CmpNeU(_) - | ExprEnum::CmpLtS(_) - | ExprEnum::CmpLeS(_) - | ExprEnum::CmpGtS(_) - | ExprEnum::CmpGeS(_) - | ExprEnum::CmpEqS(_) - | ExprEnum::CmpNeS(_) - | ExprEnum::CastUIntToUInt(_) - | ExprEnum::CastUIntToSInt(_) - | ExprEnum::CastSIntToUInt(_) - | ExprEnum::CastSIntToSInt(_) - | ExprEnum::CastBoolToUInt(_) - | ExprEnum::CastBoolToSInt(_) - | ExprEnum::CastUIntToBool(_) - | ExprEnum::CastSIntToBool(_) - | ExprEnum::CastBoolToSyncReset(_) - | ExprEnum::CastUIntToSyncReset(_) - | ExprEnum::CastSIntToSyncReset(_) - | ExprEnum::CastBoolToAsyncReset(_) - | ExprEnum::CastUIntToAsyncReset(_) - | ExprEnum::CastSIntToAsyncReset(_) - | ExprEnum::CastSyncResetToBool(_) - | ExprEnum::CastSyncResetToUInt(_) - | ExprEnum::CastSyncResetToSInt(_) - | ExprEnum::CastSyncResetToReset(_) - | ExprEnum::CastAsyncResetToBool(_) - | ExprEnum::CastAsyncResetToUInt(_) - | ExprEnum::CastAsyncResetToSInt(_) - | ExprEnum::CastAsyncResetToReset(_) - | ExprEnum::CastResetToBool(_) - | ExprEnum::CastResetToUInt(_) - | ExprEnum::CastResetToSInt(_) - | ExprEnum::CastBoolToClock(_) - | ExprEnum::CastUIntToClock(_) - | ExprEnum::CastSIntToClock(_) - | ExprEnum::CastClockToBool(_) - | ExprEnum::CastClockToUInt(_) - | ExprEnum::CastClockToSInt(_) - | ExprEnum::FieldAccess(_) - | ExprEnum::ArrayIndex(_) - | ExprEnum::DynArrayIndex(_) - | ExprEnum::ReduceBitAndU(_) - | ExprEnum::ReduceBitAndS(_) - | ExprEnum::ReduceBitOrU(_) - | ExprEnum::ReduceBitOrS(_) - | ExprEnum::ReduceBitXorU(_) - | ExprEnum::ReduceBitXorS(_) - | ExprEnum::SliceUInt(_) - | ExprEnum::SliceSInt(_) - | ExprEnum::CastToBits(_) - | ExprEnum::CastBitsTo(_) - | ExprEnum::ToTraceAsString(_) - | ExprEnum::TraceAsStringAsInner(_) - | ExprEnum::FormalInput(_) => v.default_visit(self), - ExprEnum::VariantAccess(_) - | ExprEnum::ModuleIO(_) - | ExprEnum::Instance(_) - | ExprEnum::Wire(_) - | ExprEnum::Reg(_) - | ExprEnum::RegSync(_) - | ExprEnum::RegAsync(_) - | ExprEnum::MemPort(_) => { - if self.state.visible_exprs.contains(v) { - // no need to visit inner expressions, we already checked them before adding them to visible_exprs - Ok(()) - } else { - Err(InvalidExpr::ExprIsNotVisible(v.to_expr())) - } - } - ExprEnum::SimIoForGlobal(_) => Err(InvalidExpr::ExprIsNotVisible(v.to_expr())), - } - } -} - impl Module { /// you generally should use the [`#[hdl_module]`][`crate::hdl_module`] proc-macro and [`ModuleBuilder`] instead #[track_caller] @@ -2352,7 +1974,6 @@ impl Module { AssertValidityState { module: self.canonical(), blocks: vec![], - visible_exprs: VisibleExprsStack::default(), target_states: HashMap::with_capacity_and_hasher(64, Default::default()), } .assert_validity(); @@ -2458,7 +2079,7 @@ impl RegBuilder>, Option>, T> ty, } = self; ModuleBuilder::with(|module_builder| { - let scoped_name = ScopedNameId(module_builder.name.into(), NameId(name, Id::new())); + let scoped_name = ScopedNameId(module_builder.name, NameId(name, Id::new())); let reg = Reg::new_unchecked(scoped_name, source_location, ty, clock_domain, init); let retval = reg.to_expr(); // convert before borrow_mut since ModuleBuilder could be reentered by T::canonical() @@ -2854,9 +2475,6 @@ pub fn annotate(target: Expr, annotations: impl IntoAnnotations) { instance, } .into(), - TargetBase::FormalInput(_) | TargetBase::SimIoForGlobal(_) => { - unreachable!("not a valid annotation target") - } }; ModuleBuilder::with(|m| { unwrap!(m.impl_.borrow_mut().body.builder_normal_body_opt()) @@ -2871,7 +2489,7 @@ pub fn annotate(target: Expr, annotations: impl IntoAnnotations) { #[track_caller] pub fn wire_with_loc(name: &str, source_location: SourceLocation, ty: T) -> Expr { ModuleBuilder::with(|m| { - let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new())); + let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new())); let wire = Wire::::new_unchecked(scoped_name, source_location, ty); let retval = wire.to_expr(); let canonical_wire = wire.canonical(); @@ -2903,7 +2521,7 @@ fn incomplete_declaration( source_location: SourceLocation, ) -> Rc> { ModuleBuilder::with(|m| { - let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new())); + let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new())); let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete { name: scoped_name, source_location, @@ -3079,7 +2697,7 @@ pub fn instance_with_loc( source_location: SourceLocation, ) -> Expr { ModuleBuilder::with(|m| { - let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new())); + let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new())); let instance = Instance:: { scoped_name, instantiated, @@ -3118,7 +2736,7 @@ fn memory_impl( source_location: SourceLocation, ) -> MemBuilder { ModuleBuilder::with(|m| { - let scoped_name = ScopedNameId(m.name.into(), NameId(name.intern(), Id::new())); + let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new())); let (retval, target_mem) = MemBuilder::new(scoped_name, source_location, mem_element_type); let mut impl_ = m.impl_.borrow_mut(); let body = impl_.body.builder_normal_body(); @@ -3273,7 +2891,7 @@ impl ModuleIO { NameId(self.bundle_field.name, self.id) } pub fn scoped_name(&self) -> ScopedNameId { - ScopedNameId(self.containing_module_name.into(), self.name_id()) + ScopedNameId(self.containing_module_name, self.name_id()) } pub fn source_location(&self) -> SourceLocation { self.source_location @@ -3346,102 +2964,10 @@ impl fmt::Debug for InstantiatedModule { } } -#[derive(PartialEq, Eq, Hash, Clone, Copy)] -pub enum InstantiatedModuleOrGlobal { - Global, - InstantiatedModule(InstantiatedModule), -} - -impl InstantiatedModuleOrGlobal { - pub fn leaf_module_source_location(self) -> SourceLocation { - match self { - Self::Global => SourceLocation::builtin(), - Self::InstantiatedModule(v) => v.leaf_module().source_location(), - } - } -} - -impl From for InstantiatedModuleOrGlobal { - fn from(value: InstantiatedModule) -> Self { - Self::InstantiatedModule(value) - } -} - -impl fmt::Debug for InstantiatedModuleOrGlobal { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self { - Self::Global => f.write_str("Global"), - Self::InstantiatedModule(v) => v.fmt(f), - } - } -} - #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] -pub struct TargetInInstantiatedModuleOrGlobal { - instantiated_module_or_global: InstantiatedModuleOrGlobal, - target: Target, -} - -impl TargetInInstantiatedModuleOrGlobal { - #[track_caller] - pub fn new(instantiated_module_or_global: InstantiatedModuleOrGlobal, target: Target) -> Self { - match ( - instantiated_module_or_global, - target.base().target_name().0.0, - ) { - (InstantiatedModuleOrGlobal::Global, NameIdOrGlobal::Global) - | (InstantiatedModuleOrGlobal::InstantiatedModule(_), NameIdOrGlobal::NameId(_)) => { - Self { - instantiated_module_or_global, - target, - } - } - (InstantiatedModuleOrGlobal::Global, NameIdOrGlobal::NameId(_)) - | (InstantiatedModuleOrGlobal::InstantiatedModule(_), NameIdOrGlobal::Global) => { - panic!( - "instantiated_module_or_global doesn't match target.base().target_name().0.0:\n\ - instantiated_module_or_global: {instantiated_module_or_global:?}\n\ - target: {target:?}" - ) - } - } - } - #[track_caller] - pub fn from_target( - instantiated_module: impl Into, - target: Target, - ) -> Self { - let instantiated_module = instantiated_module.into(); - Self { - instantiated_module_or_global: match target.base().target_name().0.0 { - NameIdOrGlobal::Global => InstantiatedModuleOrGlobal::Global, - NameIdOrGlobal::NameId(name_id) => { - let InstantiatedModuleOrGlobal::InstantiatedModule(instantiated_module) = - instantiated_module - else { - panic!( - "target is in a module, but no InstantiatedModule was provided: {target:#?}" - ); - }; - assert_eq!( - name_id, - instantiated_module.leaf_module().name_id(), - "target isn't contained in module:\n\ - target: {target:#?}\n\ - instantiated_module: {instantiated_module:?}", - ); - InstantiatedModuleOrGlobal::InstantiatedModule(instantiated_module) - } - }, - target, - } - } - pub fn instantiated_module_or_global(self) -> InstantiatedModuleOrGlobal { - self.instantiated_module_or_global - } - pub fn target(self) -> Target { - self.target - } +pub struct TargetInInstantiatedModule { + pub instantiated_module: InstantiatedModule, + pub target: Target, } #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs index 611401b..61167fd 100644 --- a/crates/fayalite/src/module/transform/deduce_resets.rs +++ b/crates/fayalite/src/module/transform/deduce_resets.rs @@ -10,8 +10,7 @@ use crate::{ ops::{self, ArrayLiteral}, target::{ Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField, - TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString, - TargetPathTraceAsStringInner, + TargetPathDynArrayElement, TargetPathElement, }, }, formal::FormalKind, @@ -27,7 +26,6 @@ use crate::{ prelude::*, reset::{ResetType, ResetTypeDispatch}, sim::ExternModuleSimulation, - ty::TraceAsString, util::{HashMap, HashSet}, }; use hashbrown::hash_map::Entry; @@ -105,10 +103,6 @@ enum ResetsLayout { element: Interned, reset_count: usize, }, - Transparent { - inner: Interned, - reset_count: usize, - }, } impl ResetsLayout { @@ -118,8 +112,7 @@ impl ResetsLayout { ResetsLayout::Reset | ResetsLayout::SyncReset | ResetsLayout::AsyncReset => 1, ResetsLayout::Bundle { reset_count, .. } | ResetsLayout::Enum { reset_count, .. } - | ResetsLayout::Array { reset_count, .. } - | ResetsLayout::Transparent { reset_count, .. } => reset_count, + | ResetsLayout::Array { reset_count, .. } => reset_count, } } fn new(ty: CanonicalType) -> Self { @@ -173,13 +166,6 @@ impl ResetsLayout { CanonicalType::Clock(_) => ResetsLayout::NoResets, CanonicalType::PhantomConst(_) => ResetsLayout::NoResets, CanonicalType::DynSimOnly(_) => ResetsLayout::NoResets, - CanonicalType::TraceAsString(ty) => { - let inner = ResetsLayout::new(ty.inner_ty()).intern_sized(); - ResetsLayout::Transparent { - inner, - reset_count: inner.reset_count(), - } - } } } } @@ -329,12 +315,6 @@ impl ResetGraph { } => { self.append_new_nodes_for_layout(*element, node_indexes, source_location); } - ResetsLayout::Transparent { - inner, - reset_count: _, - } => { - self.append_new_nodes_for_layout(*inner, node_indexes, source_location); - } } } } @@ -377,21 +357,6 @@ impl Resets { node_indexes: self.node_indexes, } } - fn trace_as_string_inner(self) -> Self { - let trace_as_string = TraceAsString::from_canonical(self.ty); - let ResetsLayout::Transparent { - inner, - reset_count: _, - } = self.layout - else { - unreachable!(); - }; - Self { - ty: trace_as_string.inner_ty(), - layout: *inner, - node_indexes: self.node_indexes, - } - } fn bundle_fields(self) -> impl Iterator { let bundle = Bundle::from_canonical(self.ty); let ResetsLayout::Bundle { @@ -515,17 +480,6 @@ impl Resets { CanonicalType::SyncReset(SyncReset) }, ), - CanonicalType::TraceAsString(ty) => Ok(CanonicalType::TraceAsString( - ty.with_new_inner_ty( - self.array_elements() - .substituted_type( - reset_graph, - fallback_to_sync_reset, - fallback_error_source_location, - )? - .intern_sized(), - ), - )), } } } @@ -1059,8 +1013,7 @@ fn cast_bit_op( | CanonicalType::Bundle(_) | CanonicalType::Reset(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) - | CanonicalType::TraceAsString(_) => unreachable!(), + | CanonicalType::DynSimOnly(_) => unreachable!(), $(CanonicalType::$Variant(ty) => Expr::expr_enum($arg.cast_to(ty)),)* } }; @@ -1071,8 +1024,7 @@ fn cast_bit_op( CanonicalType::Array(_) | CanonicalType::Enum(_) | CanonicalType::Bundle(_) - | CanonicalType::Reset(_) - | CanonicalType::TraceAsString(_) => unreachable!(), + | CanonicalType::Reset(_) => unreachable!(), CanonicalType::PhantomConst(_) | CanonicalType::DynSimOnly(_) => Expr::expr_enum(arg), $(CanonicalType::$Variant(_) => { @@ -1204,10 +1156,6 @@ impl RunPass

for ExprEnum { ExprEnum::SliceSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::CastToBits(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::CastBitsTo(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), - ExprEnum::TraceAsStringAsInner(expr) => { - Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)) - } - ExprEnum::ToTraceAsString(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::ModuleIO(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::Instance(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), ExprEnum::Wire(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), @@ -1215,10 +1163,6 @@ impl RunPass

for ExprEnum { ExprEnum::RegSync(expr) => reg_expr_run_pass(expr, pass_args), ExprEnum::RegAsync(expr) => reg_expr_run_pass(expr, pass_args), ExprEnum::MemPort(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), - ExprEnum::FormalInput(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)), - ExprEnum::SimIoForGlobal(_) => { - unreachable!("Module is known to not contain SimIoForGlobal from validation") - } } } } @@ -1592,67 +1536,6 @@ impl RunPassExpr for ops::CastBitsTo { } } -impl RunPassExpr for ops::TraceAsStringAsInner { - type Args<'a> = [Expr; 1]; - - fn args<'a>(&'a self) -> Self::Args<'a> { - [Expr::canonical(self.arg())] - } - - fn source_location(&self) -> Option { - None - } - - fn union_parts( - &self, - resets: Resets, - args_resets: Vec, - mut pass_args: PassArgs<'_, BuildResetGraph>, - ) -> Result<(), DeduceResetsError> { - pass_args.union(resets, args_resets[0].trace_as_string_inner(), None) - } - - fn new( - &self, - _ty: CanonicalType, - new_args: Vec>, - ) -> Result { - Ok(Self::new(Expr::from_canonical(new_args[0]))) - } -} - -impl RunPassExpr for ops::ToTraceAsString { - type Args<'a> = [Expr; 1]; - - fn args<'a>(&'a self) -> Self::Args<'a> { - [Expr::canonical(self.inner())] - } - - fn source_location(&self) -> Option { - None - } - - fn union_parts( - &self, - resets: Resets, - args_resets: Vec, - mut pass_args: PassArgs<'_, BuildResetGraph>, - ) -> Result<(), DeduceResetsError> { - pass_args.union(resets.trace_as_string_inner(), args_resets[0], None) - } - - fn new( - &self, - _ty: CanonicalType, - new_args: Vec>, - ) -> Result { - Ok(Self::new( - new_args[0], - self.ty().with_new_inner_ty(new_args[0].ty().intern_sized()), - )) - } -} - impl RunPassExpr for ModuleIO { type Args<'a> = [Expr; 0]; @@ -1808,8 +1691,7 @@ impl RunPassDispatch for AnyReg { | CanonicalType::Reset(_) | CanonicalType::Clock(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) - | CanonicalType::TraceAsString(_) => unreachable!(), + | CanonicalType::DynSimOnly(_) => unreachable!(), } }) } @@ -1936,7 +1818,6 @@ impl_run_pass_copy!([] SVAttributeAnnotation); impl_run_pass_copy!([] UInt); impl_run_pass_copy!([] usize); impl_run_pass_copy!([] FormalKind); -impl_run_pass_copy!([] crate::formal::FormalInput); impl_run_pass_copy!([] PhantomConst); macro_rules! impl_run_pass_for_struct { @@ -2253,12 +2134,6 @@ impl RunPass

for TargetBase { &TargetBase::RegAsync(v) => v.into(), TargetBase::Wire(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Wire)), TargetBase::Instance(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Instance)), - TargetBase::FormalInput(v) => { - return Ok(v.run_pass(pass_args)?.map(TargetBase::FormalInput)); - } - TargetBase::SimIoForGlobal(_) => { - unreachable!("Module is known to not contain SimIoForGlobal from validation") - } }; Ok(reg.run_pass(pass_args)?.map(|reg| match reg { AnyReg::Reg(reg) => TargetBase::Reg(reg), @@ -2298,6 +2173,30 @@ impl RunPass

for StmtDeclaration { } } +impl_run_pass_for_struct! { + impl[] RunPass for TargetPathBundleField { + name: _, + } +} + +impl_run_pass_for_struct! { + impl[] RunPass for TargetPathArrayElement { + index: _, + } +} + +impl_run_pass_for_struct! { + impl[] RunPass for TargetPathDynArrayElement {} +} + +impl_run_pass_for_enum! { + impl[] RunPass for TargetPathElement { + BundleField(v), + ArrayElement(v), + DynArrayElement(v), + } +} + impl_run_pass_for_enum! { impl[] RunPass for Target { Base(v), @@ -2305,28 +2204,11 @@ impl_run_pass_for_enum! { } } -impl RunPass

for TargetChild { - fn run_pass( - &self, - mut pass_args: PassArgs<'_, P>, - ) -> Result, DeduceResetsError> { - Ok(self.parent().run_pass(pass_args.as_mut())?.map(|parent| { - let path_element = match *self.path_element() { - TargetPathElement::BundleField(TargetPathBundleField { name: _ }) - | TargetPathElement::ArrayElement(TargetPathArrayElement { index: _ }) - | TargetPathElement::DynArrayElement(TargetPathDynArrayElement {}) - | TargetPathElement::TraceAsStringInner(TargetPathTraceAsStringInner {}) => { - self.path_element() - } - TargetPathElement::ToTraceAsString(TargetPathToTraceAsString { ty }) => { - TargetPathElement::from(TargetPathToTraceAsString { - ty: ty.with_new_inner_ty(parent.canonical_ty().intern_sized()), - }) - .intern_sized() - } - }; - TargetChild::new(parent, path_element) - })) +impl_run_pass_for_struct! { + #[constructor = TargetChild::new(parent, path_element)] + impl[] RunPass for TargetChild { + parent(): _, + path_element(): _, } } diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs index 280701d..8902921 100644 --- a/crates/fayalite/src/module/transform/simplify_enums.rs +++ b/crates/fayalite/src/module/transform/simplify_enums.rs @@ -17,7 +17,7 @@ use crate::{ transform::visit::{Fold, Folder}, }, source_location::SourceLocation, - ty::{CanonicalType, TraceAsString, Type}, + ty::{CanonicalType, Type}, util::HashMap, wire::Wire, }; @@ -64,7 +64,6 @@ fn contains_any_enum_types(ty: CanonicalType) -> bool { .fields() .iter() .any(|field| contains_any_enum_types(field.ty)), - CanonicalType::TraceAsString(ty) => contains_any_enum_types(ty.inner_ty()), CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -96,12 +95,11 @@ enum EnumTypeState { struct ModuleState { module_name: NameId, - expr_cache: HashMap, } impl ModuleState { fn gen_name(&mut self, name: &str) -> ScopedNameId { - ScopedNameId(self.module_name.into(), NameId(name.intern(), Id::new())) + ScopedNameId(self.module_name, NameId(name.intern(), Id::new())) } } @@ -315,24 +313,6 @@ impl State { } Ok(()) } - fn handle_stmt_connect_trace_as_string( - &mut self, - unfolded_lhs_ty: TraceAsString, - unfolded_rhs_ty: TraceAsString, - folded_lhs: Expr, - folded_rhs: Expr, - source_location: SourceLocation, - output_stmts: &mut Vec, - ) -> Result<(), SimplifyEnumsError> { - self.handle_stmt_connect( - unfolded_lhs_ty.inner_ty(), - unfolded_rhs_ty.inner_ty(), - ops::TraceAsStringAsInner::new(folded_lhs).to_expr(), - ops::TraceAsStringAsInner::new(folded_rhs).to_expr(), - source_location, - output_stmts, - ) - } fn handle_stmt_connect_bundle( &mut self, unfolded_lhs_ty: Bundle, @@ -529,15 +509,6 @@ impl State { source_location, output_stmts, ), - CanonicalType::TraceAsString(unfolded_lhs_ty) => self - .handle_stmt_connect_trace_as_string( - unfolded_lhs_ty, - TraceAsString::from_canonical(unfolded_rhs_ty), - Expr::from_canonical(folded_lhs), - Expr::from_canonical(folded_rhs), - source_location, - output_stmts, - ), CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -557,8 +528,6 @@ fn connect_port( rhs: Expr, source_location: SourceLocation, ) { - let lhs = Expr::unwrap_transparent_types(lhs); - let rhs = Expr::unwrap_transparent_types(rhs); if lhs.ty() == rhs.ty() { stmts.push( StmtConnect { @@ -604,9 +573,6 @@ fn connect_port( connect_port(stmts, lhs[index], rhs[index], source_location); } } - (CanonicalType::TraceAsString(_), CanonicalType::TraceAsString(_)) => { - unreachable!("handled by unwrap_transparent_types") - } (CanonicalType::Bundle(_), _) | (CanonicalType::Enum(_), _) | (CanonicalType::Array(_), _) @@ -618,8 +584,7 @@ fn connect_port( | (CanonicalType::SyncReset(_), _) | (CanonicalType::Reset(_), _) | (CanonicalType::PhantomConst(_), _) - | (CanonicalType::DynSimOnly(_), _) - | (CanonicalType::TraceAsString(_), _) => unreachable!( + | (CanonicalType::DynSimOnly(_), _) => unreachable!( "trying to connect memory ports:\n{:?}\n{:?}", lhs.ty(), rhs.ty(), @@ -676,7 +641,6 @@ impl Folder for State { fn fold_module(&mut self, v: Module) -> Result, Self::Error> { self.module_state_stack.push(ModuleState { module_name: v.name_id(), - expr_cache: HashMap::default(), }); let retval = Fold::default_fold(v, self); self.module_state_stack.pop(); @@ -684,39 +648,30 @@ impl Folder for State { } fn fold_expr_enum(&mut self, op: ExprEnum) -> Result { - if let Some(folded_op) = self - .module_state_stack - .last() - .expect("known to be in module") - .expr_cache - .get(&op) - { - return Ok(*folded_op); - } - let folded_op = match op { + match op { ExprEnum::EnumLiteral(op) => { let folded_variant_value = op.variant_value().map(|v| v.fold(self)).transpose()?; - *Expr::expr_enum(self.handle_enum_literal( + Ok(*Expr::expr_enum(self.handle_enum_literal( op.ty(), op.variant_index(), folded_variant_value, - )?) + )?)) } ExprEnum::VariantAccess(op) => { let folded_base_expr = Expr::canonical(op.base()).fold(self)?; - *Expr::expr_enum(self.handle_variant_access( + Ok(*Expr::expr_enum(self.handle_variant_access( op.base().ty(), folded_base_expr, op.variant_index(), - )?) + )?)) } - ExprEnum::MemPort(mem_port) => { + ExprEnum::MemPort(mem_port) => Ok( if let Some(&wire) = self.replacement_mem_ports.get(&mem_port) { ExprEnum::Wire(wire) } else { ExprEnum::MemPort(mem_port.fold(self)?) - } - } + }, + ), ExprEnum::UIntLiteral(_) | ExprEnum::SIntLiteral(_) | ExprEnum::BoolLiteral(_) @@ -817,23 +772,13 @@ impl Folder for State { | ExprEnum::SliceSInt(_) | ExprEnum::CastToBits(_) | ExprEnum::CastBitsTo(_) - | ExprEnum::TraceAsStringAsInner(_) - | ExprEnum::ToTraceAsString(_) | ExprEnum::ModuleIO(_) | ExprEnum::Instance(_) | ExprEnum::Wire(_) | ExprEnum::Reg(_) | ExprEnum::RegSync(_) - | ExprEnum::RegAsync(_) - | ExprEnum::FormalInput(_) - | ExprEnum::SimIoForGlobal(_) => op.default_fold(self)?, - }; - self.module_state_stack - .last_mut() - .expect("known to be in module") - .expr_cache - .insert(op, folded_op); - Ok(folded_op) + | ExprEnum::RegAsync(_) => op.default_fold(self), + } } fn fold_block(&mut self, block: Block) -> Result { @@ -991,8 +936,7 @@ impl Folder for State { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) - | CanonicalType::TraceAsString(_) => canonical_type.default_fold(self), + | CanonicalType::DynSimOnly(_) => canonical_type.default_fold(self), } } diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs index 4a97353..d741836 100644 --- a/crates/fayalite/src/module/transform/simplify_memories.rs +++ b/crates/fayalite/src/module/transform/simplify_memories.rs @@ -90,7 +90,7 @@ impl MemSplit { } } fn new(element_type: CanonicalType) -> Self { - match element_type.unwrap_transparent_types() { + match element_type { CanonicalType::Bundle(bundle_ty) => MemSplit::Bundle { fields: bundle_ty .fields() @@ -195,7 +195,6 @@ impl MemSplit { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) => unreachable!("memory element type is a storable type"), CanonicalType::DynSimOnly(_) => todo!("memory containing sim-only values"), - CanonicalType::TraceAsString(_) => unreachable!("handled by unwrap_transparent_types"), } } } @@ -307,9 +306,7 @@ impl SplitMemState<'_, '_> { let outer_mem_name_path_len = self.mem_name_path.len(); match self.split { MemSplit::Bundle { fields } => { - let CanonicalType::Bundle(bundle_type) = - self.element_type.unwrap_transparent_types() - else { + let CanonicalType::Bundle(bundle_type) = self.element_type else { unreachable!(); }; for ((field, field_offset), split) in bundle_type @@ -324,10 +321,7 @@ impl SplitMemState<'_, '_> { let field_ty_bit_width = field.ty.bit_width(); self.split_state_stack.push_map( |e: Expr| { - Expr::field( - Expr::::from_canonical(Expr::unwrap_transparent_types(e)), - &field.name, - ) + Expr::field(Expr::::from_canonical(e), &field.name) }, |initial_value_element| { let Some(field_offset) = field_offset.only_bit_width() else { @@ -383,8 +377,8 @@ impl SplitMemState<'_, '_> { }; self.output_stmts.push( StmtConnect { - lhs: Expr::unwrap_transparent_types(Expr::field(port_expr, name)), - rhs: Expr::unwrap_transparent_types(Expr::field(wire_expr, name)), + lhs: Expr::field(port_expr, name), + rhs: Expr::field(wire_expr, name), source_location: port.source_location(), } .into(), @@ -395,8 +389,7 @@ impl SplitMemState<'_, '_> { self.output_mems.push(new_mem); } MemSplit::Array { elements } => { - let CanonicalType::Array(array_type) = self.element_type.unwrap_transparent_types() - else { + let CanonicalType::Array(array_type) = self.element_type else { unreachable!(); }; let element_type = array_type.element(); @@ -405,7 +398,7 @@ impl SplitMemState<'_, '_> { self.mem_name_path.truncate(outer_mem_name_path_len); write!(self.mem_name_path, "_{index}").unwrap(); self.split_state_stack.push_map( - |e| Expr::::from_canonical(Expr::unwrap_transparent_types(e))[index], + |e| Expr::::from_canonical(e)[index], |initial_value_element| { &initial_value_element[index * element_bit_width..][..element_bit_width] }, @@ -471,7 +464,7 @@ impl ModuleState { assert_eq!(memory_element_array_range_len % input_array_type.len(), 0); let chunk_size = memory_element_array_range_len / input_array_type.len(); for index in 0..input_array_type.len() { - let map = |e| Expr::::from_canonical(Expr::unwrap_transparent_types(e))[index]; + let map = |e| Expr::::from_canonical(e)[index]; let wire_rdata = wire_rdata.map(map); let wire_wdata = wire_wdata.map(map); let wire_wmask = wire_wmask.map(map); @@ -512,8 +505,8 @@ impl ModuleState { port_read: Expr| { output_stmts.push( StmtConnect { - lhs: Expr::unwrap_transparent_types(wire_read), - rhs: Expr::unwrap_transparent_types(port_read), + lhs: wire_read, + rhs: port_read, source_location, } .into(), @@ -524,8 +517,8 @@ impl ModuleState { port_write: Expr| { output_stmts.push( StmtConnect { - lhs: Expr::unwrap_transparent_types(port_write), - rhs: Expr::unwrap_transparent_types(wire_write), + lhs: port_write, + rhs: wire_write, source_location, } .into(), @@ -537,8 +530,7 @@ impl ModuleState { connect_read( output_stmts, wire_read, - Expr::::from_canonical(Expr::unwrap_transparent_types(port_read)) - .cast_bits_to(wire_read.ty()), + Expr::::from_canonical(port_read).cast_bits_to(wire_read.ty()), ); }; let connect_write_enum = @@ -552,7 +544,7 @@ impl ModuleState { ); }; loop { - match input_element_type.unwrap_transparent_types() { + match input_element_type { CanonicalType::Bundle(_) => { unreachable!("bundle types are always split") } @@ -633,9 +625,6 @@ impl ModuleState { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) => unreachable!("memory element type is a storable type"), CanonicalType::DynSimOnly(_) => todo!("memory containing sim-only values"), - CanonicalType::TraceAsString(_) => { - unreachable!("handled by unwrap_transparent_types") - } } break; } diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs index 17fd88c..2869a49 100644 --- a/crates/fayalite/src/module/transform/visit.rs +++ b/crates/fayalite/src/module/transform/visit.rs @@ -14,17 +14,16 @@ use crate::{ Expr, ExprEnum, ValueType, ops, target::{ Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField, - TargetPathDynArrayElement, TargetPathElement, TargetPathToTraceAsString, - TargetPathTraceAsStringInner, + TargetPathDynArrayElement, TargetPathElement, }, }, - formal::{FormalInput, FormalInputKind, FormalKind}, + formal::FormalKind, int::{Bool, SIntType, SIntValue, Size, UIntType, UIntValue}, intern::{Intern, Interned}, memory::{Mem, MemPort, PortKind, PortName, PortType, ReadUnderWrite}, module::{ AnnotatedModuleIO, Block, BlockId, ExternModuleBody, ExternModuleParameter, - ExternModuleParameterValue, Instance, Module, ModuleBody, ModuleIO, NameId, NameIdOrGlobal, + ExternModuleParameterValue, Instance, Module, ModuleBody, ModuleIO, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, }, @@ -33,7 +32,7 @@ use crate::{ reset::{AsyncReset, Reset, ResetType, SyncReset}, sim::{ExternModuleSimulation, value::DynSimOnly}, source_location::SourceLocation, - ty::{CanonicalType, TraceAsString, Type}, + ty::{CanonicalType, Type}, vendor::xilinx::{ XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, XilinxAnnotation, }, @@ -482,30 +481,4 @@ impl, State: ?Sized + Visitor> Visit for &'_ mut } } -impl Visit for NameIdOrGlobal { - fn visit(&self, state: &mut State) -> Result<(), ::Error> { - state.visit_name_id_or_global(self) - } - - fn default_visit(&self, state: &mut State) -> Result<(), ::Error> { - match self { - Self::Global => Ok(()), - Self::NameId(name_id) => name_id.visit(state), - } - } -} - -impl Fold for NameIdOrGlobal { - fn fold(self, state: &mut State) -> Result::Error> { - state.fold_name_id_or_global(self) - } - - fn default_fold(self, state: &mut State) -> Result::Error> { - match self { - Self::Global => Ok(Self::Global), - Self::NameId(name_id) => Ok(Self::NameId(name_id.fold(state)?)), - } - } -} - include!(concat!(env!("OUT_DIR"), "/visit.rs")); diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index ba85817..fb7be6f 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -9,7 +9,7 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, - SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self, + StaticType, Type, TypeProperties, impl_match_variant_as_self, serde_impls::{SerdeCanonicalType, SerdePhantomConst}, }, }; @@ -327,15 +327,6 @@ impl Type for PhantomConst { } } -impl SimValueDebug for PhantomConst { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl Default for PhantomConst where Interned: Default, diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs index 69feeb5..4c5bfdf 100644 --- a/crates/fayalite/src/prelude.rs +++ b/crates/fayalite/src/prelude.rs @@ -13,11 +13,11 @@ pub use crate::{ enum_::{Enum, HdlNone, HdlOption, HdlSome}, expr::{ CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr, - ReduceBits, ToExpr, ToTraceAsString, ValueType, repeat, + ReduceBits, ToExpr, ValueType, repeat, }, formal::{ - all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, hdl_assert, - hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover, + MakeFormalExpr, all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, + hdl_assert, hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover, hdl_cover_with_enable, }, hdl, hdl_module, @@ -37,8 +37,8 @@ pub use crate::{ value::{SimOnly, SimOnlyValue, SimValue, ToSimValue, ToSimValueWithType}, }, source_location::SourceLocation, - testing::{FormalMode, assert_formal, checked_vcd_output}, - ty::{AsMask, CanonicalType, TraceAsString, Type}, + testing::{FormalMode, assert_formal}, + ty::{AsMask, CanonicalType, Type}, util::{ConstUsize, GenericConstUsize}, wire::Wire, }; diff --git a/crates/fayalite/src/reg.rs b/crates/fayalite/src/reg.rs index 2e4ab16..7f50655 100644 --- a/crates/fayalite/src/reg.rs +++ b/crates/fayalite/src/reg.rs @@ -79,7 +79,6 @@ impl Reg { if let Some(init) = init { assert_eq!(ty, init.ty(), "register's type must match init type"); } - scoped_name.0.assert_is_name_id(); Self { name: scoped_name, source_location, @@ -95,7 +94,7 @@ impl Reg { self.containing_module_name_id().0 } pub fn containing_module_name_id(&self) -> NameId { - self.name.0.unwrap_name_id() + self.name.0 } pub fn name(&self) -> Interned { self.name_id().0 diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs index ddc3651..13273ac 100644 --- a/crates/fayalite/src/reset.rs +++ b/crates/fayalite/src/reset.rs @@ -1,6 +1,5 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information - use crate::{ clock::Clock, expr::{CastToImpl, Expr, ValueType}, @@ -9,13 +8,11 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, - impl_match_variant_as_self, + OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self, }, util::ConstUsize, }; use bitvec::{bits, order::Lsb0}; -use std::fmt; mod sealed { pub trait ResetTypeSealed {} @@ -103,15 +100,6 @@ macro_rules! reset_type { } } - impl SimValueDebug for $name { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } - } - impl $name { pub fn type_properties(self) -> TypeProperties { Self::TYPE_PROPERTIES diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 3bd8466..45691ea 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -6,29 +6,25 @@ use crate::{ bundle::{BundleField, BundleType}, expr::{ - ExprEnum, Flow, - ops::SimIoForGlobal, + Flow, target::{ - GetTarget, Target, TargetBase, TargetChild, TargetPathArrayElement, - TargetPathBundleField, TargetPathElement, TargetPathTraceAsStringInner, + GetTarget, Target, TargetPathArrayElement, TargetPathBundleField, TargetPathElement, }, }, - formal::FormalInput, int::BoolOrIntType, intern::{ - Intern, InternSlice, Interned, InternedCompare, InternedSliceIter, Memoize, - PtrEqWithTypeId, SupportsPtrEqWithTypeId, + Intern, InternSlice, Interned, InternedCompare, PtrEqWithTypeId, SupportsPtrEqWithTypeId, }, module::{ - ModuleIO, StmtFormal, + ModuleIO, transform::visit::{Fold, Folder, Visit, Visitor}, }, prelude::*, reset::ResetType, sim::{ compiler::{ - Compiled, CompiledAssert, CompiledBundleField, CompiledExternModule, - CompiledTypeLayoutBody, CompiledValue, ExternModuleClockForPast, + Compiled, CompiledBundleField, CompiledExternModule, CompiledTypeLayoutBody, + CompiledValue, ExternModuleClockForPast, }, interpreter::{ BreakAction, BreakpointsSet, RunResult, SmallUInt, State, @@ -42,7 +38,7 @@ use crate::{ }, ty::{ OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSizeRange, OpaqueSimValueSlice, - OpaqueSimValueWriter, TraceAsString, + OpaqueSimValueWriter, }, util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet, copy_le_bytes_to_bitslice}, }; @@ -53,7 +49,7 @@ use std::{ any::Any, cell::{Cell, RefCell}, collections::{BTreeMap, BTreeSet}, - fmt::{self, Write}, + fmt, future::{Future, IntoFuture}, hash::Hash, mem, @@ -318,14 +314,6 @@ impl_trace_decl! { ty: CanonicalType, flow: Flow, }), - FormalInput(TraceFormalInput { - fn children(self) -> _ { - [*self.child].intern_slice() - } - name: Interned, - child: Interned, - formal_input: FormalInput, - }), Bundle(TraceBundle { fn children(self) -> _ { self.fields @@ -444,15 +432,6 @@ impl_trace_decl! { ty: DynSimOnly, flow: Flow, }), - TraceAsString(TraceTraceAsString { - fn location(self) -> _ { - self.location - } - location: TraceLocation, - name: Interned, - ty: TraceAsString, - flow: Flow, - }), }), } @@ -564,7 +543,6 @@ pub trait TraceWriter: fmt::Debug + 'static { id: TraceScalarId, value: &DynSimOnlyValue, ) -> Result<(), Self::Error>; - fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error>; } pub struct DynTraceWriterDecls(Box); @@ -629,7 +607,6 @@ trait TraceWriterDynTrait: fmt::Debug + 'static { id: TraceScalarId, value: &DynSimOnlyValue, ) -> std::io::Result<()>; - fn set_signal_string_dyn(&mut self, id: TraceScalarId, value: &str) -> std::io::Result<()>; } impl TraceWriterDynTrait for T { @@ -703,9 +680,6 @@ impl TraceWriterDynTrait for T { ) -> std::io::Result<()> { Ok(TraceWriter::set_signal_sim_only_value(self, id, value).map_err(err_into_io)?) } - fn set_signal_string_dyn(&mut self, id: TraceScalarId, value: &str) -> std::io::Result<()> { - Ok(TraceWriter::set_signal_string(self, id, value).map_err(err_into_io)?) - } } pub struct DynTraceWriter(Box); @@ -784,9 +758,6 @@ impl TraceWriter for DynTraceWriter { ) -> Result<(), Self::Error> { self.0.set_signal_sim_only_value_dyn(id, value) } - fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error> { - self.0.set_signal_string_dyn(id, value) - } } #[derive(Debug)] @@ -857,7 +828,6 @@ where #[derive(Clone, PartialEq, Eq, Hash, Debug)] pub(crate) struct SimTrace { kind: K, - maybe_changed: bool, state: S, last_state: S, } @@ -878,14 +848,12 @@ impl SimTraceDebug for SimTrace { fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { kind, - maybe_changed, state, last_state, } = self; f.debug_struct("SimTrace") .field("id", &id) .field("kind", kind) - .field("maybe_changed", maybe_changed) .field("state", state) .field("last_state", last_state) .finish() @@ -896,14 +864,12 @@ impl SimTraceDebug for SimTrace fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { kind, - maybe_changed, state, last_state, } = self; f.debug_struct("SimTrace") .field("id", &id) .field("kind", kind) - .field("maybe_changed", maybe_changed) .field("state", state) .field("last_state", last_state) .finish() @@ -963,10 +929,6 @@ pub(crate) enum SimTraceKind { PhantomConst { ty: PhantomConst, }, - TraceAsString { - layout: compiler::CompiledTypeLayout, - range: TypeIndexRange, - }, } #[derive(PartialEq, Eq)] @@ -974,7 +936,6 @@ pub(crate) enum SimTraceState { Bits(BitVec), SimOnly(DynSimOnlyValue), PhantomConst, - OpaqueSimValue(OpaqueSimValue), } impl Clone for SimTraceState { @@ -983,7 +944,6 @@ impl Clone for SimTraceState { Self::Bits(v) => Self::Bits(v.clone()), Self::SimOnly(v) => Self::SimOnly(v.clone()), Self::PhantomConst => Self::PhantomConst, - Self::OpaqueSimValue(v) => Self::OpaqueSimValue(v.clone()), } } fn clone_from(&mut self, source: &Self) { @@ -991,9 +951,6 @@ impl Clone for SimTraceState { (SimTraceState::Bits(dest), SimTraceState::Bits(source)) => { dest.clone_from_bitslice(source); } - (SimTraceState::OpaqueSimValue(dest), SimTraceState::OpaqueSimValue(source)) => { - dest.clone_from(source); - } _ => *self = source.clone(), } } @@ -1028,20 +985,6 @@ impl SimTraceState { unreachable!() } } - fn unwrap_opaque_sim_value_ref(&self) -> &OpaqueSimValue { - if let SimTraceState::OpaqueSimValue(v) = self { - v - } else { - unreachable!() - } - } - fn unwrap_opaque_sim_value_mut(&mut self) -> &mut OpaqueSimValue { - if let SimTraceState::OpaqueSimValue(v) = self { - v - } else { - unreachable!() - } - } } impl fmt::Debug for SimTraceState { @@ -1050,7 +993,6 @@ impl fmt::Debug for SimTraceState { SimTraceState::Bits(v) => BitSliceWriteWithBase(v).fmt(f), SimTraceState::SimOnly(v) => v.fmt(f), SimTraceState::PhantomConst => f.debug_tuple("PhantomConst").finish(), - SimTraceState::OpaqueSimValue(v) => v.fmt(f), } } } @@ -1079,13 +1021,6 @@ impl SimTraceKind { } SimTraceKind::PhantomConst { .. } => SimTraceState::PhantomConst, SimTraceKind::SimOnly { index: _, ty } => SimTraceState::SimOnly(ty.default_value()), - SimTraceKind::TraceAsString { layout, range: _ } => { - let type_properties = layout.ty.type_properties(); - SimTraceState::OpaqueSimValue(OpaqueSimValue::from_bits_and_sim_only_values( - UIntValue::new_dyn(Arc::new(BitVec::repeat(false, type_properties.bit_width))), - Vec::with_capacity(type_properties.sim_only_values_len), - )) - } } } } @@ -1240,31 +1175,6 @@ impl SimulationModuleState { true } } - CompiledTypeLayoutBody::Transparent { .. } => { - let value = value.map_ty(|ty| match ty { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) - | CanonicalType::Array(_) - | CanonicalType::Enum(_) - | CanonicalType::Bundle(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => unreachable!(), - CanonicalType::TraceAsString(ty) => ty, - }); - let sub_target = target - .join(TargetPathElement::from(TargetPathTraceAsStringInner {}).intern_sized()); - if self.parse_io(sub_target, value.inner()) { - self.uninitialized_ios.insert(target, vec![sub_target]); - true - } else { - false - } - } } } fn mark_target_as_initialized(&mut self, mut target: Target) { @@ -1299,14 +1209,9 @@ impl SimulationModuleState { #[track_caller] fn get_io( &self, - target: &mut Interned, - which_module: WhichModule<'_>, + mut target: Target, + which_module: WhichModule, ) -> CompiledValue { - match which_module { - WhichModule::Main { global_io } => *target = global_io.to_sim_io_target(*target), - WhichModule::Extern { .. } => {} - } - let mut target = **target; assert!( target.canonical_ty().is_passive(), "simulator read/write expression must have a passive type \ @@ -1320,10 +1225,7 @@ impl SimulationModuleState { Target::Base(_) => break, Target::Child(child) => { match *child.path_element() { - TargetPathElement::BundleField(_) - | TargetPathElement::ArrayElement(_) - | TargetPathElement::TraceAsStringInner(_) - | TargetPathElement::ToTraceAsString(_) => {} + TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} TargetPathElement::DynArrayElement(_) => panic!( "simulator read/write expression must not have dynamic array indexes" ), @@ -1333,9 +1235,9 @@ impl SimulationModuleState { }; } match which_module { - WhichModule::Main { .. } => panic!( + WhichModule::Main => panic!( "simulator read/write expression must be \ - an array element/field of `Simulation::io()` or `Simulation::global_io()`" + an array element/field of `Simulation::io()`" ), WhichModule::Extern { .. } => panic!( "simulator read/write expression must be \ @@ -1345,18 +1247,18 @@ impl SimulationModuleState { } } #[track_caller] - fn is_reset_async(&self, io: Expr, which_module: WhichModule<'_>) -> bool { - let Some(mut target) = io.target() else { + fn is_reset_async(&self, io: Expr, which_module: WhichModule) -> bool { + let Some(target) = io.target() else { match which_module { - WhichModule::Main { .. } => panic!( - "can't read from an expression that's not a field/element of `Simulation::io()` or `Simulation::global_io()`" + WhichModule::Main => panic!( + "can't read from an expression that's not a field/element of `Simulation::io()`" ), WhichModule::Extern { .. } => panic!( "can't read from an expression that's not based on one of this module's inputs/outputs" ), } }; - match self.get_io(&mut target, which_module).layout.ty { + match self.get_io(*target, which_module).layout.ty { CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -1366,8 +1268,7 @@ impl SimulationModuleState { | CanonicalType::Reset(_) | CanonicalType::Clock(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) - | CanonicalType::TraceAsString(_) => unreachable!(), + | CanonicalType::DynSimOnly(_) => unreachable!(), CanonicalType::AsyncReset(_) => true, CanonicalType::SyncReset(_) => false, } @@ -1376,24 +1277,24 @@ impl SimulationModuleState { fn read_helper_current( &self, io: Expr, - which_module: WhichModule<'_>, + which_module: WhichModule, ) -> MaybeNeedsSettle> { - let Some(mut target) = io.target() else { + let Some(target) = io.target() else { match which_module { - WhichModule::Main { .. } => panic!( - "can't read from an expression that's not a field/element of `Simulation::io()` or `Simulation::global_io()`" + WhichModule::Main => panic!( + "can't read from an expression that's not a field/element of `Simulation::io()`" ), WhichModule::Extern { .. } => panic!( "can't read from an expression that's not based on one of this module's inputs/outputs" ), } }; - let compiled_value = self.get_io(&mut target, which_module); + let compiled_value = self.get_io(*target, which_module); match target.flow() { Flow::Source => { if !self.uninitialized_ios.is_empty() { match which_module { - WhichModule::Main { .. } => { + WhichModule::Main => { panic!( "can't read from an output before initializing all inputs\nuninitialized_ios={:#?}", SortedSetDebug(&self.uninitialized_ios), @@ -1412,9 +1313,7 @@ impl SimulationModuleState { Flow::Sink => { if self.uninitialized_ios.contains_key(&*target) { match which_module { - WhichModule::Main { .. } => { - panic!("can't read from an uninitialized input") - } + WhichModule::Main => panic!("can't read from an uninitialized input"), WhichModule::Extern { .. } => { panic!("can't read from an uninitialized output"); } @@ -1430,7 +1329,7 @@ impl SimulationModuleState { &self, io: Expr, read_time: ReadTime, - which_module: WhichModule<'_>, + which_module: WhichModule, ) -> MaybeNeedsSettle> { match read_time { ReadTime::Current => self.read_helper_current(io, which_module), @@ -1456,22 +1355,22 @@ impl SimulationModuleState { fn write_helper( &mut self, io: Expr, - which_module: WhichModule<'_>, + which_module: WhichModule, ) -> CompiledValue { - let Some(mut target) = io.target() else { + let Some(target) = io.target() else { match which_module { - WhichModule::Main { .. } => panic!( - "can't write to an expression that's not a field/element of `Simulation::io()` or `Simulation::global_io()`" + WhichModule::Main => panic!( + "can't write to an expression that's not a field/element of `Simulation::io()`" ), WhichModule::Extern { .. } => panic!( "can't write to an expression that's not based on one of this module's outputs" ), } }; - let compiled_value = self.get_io(&mut target, which_module); + let compiled_value = self.get_io(*target, which_module); match target.flow() { Flow::Source => match which_module { - WhichModule::Main { .. } => panic!("can't write to an output"), + WhichModule::Main => panic!("can't write to an output"), WhichModule::Extern { .. } => panic!("can't write to an input"), }, Flow::Sink => {} @@ -1534,26 +1433,6 @@ impl SimulationExternModuleClockForPast { ); } } - CompiledTypeLayoutBody::Transparent { .. } => { - let map_ty_fn = |ty| match ty { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) - | CanonicalType::Array(_) - | CanonicalType::Enum(_) - | CanonicalType::Bundle(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => unreachable!(), - CanonicalType::TraceAsString(ty) => ty, - }; - let current = current.map_ty(map_ty_fn); - let past = past.map_ty(map_ty_fn); - self.add_current_to_past_mapping(current.inner(), past.inner()); - } } } } @@ -1591,9 +1470,9 @@ impl fmt::Debug for SimulationExternModuleState { } } -#[derive(Copy, Clone)] -enum WhichModule<'a> { - Main { global_io: &'a SimulationGlobalIo }, +#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] +enum WhichModule { + Main, Extern { module_index: usize }, } @@ -2004,7 +1883,6 @@ impl SensitivitySet { struct SimulationImpl { state: interpreter::State, io: Expr, - global_io: SimulationGlobalIo, main_module: SimulationModuleState, extern_modules: Box<[SimulationExternModuleState]>, trace_decls: TraceModule, @@ -2023,8 +1901,6 @@ struct SimulationImpl { ), >, waiting_sensitivity_sets_by_address: HashMap<*const SensitivitySet, Rc>, - trace_as_string_buf: String, - asserts: Interned<[CompiledAssert]>, } impl fmt::Debug for SimulationImpl { @@ -2102,7 +1978,6 @@ impl SimulationImpl { let Self { state, io: self_io, - global_io, main_module, extern_modules, trace_decls, @@ -2115,16 +1990,10 @@ impl SimulationImpl { next_sensitivity_set_debug_id: _, waiting_sensitivity_sets_by_compiled_value, waiting_sensitivity_sets_by_address, - trace_as_string_buf: _, - asserts, } = self; f.debug_struct("Simulation") .field("state", state) .field("io", io.unwrap_or(self_io)) - .field( - "global_io", - &fmt::from_fn(|f| f.debug_map().entries(global_io.global_io).finish()), - ) .field("main_module", main_module) .field("extern_modules", extern_modules) .field("trace_decls", trace_decls) @@ -2144,7 +2013,6 @@ impl SimulationImpl { "waiting_sensitivity_sets_by_compiled_value", &DebugSensitivitySetsByCompiledValue(waiting_sensitivity_sets_by_compiled_value), ) - .field("asserts", asserts) .finish_non_exhaustive() } fn new(compiled: Compiled) -> Self { @@ -2187,29 +2055,22 @@ impl SimulationImpl { Self { state: State::new(compiled.insns), io: compiled.io.to_expr(), - global_io: SimulationGlobalIo::new(compiled.global_io), main_module: SimulationModuleState::new( compiled - .global_io - .iter() - .map(|&(global_io, value)| (global_io.into(), value)) - .chain( - compiled - .io - .ty() - .fields() - .into_iter() - .zip(compiled.base_module.module_io) - .map(|(BundleField { name, .. }, value)| { - ( - io_target.join( - TargetPathElement::from(TargetPathBundleField { name }) - .intern_sized(), - ), - value, - ) - }), - ), + .io + .ty() + .fields() + .into_iter() + .zip(compiled.base_module.module_io) + .map(|(BundleField { name, .. }, value)| { + ( + io_target.join( + TargetPathElement::from(TargetPathBundleField { name }) + .intern_sized(), + ), + value, + ) + }), &[], ), extern_modules, @@ -2217,12 +2078,10 @@ impl SimulationImpl { traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { kind, - maybe_changed: _, state: _, last_state: _, }| SimTrace { kind, - maybe_changed: true, state: kind.make_state(), last_state: kind.make_state(), }, @@ -2235,8 +2094,6 @@ impl SimulationImpl { next_sensitivity_set_debug_id: 0, waiting_sensitivity_sets_by_compiled_value: HashMap::default(), waiting_sensitivity_sets_by_address: HashMap::default(), - trace_as_string_buf: String::with_capacity(256), - asserts: compiled.asserts, } } fn write_traces( @@ -2269,16 +2126,13 @@ impl SimulationImpl { id, &SimTrace { kind, - maybe_changed, ref state, ref last_state, }, ) in self.traces.0.iter().enumerate() { - if ONLY_IF_CHANGED { - if !(maybe_changed && state != last_state) { - continue; - } + if ONLY_IF_CHANGED && state == last_state { + continue; } let id = TraceScalarId(id); match kind { @@ -2317,15 +2171,6 @@ impl SimulationImpl { SimTraceKind::SimOnly { .. } => { trace_writer.set_signal_sim_only_value(id, state.unwrap_sim_only_ref())? } - SimTraceKind::TraceAsString { layout, .. } => { - self.trace_as_string_buf.clear(); - layout.ty.trace_fmt_append_to_string( - &mut self.trace_as_string_buf, - state.unwrap_opaque_sim_value_ref().as_slice(), - ); - trace_writer.set_signal_string(id, &self.trace_as_string_buf)?; - self.trace_as_string_buf.clear(); - } } } Ok(trace_writer) @@ -2348,48 +2193,10 @@ impl SimulationImpl { fn read_traces(&mut self) { for &mut SimTrace { kind, - ref mut maybe_changed, ref mut state, ref mut last_state, } in &mut self.traces.0 { - let new_maybe_changed = match kind { - SimTraceKind::BigUInt { index, ty: _ } - | SimTraceKind::BigSInt { index, ty: _ } - | SimTraceKind::BigBool { index } - | SimTraceKind::BigAsyncReset { index } - | SimTraceKind::BigSyncReset { index } - | SimTraceKind::BigClock { index } => self - .state - .big_slots - .state_index_fetch_maybe_modified_flag(index), - SimTraceKind::SmallUInt { index, ty: _ } - | SimTraceKind::SmallSInt { index, ty: _ } - | SimTraceKind::SmallBool { index } - | SimTraceKind::SmallAsyncReset { index } - | SimTraceKind::SmallSyncReset { index } - | SimTraceKind::SmallClock { index } - | SimTraceKind::EnumDiscriminant { index, ty: _ } => self - .state - .small_slots - .state_index_fetch_maybe_modified_flag(index), - SimTraceKind::SimOnly { index, ty: _ } => self - .state - .sim_only_slots - .state_index_fetch_maybe_modified_flag(index), - SimTraceKind::PhantomConst { ty: _ } => IS_INITIAL_STEP, - SimTraceKind::TraceAsString { layout: _, range } => self - .state - .type_index_range_fetch_maybe_modified_flags(range), - }; - if !new_maybe_changed && !IS_INITIAL_STEP { - if *maybe_changed { - last_state.clone_from(state); - } - *maybe_changed = false; - continue; - } - *maybe_changed = new_maybe_changed; if !IS_INITIAL_STEP { mem::swap(state, last_state); } @@ -2434,26 +2241,11 @@ impl SimulationImpl { .unwrap_sim_only_mut() .clone_from(&self.state.sim_only_slots[index]); } - SimTraceKind::TraceAsString { layout, range } => { - let CompiledTypeLayoutBody::Transparent { inner } = layout.body else { - unreachable!() - }; - Self::read_opaque_no_settle( - &mut self.state, - CompiledValue { - layout: *inner, - range, - write: None, - }, - state.unwrap_opaque_sim_value_mut(), - ); - } } if IS_INITIAL_STEP { last_state.clone_from(state); } } - self.state.clear_all_maybe_modified_flags(); } #[track_caller] fn advance_time(this_ref: &Rc>, duration: SimDuration) { @@ -2764,50 +2556,6 @@ impl SimulationImpl { self.cancel_wake_after_change(&sensitivity_set); } } - #[track_caller] - #[cold] - fn handle_failed_asserts(&mut self, assert_failed_log: Vec) -> ! { - let mut message = format!( - "Assertions/Assumptions failed at time {:?}:\n", - self.event_queue.lock().instant, - ); - for assert_failed_index in assert_failed_log { - let CompiledAssert { - instantiated_module, - stmt_formal: - StmtFormal { - kind, - clk: _, - pred: _, - en: _, - text, - source_location, - }, - } = self.asserts[assert_failed_index]; - writeln!( - message, - "at {source_location}: in {instantiated_module:?}: {} failed: {text}", - kind.as_str() - ) - .unwrap(); - } - panic!("{message}") - } - #[track_caller] - fn check_for_failed_asserts(&mut self) { - if self.state.assert_failed_log.is_empty() { - return; - } - if let Some(Event { - instant: _, - kind: EventKind::State, - }) = self.event_queue.peek_first_event_for_now() - { - return; - } - let assert_failed_log = mem::take(&mut self.state.assert_failed_log); - self.handle_failed_asserts(assert_failed_log); - } fn write_traces_after_event(&mut self) { if let Some(Event { instant: _, @@ -2910,7 +2658,6 @@ impl SimulationImpl { } } this.write_traces_after_event(); - this.check_for_failed_asserts(); this.check_waiting_sensitivity_sets(); } else { event_queue = first_entry.into_event_queue_lock(); @@ -2932,23 +2679,18 @@ impl SimulationImpl { fn settle(this_ref: &Rc>) { Self::run_until(this_ref, &mut Some); } - fn get_module(&self, which_module: WhichModule<'_>) -> &SimulationModuleState { + fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState { match which_module { - WhichModule::Main { .. } => &self.main_module, + WhichModule::Main => &self.main_module, WhichModule::Extern { module_index } => &self.extern_modules[module_index].module_state, } } - fn get_module_mut_and_which_module( - &mut self, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, - ) -> (&mut SimulationModuleState, WhichModule<'_>) { - let which_module = which_module(&self.global_io); + fn get_module_mut(&mut self, which_module: WhichModule) -> &mut SimulationModuleState { match which_module { - WhichModule::Main { .. } => (&mut self.main_module, which_module), - WhichModule::Extern { module_index } => ( - &mut self.extern_modules[module_index].module_state, - which_module, - ), + WhichModule::Main => &mut self.main_module, + WhichModule::Extern { module_index } => { + &mut self.extern_modules[module_index].module_state + } } } #[track_caller] @@ -2956,23 +2698,18 @@ impl SimulationImpl { &mut self, io: Expr, read_time: ReadTime, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, + which_module: WhichModule, ) -> MaybeNeedsSettle { - let which_module = which_module(&self.global_io); self.get_module(which_module) .read_helper(Expr::canonical(io), read_time, which_module) .map(|compiled_value| ReadBitFn { compiled_value }) .apply_no_settle(&mut self.state) } #[track_caller] - fn write_bit( - &mut self, - io: Expr, - value: bool, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, - ) { - let (module, which_module) = self.get_module_mut_and_which_module(which_module); - let compiled_value = module.write_helper(io, which_module); + fn write_bit(&mut self, io: Expr, value: bool, which_module: WhichModule) { + let compiled_value = self + .get_module_mut(which_module) + .write_helper(io, which_module); self.event_queue.add_event_for_now(EventKind::State); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { @@ -2990,9 +2727,8 @@ impl SimulationImpl { &mut self, io: Expr, read_time: ReadTime, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, + which_module: WhichModule, ) -> MaybeNeedsSettle, I::Value> { - let which_module = which_module(&self.global_io); self.get_module(which_module) .read_helper(Expr::canonical(io), read_time, which_module) .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io }) @@ -3003,10 +2739,11 @@ impl SimulationImpl { &mut self, io: Expr, value: I::Value, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, + which_module: WhichModule, ) { - let (module, which_module) = self.get_module_mut_and_which_module(which_module); - let compiled_value = module.write_helper(Expr::canonical(io), which_module); + let compiled_value = self + .get_module_mut(which_module) + .write_helper(Expr::canonical(io), which_module); self.event_queue.add_event_for_now(EventKind::State); let value: BigInt = value.into(); match compiled_value.range.len().as_single() { @@ -3035,7 +2772,6 @@ impl SimulationImpl { + Copy, read_write_sim_only_scalar: impl Fn(usize, &mut Opaque, &mut DynSimOnlyValue) + Copy, ) { - let compiled_value = compiled_value.unwrap_transparent_types(); match compiled_value.layout.body { CompiledTypeLayoutBody::Scalar => { let signed = match compiled_value.layout.ty { @@ -3051,7 +2787,6 @@ impl SimulationImpl { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => false, - CanonicalType::TraceAsString(_) => unreachable!(), }; let indexes = OpaqueSimValueSizeRange::from( start_index..start_index + compiled_value.layout.ty.size(), @@ -3128,17 +2863,14 @@ impl SimulationImpl { ); } } - CompiledTypeLayoutBody::Transparent { .. } => { - unreachable!("handled by unwrap_transparent_types") - } } } #[track_caller] - fn read_opaque_no_settle( + fn read_no_settle_helper( state: &mut interpreter::State, + io: Expr, compiled_value: CompiledValue, - opaque: &mut OpaqueSimValue, - ) { + ) -> SimValue { #[track_caller] fn read_write_sim_only_scalar( index: usize, @@ -3159,7 +2891,8 @@ impl SimulationImpl { }, ); } - let size = compiled_value.layout.ty.size(); + let size = io.ty().size(); + let mut opaque = OpaqueSimValue::with_capacity(size); opaque.rewrite_with(size, |mut writer| { SimulationImpl::read_write_sim_value_helper( state, @@ -3191,16 +2924,6 @@ impl SimulationImpl { ); writer.fill_cloned_from_slice(OpaqueSimValueSlice::empty()) }); - } - #[track_caller] - fn read_no_settle_helper( - state: &mut interpreter::State, - io: Expr, - compiled_value: CompiledValue, - ) -> SimValue { - let size = io.ty().size(); - let mut opaque = OpaqueSimValue::with_capacity(size); - Self::read_opaque_no_settle(state, compiled_value, &mut opaque); SimValue::from_opaque(io.ty(), opaque) } /// doesn't modify `opaque` @@ -3238,12 +2961,7 @@ impl SimulationImpl { any_change.get() } #[track_caller] - fn is_reset_async( - &self, - io: Expr, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, - ) -> bool { - let which_module = which_module(&self.global_io); + fn is_reset_async(&self, io: Expr, which_module: WhichModule) -> bool { self.get_module(which_module) .is_reset_async(io, which_module) } @@ -3252,12 +2970,11 @@ impl SimulationImpl { &mut self, io: Expr, read_time: ReadTime, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, + which_module: WhichModule, ) -> ( CompiledValue, MaybeNeedsSettle>, ) { - let which_module = which_module(&self.global_io); let compiled_value = self .get_module(which_module) .read_helper(io, read_time, which_module); @@ -3285,10 +3002,11 @@ impl SimulationImpl { &mut self, io: Expr, value: &SimValue, - which_module: impl for<'a> Fn(&'a SimulationGlobalIo) -> WhichModule<'a>, + which_module: WhichModule, ) { - let (module, which_module) = self.get_module_mut_and_which_module(which_module); - let compiled_value = module.write_helper(io, which_module); + let compiled_value = self + .get_module_mut(which_module) + .write_helper(io, which_module); self.event_queue.add_event_for_now(EventKind::State); assert_eq!(io.ty(), value.ty()); Self::read_write_sim_value_helper( @@ -3465,318 +3183,6 @@ impl Drop for SimulationImpl { } } -#[derive(Clone)] -pub struct SimulationGlobalIo { - global_io: Interned<[(SimIoForGlobal, CompiledValue)]>, - global_io_map: Rc>, -} - -impl Default for SimulationGlobalIo { - fn default() -> Self { - Self { - global_io: Interned::default(), - global_io_map: Rc::default(), - } - } -} - -impl fmt::Debug for SimulationGlobalIo { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_map().entries(self.global_io).finish() - } -} - -impl SimulationGlobalIo { - fn new(global_io: Interned<[(SimIoForGlobal, CompiledValue)]>) -> Self { - Self { - global_io, - global_io_map: Rc::new(HashMap::from_iter( - global_io - .iter() - .enumerate() - .map(|(index, &(global, _))| (global, index)), - )), - } - } - #[must_use] - pub fn iter(&self) -> SimulationGlobalIoIter { - SimulationGlobalIoIter { - global_io: self.global_io.into_iter(), - } - } - #[must_use] - pub fn globals(&self) -> SimulationGlobalIoGlobalsIter { - SimulationGlobalIoGlobalsIter { - global_io: self.global_io.into_iter(), - } - } - #[must_use] - pub fn exprs(&self) -> SimulationGlobalIoExprsIter { - SimulationGlobalIoExprsIter { - global_io: self.global_io.into_iter(), - } - } - #[must_use] - pub fn len(&self) -> usize { - self.global_io.len() - } - #[must_use] - pub fn is_empty(&self) -> bool { - self.len() == 0 - } - #[must_use] - pub fn contains(&self, global: FormalInput) -> bool { - self.global_io_map - .contains_key(&SimIoForGlobal::new(global)) - } - #[must_use] - pub fn get(&self, global: FormalInput) -> Option> { - self.contains(global) - .then(|| SimIoForGlobal::new(global).to_expr()) - } - #[must_use] - pub fn expr_to_global(&self, expr: Expr) -> Option { - let global = match *Expr::expr_enum(expr) { - ExprEnum::FormalInput(global) => global, - ExprEnum::SimIoForGlobal(expr) => expr.global(), - _ => return None, - }; - self.global_io_map - .contains_key(&SimIoForGlobal::new(global)) - .then_some(global) - } - #[must_use] - fn to_sim_io_target(&self, target: Interned) -> Interned { - #[derive(Copy, Clone, PartialEq, Eq, Hash)] - struct FormalInputExprToSimIoExpr; - impl Memoize for FormalInputExprToSimIoExpr { - type Input = Interned; - type InputOwned = Interned; - type Output = Interned; - - fn inner(self, input: &Self::Input) -> Self::Output { - match **input { - Target::Base(base) => match *base { - TargetBase::ModuleIO(_) - | TargetBase::MemPort(_) - | TargetBase::Reg(_) - | TargetBase::RegSync(_) - | TargetBase::RegAsync(_) - | TargetBase::Wire(_) - | TargetBase::Instance(_) - | TargetBase::SimIoForGlobal(_) => *input, - TargetBase::FormalInput(global) => { - Target::from(SimIoForGlobal::new(global)).intern() - } - }, - Target::Child(child) => Target::Child(TargetChild::new( - self.get_owned(child.parent()), - child.path_element(), - )) - .intern_sized(), - } - } - } - match *target.base() { - TargetBase::ModuleIO(_) - | TargetBase::MemPort(_) - | TargetBase::Reg(_) - | TargetBase::RegSync(_) - | TargetBase::RegAsync(_) - | TargetBase::Wire(_) - | TargetBase::Instance(_) - | TargetBase::SimIoForGlobal(_) => target, - TargetBase::FormalInput(global) => { - if self.contains(global) { - FormalInputExprToSimIoExpr.get_owned(target) - } else { - target - } - } - } - } -} - -impl IntoIterator for SimulationGlobalIo { - type Item = (FormalInput, Expr); - type IntoIter = SimulationGlobalIoIter; - - fn into_iter(self) -> Self::IntoIter { - self.iter() - } -} - -impl IntoIterator for &'_ SimulationGlobalIo { - type Item = (FormalInput, Expr); - type IntoIter = SimulationGlobalIoIter; - - fn into_iter(self) -> Self::IntoIter { - self.iter() - } -} - -impl IntoIterator for &'_ mut SimulationGlobalIo { - type Item = (FormalInput, Expr); - type IntoIter = SimulationGlobalIoIter; - - fn into_iter(self) -> Self::IntoIter { - self.iter() - } -} - -macro_rules! make_simulation_global_io_iter { - ( - impl $SimulationGlobalIoIter:ident { - fn $global_io_to_item:ident( - $global_io_to_item_arg:ident: (SimIoForGlobal, CompiledValue), - ) -> $item_ty:ty - $global_io_to_item_block:block - } - ) => { - #[derive(Clone, Default)] - pub struct $SimulationGlobalIoIter { - global_io: InternedSliceIter<(SimIoForGlobal, CompiledValue)>, - } - - impl $SimulationGlobalIoIter { - fn $global_io_to_item( - $global_io_to_item_arg: (SimIoForGlobal, CompiledValue), - ) -> $item_ty - $global_io_to_item_block - } - - impl Iterator for $SimulationGlobalIoIter { - type Item = $item_ty; - - fn next(&mut self) -> Option { - self.global_io.next().map(Self::global_io_to_item) - } - - fn size_hint(&self) -> (usize, Option) { - self.global_io.size_hint() - } - - fn count(self) -> usize { - self.global_io.count() - } - - fn last(mut self) -> Option { - self.next_back() - } - - fn nth(&mut self, n: usize) -> Option { - self.global_io.nth(n).map(Self::global_io_to_item) - } - - fn fold(self, init: B, f: F) -> B - where - F: FnMut(B, Self::Item) -> B, - { - self.global_io.map(Self::global_io_to_item).fold(init, f) - } - } - - impl std::iter::FusedIterator for $SimulationGlobalIoIter {} - - impl DoubleEndedIterator for $SimulationGlobalIoIter { - fn next_back(&mut self) -> Option { - self.global_io.next_back().map(Self::global_io_to_item) - } - - fn nth_back(&mut self, n: usize) -> Option { - self.global_io.nth_back(n).map(Self::global_io_to_item) - } - - fn rfold(self, init: B, f: F) -> B - where - F: FnMut(B, Self::Item) -> B, - { - self.global_io.map(Self::global_io_to_item).rfold(init, f) - } - } - - impl ExactSizeIterator for $SimulationGlobalIoIter {} - }; -} - -make_simulation_global_io_iter! { - impl SimulationGlobalIoIter { - fn global_io_to_item( - v: (SimIoForGlobal, CompiledValue), - ) -> (FormalInput, Expr) { - let (global, _) = v; - (global.global(), global.to_expr()) - } - } -} - -impl SimulationGlobalIoIter { - #[must_use] - pub fn globals(self) -> SimulationGlobalIoGlobalsIter { - SimulationGlobalIoGlobalsIter { - global_io: self.global_io, - } - } - #[must_use] - pub fn exprs(self) -> SimulationGlobalIoExprsIter { - SimulationGlobalIoExprsIter { - global_io: self.global_io, - } - } -} - -impl fmt::Debug for SimulationGlobalIoIter { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_tuple("SimulationGlobalIoIter") - .field(&fmt::from_fn(|f| { - f.debug_map().entries(self.clone()).finish() - })) - .finish() - } -} - -make_simulation_global_io_iter! { - impl SimulationGlobalIoGlobalsIter { - fn global_io_to_item( - v: (SimIoForGlobal, CompiledValue), - ) -> FormalInput { - let (global, _) = v; - global.global() - } - } -} - -impl fmt::Debug for SimulationGlobalIoGlobalsIter { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_tuple("SimulationGlobalIoGlobalsIter") - .field(&fmt::from_fn(|f| { - f.debug_set().entries(self.clone()).finish() - })) - .finish() - } -} - -make_simulation_global_io_iter! { - impl SimulationGlobalIoExprsIter { - fn global_io_to_item( - v: (SimIoForGlobal, CompiledValue), - ) -> Expr { - let (global, _) = v; - global.to_expr() - } - } -} - -impl fmt::Debug for SimulationGlobalIoExprsIter { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_tuple("SimulationGlobalIoExprsIter") - .field(&fmt::from_fn(|f| { - f.debug_set().entries(self.clone()).finish() - })) - .finish() - } -} - pub struct Simulation { sim_impl: Rc>, io: Expr, @@ -3851,15 +3257,14 @@ macro_rules! impl_simulation_methods { ( async_await = ($($async:tt, $await:tt)?), track_caller = ($(#[$track_caller:tt])?), - which_module = |$self:ident, $global_io:ident| $which_module:expr, + which_module = |$self:ident| $which_module:expr, ) => { $(#[$track_caller])? pub $($async)? fn read_bool_or_int(&mut $self, io: Expr) -> I::Value { - let retval = $self.sim_impl.borrow_mut().read_bool_or_int( - io, - ReadTime::Current, - |$global_io: &SimulationGlobalIo| $which_module, - ); + let retval = $self + .sim_impl + .borrow_mut() + .read_bool_or_int(io, ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3872,74 +3277,64 @@ macro_rules! impl_simulation_methods { $self.sim_impl.borrow_mut().write_bool_or_int( io, SimValue::into_value(value), - |$global_io: &SimulationGlobalIo| $which_module, + $which_module, ); } $(#[$track_caller])? pub $($async)? fn write_clock(&mut $self, io: Expr, value: bool) { - $self.sim_impl.borrow_mut().write_bit( - Expr::canonical(io), - value, - |$global_io: &SimulationGlobalIo| $which_module, - ); + $self.sim_impl + .borrow_mut() + .write_bit(Expr::canonical(io), value, $which_module); } $(#[$track_caller])? pub $($async)? fn read_clock(&mut $self, io: Expr) -> bool { - let retval = $self.sim_impl.borrow_mut().read_bit( - Expr::canonical(io), - ReadTime::Current, - |$global_io: &SimulationGlobalIo| $which_module, - ); + let retval = $self + .sim_impl + .borrow_mut() + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? pub $($async)? fn write_bool(&mut $self, io: Expr, value: bool) { - $self.sim_impl.borrow_mut().write_bit( - Expr::canonical(io), - value, - |$global_io: &SimulationGlobalIo| $which_module, - ); + $self.sim_impl + .borrow_mut() + .write_bit(Expr::canonical(io), value, $which_module); } $(#[$track_caller])? pub $($async)? fn read_bool(&mut $self, io: Expr) -> bool { - let retval = $self.sim_impl.borrow_mut().read_bit( - Expr::canonical(io), - ReadTime::Current, - |$global_io: &SimulationGlobalIo| $which_module, - ); + let retval = $self + .sim_impl + .borrow_mut() + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? pub $($async)? fn write_reset(&mut $self, io: Expr, value: bool) { - $self.sim_impl.borrow_mut().write_bit( - Expr::canonical(io), - value, - |$global_io: &SimulationGlobalIo| $which_module, - ); + $self.sim_impl + .borrow_mut() + .write_bit(Expr::canonical(io), value, $which_module); } $(#[$track_caller])? pub $($async)? fn read_reset(&mut $self, io: Expr) -> bool { - let retval = $self.sim_impl.borrow_mut().read_bit( - Expr::canonical(io), - ReadTime::Current, - |$global_io: &SimulationGlobalIo| $which_module, - ); + let retval = $self + .sim_impl + .borrow_mut() + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } #[track_caller] pub fn is_reset_async(&$self, io: Expr) -> bool { - $self.sim_impl.borrow().is_reset_async( - Expr::canonical(io), - |$global_io: &SimulationGlobalIo| $which_module, - ) + $self + .sim_impl + .borrow_mut() + .is_reset_async(Expr::canonical(io), $which_module) } $(#[$track_caller])? pub $($async)? fn read(&mut $self, io: Expr) -> SimValue { - let retval = $self.sim_impl.borrow_mut().read( - Expr::canonical(io), - ReadTime::Current, - |$global_io: &SimulationGlobalIo| $which_module, - ).1; + let retval = $self + .sim_impl + .borrow_mut() + .read(Expr::canonical(io), ReadTime::Current, $which_module).1; SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?) } $(#[$track_caller])? @@ -3947,7 +3342,7 @@ macro_rules! impl_simulation_methods { $self.sim_impl.borrow_mut().write( Expr::canonical(io), &SimValue::into_canonical(value.into_sim_value_with_type(io.ty())), - |$global_io: &SimulationGlobalIo| $which_module, + $which_module, ); } }; @@ -3986,9 +3381,6 @@ impl Simulation { pub fn io(&self) -> Expr { self.io.to_expr() } - pub fn global_io(&self) -> SimulationGlobalIo { - self.sim_impl.borrow().global_io.clone() - } pub fn from_compiled(compiled: Compiled) -> Self { let sim_impl = SimulationImpl::new(compiled.canonical()); Self { @@ -4014,7 +3406,7 @@ impl Simulation { impl_simulation_methods!( async_await = (), track_caller = (#[track_caller]), - which_module = |self, global_io| WhichModule::Main { global_io }, + which_module = |self| WhichModule::Main, ); #[doc(hidden)] /// This is explicitly unstable and may be changed/removed at any time @@ -4083,7 +3475,7 @@ impl ExternModuleSimulationState { let (key, value) = self .sim_impl .borrow_mut() - .read(io, ReadTime::Current, |_| which_module); + .read(io, ReadTime::Current, which_module); let value = self.settle_if_needed(value).await; let key = Rc::new(key); if sensitivity_set.compiled_values.insert(key.clone()) { @@ -4355,7 +3747,7 @@ impl ExternModuleSimulationState { let retval = self.sim_impl.borrow_mut().read_bool_or_int( io, ReadTime::Past { clock_for_past }, - |_| WhichModule::Extern { + WhichModule::Extern { module_index: self.module_index, }, ); @@ -4371,7 +3763,7 @@ impl ExternModuleSimulationState { let retval = self.sim_impl.borrow_mut().read_bit( Expr::canonical(io), ReadTime::Past { clock_for_past }, - |_| WhichModule::Extern { + WhichModule::Extern { module_index: self.module_index, }, ); @@ -4387,7 +3779,7 @@ impl ExternModuleSimulationState { let retval = self.sim_impl.borrow_mut().read_bit( Expr::canonical(io), ReadTime::Past { clock_for_past }, - |_| WhichModule::Extern { + WhichModule::Extern { module_index: self.module_index, }, ); @@ -4407,7 +3799,7 @@ impl ExternModuleSimulationState { let retval = self.sim_impl.borrow_mut().read_bit( Expr::canonical(io), ReadTime::Past { clock_for_past }, - |_| WhichModule::Extern { + WhichModule::Extern { module_index: self.module_index, }, ); @@ -4430,7 +3822,7 @@ impl ExternModuleSimulationState { .read( Expr::canonical(io), ReadTime::Past { clock_for_past }, - |_| WhichModule::Extern { + WhichModule::Extern { module_index: self.module_index, }, ) @@ -4440,7 +3832,7 @@ impl ExternModuleSimulationState { impl_simulation_methods!( async_await = (async, await), track_caller = (), - which_module = |self, _global_io| WhichModule::Extern { module_index: self.module_index }, + which_module = |self| WhichModule::Extern { module_index: self.module_index }, ); } diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index c3c47fd..e85ff0f 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -7,32 +7,29 @@ use crate::{ bundle::{BundleField, BundleType}, enum_::{EnumType, EnumVariant}, expr::{ - ExprEnum, Flow, ValueType, - ops::{self, SimIoForGlobal}, + ExprEnum, Flow, ValueType, ops, target::{ GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, - TargetPathElement, TargetPathToTraceAsString, TargetPathTraceAsStringInner, + TargetPathElement, }, }, - formal::FormalKind, int::BoolOrIntType, intern::{Intern, InternSlice, Interned, Memoize}, memory::PortKind, module::{ - AnnotatedModuleIO, Block, ExternModuleBody, Id, InstantiatedModule, - InstantiatedModuleOrGlobal, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, - StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, - StmtWire, TargetInInstantiatedModuleOrGlobal, transform::deduce_resets::deduce_resets, + AnnotatedModuleIO, Block, ExternModuleBody, Id, InstantiatedModule, ModuleBody, NameId, + NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, + StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule, + transform::deduce_resets::deduce_resets, }, prelude::*, reset::{ResetType, ResetTypeDispatch}, sim::{ ExternModuleSimulation, SimTrace, SimTraceKind, SimTraces, TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl, TraceEnumDiscriminant, TraceEnumWithFields, - TraceFieldlessEnum, TraceFormalInput, TraceInstance, TraceLocation, TraceMem, TraceMemPort, - TraceMemoryId, TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, - TraceReg, TraceSInt, TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, - TraceTraceAsString, TraceUInt, TraceWire, + TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, + TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, + TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, interpreter::{ self, Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label, PrefixLinesWrapper, SmallUInt, @@ -45,8 +42,8 @@ use crate::{ }, }, }, - ty::{OpaqueSimValueSize, StaticType, TraceAsString}, - util::{HashMap, HashSet, chain}, + ty::{OpaqueSimValueSize, StaticType}, + util::{HashMap, chain}, }; use bitvec::vec::BitVec; use num_bigint::BigInt; @@ -113,9 +110,6 @@ pub(crate) enum CompiledTypeLayoutBody { Bundle { fields: Interned<[CompiledBundleField]>, }, - Transparent { - inner: Interned>, - }, } impl CompiledTypeLayoutBody { @@ -134,9 +128,6 @@ impl CompiledTypeLayoutBody { .map(|field| field.with_prefixed_debug_names(prefix)) .collect(), }, - CompiledTypeLayoutBody::Transparent { inner } => CompiledTypeLayoutBody::Transparent { - inner: inner.with_prefixed_debug_names(prefix).intern_sized(), - }, } } fn with_anonymized_debug_info(self) -> Self { @@ -154,9 +145,6 @@ impl CompiledTypeLayoutBody { .map(|field| field.with_anonymized_debug_info()) .collect(), }, - CompiledTypeLayoutBody::Transparent { inner } => CompiledTypeLayoutBody::Transparent { - inner: inner.with_anonymized_debug_info().intern_sized(), - }, } } } @@ -191,7 +179,7 @@ impl CompiledTypeLayout { impl Memoize for MyMemoize { type Input = CanonicalType; type InputOwned = CanonicalType; - type Output = (TypeLayout, CompiledTypeLayoutBody); + type Output = CompiledTypeLayout; fn inner(self, input: &Self::Input) -> Self::Output { match input { @@ -209,7 +197,11 @@ impl CompiledTypeLayout { ty: *input, }; layout.big_slots = StatePartLayout::scalar(debug_data, ()); - (layout.into(), CompiledTypeLayoutBody::Scalar) + CompiledTypeLayout { + ty: *input, + layout: layout.into(), + body: CompiledTypeLayoutBody::Scalar, + } } CanonicalType::Array(array) => { let mut layout = TypeLayout::empty(); @@ -223,16 +215,19 @@ impl CompiledTypeLayout { if array.is_empty() { elements_non_empty.push(element.with_prefixed_debug_names("[]")); } - ( - layout.into(), - CompiledTypeLayoutBody::Array { + CompiledTypeLayout { + ty: *input, + layout: layout.into(), + body: CompiledTypeLayoutBody::Array { elements_non_empty: elements_non_empty.intern_deref(), }, - ) - } - CanonicalType::PhantomConst(_) => { - (TypeLayout::empty(), CompiledTypeLayoutBody::PhantomConst) + } } + CanonicalType::PhantomConst(_) => CompiledTypeLayout { + ty: *input, + layout: TypeLayout::empty(), + body: CompiledTypeLayoutBody::PhantomConst, + }, CanonicalType::Bundle(bundle) => { let mut layout = TypeLayout::empty(); let fields = bundle @@ -251,7 +246,11 @@ impl CompiledTypeLayout { }, ) .collect(); - (layout.into(), CompiledTypeLayoutBody::Bundle { fields }) + CompiledTypeLayout { + ty: *input, + layout: layout.into(), + body: CompiledTypeLayoutBody::Bundle { fields }, + } } CanonicalType::DynSimOnly(ty) => { let mut layout = TypeLayout::empty(); @@ -260,30 +259,24 @@ impl CompiledTypeLayout { ty: *input, }; layout.sim_only_slots = StatePartLayout::scalar(debug_data, *ty); - (layout.into(), CompiledTypeLayoutBody::Scalar) - } - CanonicalType::TraceAsString(ty) => { - let inner = CompiledTypeLayout::get(ty.inner_ty()).intern_sized(); - (inner.layout, CompiledTypeLayoutBody::Transparent { inner }) + CompiledTypeLayout { + ty: *input, + layout: layout.into(), + body: CompiledTypeLayoutBody::Scalar, + } } } } } - let (layout, body) = MyMemoize.get_owned(ty.canonical()); + let CompiledTypeLayout { + ty: _, + layout, + body, + } = MyMemoize.get_owned(ty.canonical()); Self { ty, layout, body } } } -impl CompiledTypeLayout { - #[must_use] - fn unwrap_transparent_types(mut self) -> Self { - while let CompiledTypeLayoutBody::Transparent { inner } = self.body { - self = *inner; - } - self - } -} - #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) struct CompiledValue { pub(crate) layout: CompiledTypeLayout, @@ -331,29 +324,6 @@ impl CompiledValue { } } -impl CompiledValue { - #[must_use] - pub(crate) fn unwrap_transparent_types(self) -> Self { - let Self { - layout, - range, - write, - } = self; - Self { - layout: layout.unwrap_transparent_types(), - range, - write: write.map(|(layout, range)| (layout.unwrap_transparent_types(), range)), - } - } - #[must_use] - pub(crate) fn wrap_in_trace_as_string(self, ty: TraceAsString) -> CompiledValue { - self.map(|layout, range| { - assert_eq!(layout.ty, ty.inner_ty()); - (CompiledTypeLayout::get(ty), range) - }) - } -} - pub(crate) struct DebugCompiledValueStateAsMap<'a> { pub(crate) compiled_value: CompiledValue, pub(crate) state_layout: &'a interpreter::parts::StateLayout, @@ -432,17 +402,6 @@ impl CompiledValue { } } -impl CompiledValue { - pub(crate) fn inner(self) -> CompiledValue { - self.map(|layout, range| { - let CompiledTypeLayoutBody::Transparent { inner } = layout.body else { - unreachable!(); - }; - (*inner, range) - }) - } -} - macro_rules! make_type_array_indexes { ( type_plural_fields = [$($type_plural_field:ident,)*]; @@ -659,16 +618,6 @@ impl CompiledExpr { } } -impl CompiledExpr { - #[must_use] - pub(crate) fn wrap_in_trace_as_string(self, ty: TraceAsString) -> CompiledExpr { - CompiledExpr { - static_part: self.static_part.wrap_in_trace_as_string(ty), - indexes: self.indexes, - } - } -} - impl CompiledExpr { fn field_by_index(self, field_index: usize) -> CompiledExpr { CompiledExpr { @@ -717,15 +666,6 @@ impl CompiledExpr { } } -impl CompiledExpr { - pub(crate) fn inner(self) -> CompiledExpr { - CompiledExpr { - static_part: self.static_part.inner(), - indexes: self.indexes, - } - } -} - macro_rules! make_assignment_graph { ( type_plural_fields = [$($type_plural_field:ident,)*]; @@ -1753,19 +1693,6 @@ struct Memory { ports: Vec, } -#[derive(Clone, PartialEq, Eq, Hash, Debug)] -pub(crate) struct CompiledAssert { - pub(crate) instantiated_module: Interned, - pub(crate) stmt_formal: StmtFormal, -} - -#[derive(Debug)] -struct Assert { - compiled_assert: CompiledAssert, - clk_triggered: StatePartIndex, - pred: StatePartIndex, -} - #[derive(Copy, Clone)] enum MakeTraceDeclTarget { Expr(Expr), @@ -1817,10 +1744,10 @@ pub struct Compiler { base_module: Interned>, modules: HashMap, extern_modules: Vec, - compiled_values: HashMap>, + compiled_values: HashMap>, compiled_exprs: HashMap, CompiledExpr>, compiled_exprs_to_values: HashMap, CompiledValue>, - decl_conditions: HashMap>, + decl_conditions: HashMap>, compiled_values_to_dyn_array_indexes: HashMap, StatePartIndex>, compiled_value_bool_dest_is_small_map: @@ -1833,10 +1760,6 @@ pub struct Compiler { traces: SimTraces>>, memories: Vec, dump_assignments_dot: Option>>, - global_io: Vec<(SimIoForGlobal, CompiledValue)>, - global_io_set: HashSet, - global_trace_decls: Vec, - asserts: Vec, } macro_rules! impl_compiler { @@ -1852,7 +1775,7 @@ macro_rules! impl_compiler { impl Compiler { fn make_trace_scalar_helper( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, target: MakeTraceDeclTarget, source_location: SourceLocation, empty_kind: impl FnOnce() -> SimTraceKind, @@ -1860,7 +1783,7 @@ macro_rules! impl_compiler { ) -> TraceLocation { match target { MakeTraceDeclTarget::Expr(target) => { - let compiled_value = self.compile_expr(instantiated_module_or_global, target); + let compiled_value = self.compile_expr(instantiated_module, target); let compiled_value = self.compiled_expr_to_value(compiled_value, source_location); if compiled_value.range.is_empty() { TraceLocation::Scalar(self.new_sim_trace(empty_kind())) @@ -1890,7 +1813,7 @@ macro_rules! impl_compiler { } fn make_trace_scalar( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, target: MakeTraceDeclTarget, name: Interned, source_location: SourceLocation, @@ -1899,7 +1822,7 @@ macro_rules! impl_compiler { match target.ty() { CanonicalType::UInt(ty) => TraceUInt { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -1914,7 +1837,7 @@ macro_rules! impl_compiler { .into(), CanonicalType::SInt(ty) => TraceSInt { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -1929,7 +1852,7 @@ macro_rules! impl_compiler { .into(), CanonicalType::Bool(_) => TraceBool { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -1946,7 +1869,7 @@ macro_rules! impl_compiler { assert_eq!(ty.discriminant_bit_width(), ty.type_properties().bit_width); let location = match target { MakeTraceDeclTarget::Expr(target) => { - let compiled_value = self.compile_expr(instantiated_module_or_global, target); + let compiled_value = self.compile_expr(instantiated_module, target); let compiled_value = self.compiled_expr_to_value(compiled_value, source_location); let discriminant = self.compile_enum_discriminant( @@ -1983,7 +1906,7 @@ macro_rules! impl_compiler { CanonicalType::Bundle(_) => unreachable!(), CanonicalType::AsyncReset(_) => TraceAsyncReset { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -1997,7 +1920,7 @@ macro_rules! impl_compiler { .into(), CanonicalType::SyncReset(_) => TraceSyncReset { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -2012,7 +1935,7 @@ macro_rules! impl_compiler { CanonicalType::Reset(_) => unreachable!(), CanonicalType::Clock(_) => TraceClock { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -2026,7 +1949,7 @@ macro_rules! impl_compiler { .into(), CanonicalType::PhantomConst(ty) => TracePhantomConst { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || SimTraceKind::PhantomConst { ty }, @@ -2041,7 +1964,7 @@ macro_rules! impl_compiler { .into(), CanonicalType::DynSimOnly(ty) => TraceSimOnly { location: self.make_trace_scalar_helper( - instantiated_module_or_global, + instantiated_module, target, source_location, || unreachable!(), @@ -2054,39 +1977,6 @@ macro_rules! impl_compiler { flow, } .into(), - CanonicalType::TraceAsString(ty) => { - let location = match target { - MakeTraceDeclTarget::Expr(target) => { - let compiled_value = self.compile_expr(instantiated_module_or_global, target); - let CompiledValue { layout, range, write: _ } = - self.compiled_expr_to_value(compiled_value, source_location).map_ty(Type::from_canonical); - TraceLocation::Scalar(self.new_sim_trace(SimTraceKind::TraceAsString { - layout, - range, - })) - } - MakeTraceDeclTarget::Memory { - id, - depth, - stride, - start, - ty: _, - } => TraceLocation::Memory(TraceMemoryLocation { - id, - depth, - stride, - start, - len: ty.type_properties().bit_width, - }), - }; - TraceTraceAsString { - location, - name, - ty, - flow, - } - .into() - } } } fn compiled_expr_to_value( @@ -2333,10 +2223,6 @@ impl Compiler { traces: SimTraces(Vec::new()), memories: Vec::new(), dump_assignments_dot: None, - global_io: Vec::new(), - global_io_set: HashSet::default(), - global_trace_decls: Vec::new(), - asserts: Vec::new(), } } #[doc(hidden)] @@ -2348,7 +2234,6 @@ impl Compiler { let id = TraceScalarId(self.traces.0.len()); self.traces.0.push(SimTrace { kind, - maybe_changed: true, state: (), last_state: (), }); @@ -2356,17 +2241,16 @@ impl Compiler { } fn make_trace_decl_child( &mut self, - instantiated_module_or_global: impl Into, + instantiated_module: InstantiatedModule, target: MakeTraceDeclTarget, name: Interned, source_location: SourceLocation, ) -> TraceDecl { - let instantiated_module_or_global = instantiated_module_or_global.into(); match target.ty() { CanonicalType::Array(ty) => { let elements = Interned::from_iter((0..ty.len()).map(|index| { self.make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, match target { MakeTraceDeclTarget::Expr(target) => MakeTraceDeclTarget::Expr( Expr::::from_canonical(target)[index], @@ -2399,18 +2283,12 @@ impl Compiler { } CanonicalType::Enum(ty) => { if ty.variants().iter().all(|v| v.ty.is_none()) { - self.make_trace_scalar( - instantiated_module_or_global, - target, - name, - source_location, - ) + self.make_trace_scalar(instantiated_module, target, name, source_location) } else { let flow = target.flow(); let location = match target { MakeTraceDeclTarget::Expr(target) => { - let compiled_value = - self.compile_expr(instantiated_module_or_global, target); + let compiled_value = self.compile_expr(instantiated_module, target); let compiled_value = self.compiled_expr_to_value(compiled_value, source_location); let discriminant = self.compile_enum_discriminant( @@ -2449,7 +2327,7 @@ impl Compiler { |(variant_index, variant)| { variant.ty.map(|variant_ty| { self.make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, match target { MakeTraceDeclTarget::Expr(target) => { MakeTraceDeclTarget::Expr( @@ -2494,7 +2372,7 @@ impl Compiler { let fields = Interned::from_iter(ty.fields().iter().zip(ty.field_offsets()).map( |(field, field_offset)| { self.make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, match target { MakeTraceDeclTarget::Expr(target) => { MakeTraceDeclTarget::Expr(Expr::field( @@ -2542,25 +2420,23 @@ impl Compiler { | CanonicalType::Reset(_) | CanonicalType::Clock(_) | CanonicalType::DynSimOnly(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::TraceAsString(_) => { - self.make_trace_scalar(instantiated_module_or_global, target, name, source_location) + | CanonicalType::PhantomConst(_) => { + self.make_trace_scalar(instantiated_module, target, name, source_location) } } } fn make_trace_decl( &mut self, - instantiated_module_or_global: impl Into, + instantiated_module: InstantiatedModule, target_base: TargetBase, ) -> TraceDecl { - let instantiated_module_or_global = instantiated_module_or_global.into(); let target = MakeTraceDeclTarget::Expr(target_base.to_expr()); match target_base { TargetBase::ModuleIO(module_io) => TraceModuleIO { name: module_io.name(), child: self .make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, module_io.name(), module_io.source_location(), @@ -2573,7 +2449,7 @@ impl Compiler { TargetBase::MemPort(mem_port) => { let name = Intern::intern_owned(mem_port.port_name().to_string()); let TraceDecl::Scope(TraceScope::Bundle(bundle)) = self.make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, name, mem_port.source_location(), @@ -2591,7 +2467,7 @@ impl Compiler { name: reg.name(), child: self .make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, reg.name(), reg.source_location(), @@ -2604,7 +2480,7 @@ impl Compiler { name: reg.name(), child: self .make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, reg.name(), reg.source_location(), @@ -2617,7 +2493,7 @@ impl Compiler { name: reg.name(), child: self .make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, reg.name(), reg.source_location(), @@ -2630,7 +2506,7 @@ impl Compiler { name: wire.name(), child: self .make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, wire.name(), wire.source_location(), @@ -2641,18 +2517,13 @@ impl Compiler { .into(), TargetBase::Instance(instance) => { let TraceDecl::Scope(TraceScope::Bundle(instance_io)) = self.make_trace_decl_child( - instantiated_module_or_global, + instantiated_module, target, instance.name(), instance.source_location(), ) else { unreachable!() }; - let InstantiatedModuleOrGlobal::InstantiatedModule(instantiated_module) = - instantiated_module_or_global - else { - unreachable!(); - }; let compiled_module = &self.modules[&InstantiatedModule::Child { parent: instantiated_module.intern(), instance: instance.intern(), @@ -2665,45 +2536,23 @@ impl Compiler { } .into() } - TargetBase::FormalInput(formal_input) => TraceFormalInput { - name: formal_input.name(), - child: self - .make_trace_decl_child( - instantiated_module_or_global, - target, - formal_input.name(), - formal_input.source_location(), - ) - .intern(), - formal_input, - } - .into(), - TargetBase::SimIoForGlobal(_) => { - unreachable!("Module is known to not contain SimIoForGlobal from validation") - } } } fn compile_value( &mut self, - target: TargetInInstantiatedModuleOrGlobal, + target: TargetInInstantiatedModule, ) -> CompiledValue { if let Some(&retval) = self.compiled_values.get(&target) { return retval; } - let mut new_global_io = None; - let retval = match target.target() { + let retval = match target.target { Target::Base(base) => { let unprefixed_layout = CompiledTypeLayout::get(base.canonical_ty()); - let layout = unprefixed_layout.with_prefixed_debug_names(&match target - .instantiated_module_or_global() - { - InstantiatedModuleOrGlobal::Global => { - format!("{:?}", base.target_name()) - } - InstantiatedModuleOrGlobal::InstantiatedModule(instantiated_module) => { - format!("{instantiated_module:?}.{:?}", base.target_name()) - } - }); + let layout = unprefixed_layout.with_prefixed_debug_names(&format!( + "{:?}.{:?}", + target.instantiated_module, + base.target_name() + )); let range = self.insns.allocate_variable(&layout.layout); let write = match *base { TargetBase::ModuleIO(_) @@ -2713,7 +2562,7 @@ impl Compiler { TargetBase::Reg(_) | TargetBase::RegSync(_) | TargetBase::RegAsync(_) => { let write_layout = unprefixed_layout.with_prefixed_debug_names(&format!( "{:?}.{:?}$next", - target.instantiated_module_or_global(), + target.instantiated_module, base.target_name() )); Some(( @@ -2721,16 +2570,6 @@ impl Compiler { self.insns.allocate_variable(&write_layout.layout), )) } - TargetBase::FormalInput(formal_input) => { - if self.global_io_set.insert(SimIoForGlobal::new(formal_input)) { - new_global_io = - Some((formal_input, target.instantiated_module_or_global(), *base)); - } - None - } - TargetBase::SimIoForGlobal(_) => unreachable!( - "Module is known to not contain SimIoForGlobal from validation" - ), }; CompiledValue { range, @@ -2739,10 +2578,10 @@ impl Compiler { } } Target::Child(target_child) => { - let parent = self.compile_value(TargetInInstantiatedModuleOrGlobal::new( - target.instantiated_module_or_global(), - *target_child.parent(), - )); + let parent = self.compile_value(TargetInInstantiatedModule { + instantiated_module: target.instantiated_module, + target: *target_child.parent(), + }); match *target_child.path_element() { TargetPathElement::BundleField(TargetPathBundleField { name }) => { parent.map_ty(Bundle::from_canonical).field_by_name(name) @@ -2751,22 +2590,10 @@ impl Compiler { parent.map_ty(Array::from_canonical).element(index) } TargetPathElement::DynArrayElement(_) => unreachable!(), - TargetPathElement::TraceAsStringInner(TargetPathTraceAsStringInner {}) => { - parent.map_ty(TraceAsString::from_canonical).inner() - } - TargetPathElement::ToTraceAsString(TargetPathToTraceAsString { ty }) => parent - .wrap_in_trace_as_string(ty) - .map_ty(|ty| ty.canonical()), } } }; self.compiled_values.insert(target, retval); - if let Some((new_global_io, instantiated_module_or_global, base)) = new_global_io { - let trace_decl = self.make_trace_decl(instantiated_module_or_global, base); - self.global_trace_decls.push(trace_decl); - self.global_io - .push((SimIoForGlobal::new(new_global_io), retval)); - } retval } fn add_assignment>( @@ -2781,20 +2608,18 @@ impl Compiler { } fn simple_big_expr_input( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, input: Expr, ) -> StatePartIndex { - let input = self.compile_expr(instantiated_module_or_global, input); - let input = self.compiled_expr_to_value( - input, - instantiated_module_or_global.leaf_module_source_location(), - ); + let input = self.compile_expr(instantiated_module, input); + let input = + self.compiled_expr_to_value(input, instantiated_module.leaf_module().source_location()); assert_eq!(input.range.len(), TypeLen::big_slot()); input.range.big_slots.start } fn compile_expr_helper( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, dest_ty: CanonicalType, make_insns: impl FnOnce(&mut Self, TypeIndexRange) -> Vec, ) -> CompiledValue { @@ -2809,24 +2634,24 @@ impl Compiler { self.add_assignment( Interned::default(), insns, - instantiated_module_or_global.leaf_module_source_location(), + instantiated_module.leaf_module().source_location(), ); retval } fn simple_nary_big_expr_helper( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, dest_ty: CanonicalType, make_insns: impl FnOnce(StatePartIndex) -> Vec, ) -> CompiledValue { - self.compile_expr_helper(instantiated_module_or_global, dest_ty, |_, dest| { + self.compile_expr_helper(instantiated_module, dest_ty, |_, dest| { assert_eq!(dest.len(), TypeLen::big_slot()); make_insns(dest.big_slots.start) }) } fn simple_nary_big_expr( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, dest_ty: CanonicalType, inputs: [Expr; N], make_insns: impl FnOnce( @@ -2834,9 +2659,8 @@ impl Compiler { [StatePartIndex; N], ) -> Vec, ) -> CompiledValue { - let inputs = - inputs.map(|input| self.simple_big_expr_input(instantiated_module_or_global, input)); - self.simple_nary_big_expr_helper(instantiated_module_or_global, dest_ty, |dest| { + let inputs = inputs.map(|input| self.simple_big_expr_input(instantiated_module, input)); + self.simple_nary_big_expr_helper(instantiated_module, dest_ty, |dest| { make_insns(dest, inputs) }) } @@ -2928,22 +2752,20 @@ impl Compiler { } fn compile_cast_scalar_to_bits( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, arg: Expr, cast_fn: impl FnOnce(Expr) -> Expr, ) -> CompiledValue { let arg = Expr::::from_canonical(arg); let retval = cast_fn(arg); - let retval = self.compile_expr(instantiated_module_or_global, Expr::canonical(retval)); - let retval = self.compiled_expr_to_value( - retval, - instantiated_module_or_global.leaf_module_source_location(), - ); + let retval = self.compile_expr(instantiated_module, Expr::canonical(retval)); + let retval = self + .compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location()); retval.map_ty(UInt::from_canonical) } fn compile_cast_aggregate_to_bits( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, parts: impl IntoIterator>, ) -> CompiledValue { let retval = parts @@ -2951,26 +2773,22 @@ impl Compiler { .map(|part| part.cast_to_bits()) .reduce(|accumulator, part| accumulator | (part << accumulator.ty().width)) .unwrap_or_else(|| UInt[0].zero().to_expr()); - let retval = self.compile_expr(instantiated_module_or_global, Expr::canonical(retval)); - let retval = self.compiled_expr_to_value( - retval, - instantiated_module_or_global.leaf_module_source_location(), - ); + let retval = self.compile_expr(instantiated_module, Expr::canonical(retval)); + let retval = self + .compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location()); retval.map_ty(UInt::from_canonical) } fn compile_cast_to_bits( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, expr: ops::CastToBits, ) -> CompiledValue { match expr.arg().ty() { CanonicalType::UInt(_) => { - self.compile_cast_scalar_to_bits(instantiated_module_or_global, expr.arg(), |arg| { - arg - }) + self.compile_cast_scalar_to_bits(instantiated_module, expr.arg(), |arg| arg) } CanonicalType::SInt(ty) => self.compile_cast_scalar_to_bits( - instantiated_module_or_global, + instantiated_module, expr.arg(), |arg: Expr| arg.cast_to(ty.as_same_width_uint()), ), @@ -2979,42 +2797,36 @@ impl Compiler { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) | CanonicalType::Clock(_) => self.compile_cast_scalar_to_bits( - instantiated_module_or_global, + instantiated_module, expr.arg(), |arg: Expr| arg.cast_to(UInt[1]), ), CanonicalType::Array(ty) => self.compile_cast_aggregate_to_bits( - instantiated_module_or_global, + instantiated_module, (0..ty.len()).map(|index| Expr::::from_canonical(expr.arg())[index]), ), CanonicalType::Enum(ty) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, UInt[ty.type_properties().bit_width].canonical(), [Expr::canonical(expr.arg())], |dest, [src]| vec![Insn::Copy { dest, src }], ) .map_ty(UInt::from_canonical), CanonicalType::Bundle(ty) => self.compile_cast_aggregate_to_bits( - instantiated_module_or_global, + instantiated_module, ty.fields().iter().map(|field| { Expr::field(Expr::::from_canonical(expr.arg()), &field.name) }), ), CanonicalType::PhantomConst(_) | CanonicalType::DynSimOnly(_) => { - self.compile_cast_aggregate_to_bits(instantiated_module_or_global, []) + self.compile_cast_aggregate_to_bits(instantiated_module, []) } - CanonicalType::TraceAsString(_) => self.compile_cast_to_bits( - instantiated_module_or_global, - ops::CastToBits::new( - ops::TraceAsStringAsInner::new(Expr::from_canonical(expr.arg())).to_expr(), - ), - ), } } fn compile_cast_bits_to_or_uninit( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, arg: Option>, ty: CanonicalType, ) -> CompiledValue { @@ -3043,7 +2855,7 @@ impl Compiler { } ty @ CanonicalType::Enum(_) => { return self.simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, ty, [Expr::canonical(arg.unwrap_or_else(|| { UInt::new_dyn(ty.bit_width()).zero().to_expr() @@ -3088,53 +2900,36 @@ impl Compiler { ), CanonicalType::PhantomConst(ty) => { if let Some(arg) = arg { - let _ = self.compile_expr(instantiated_module_or_global, Expr::canonical(arg)); + let _ = self.compile_expr(instantiated_module, Expr::canonical(arg)); } Expr::canonical(ty.to_expr()) } CanonicalType::DynSimOnly(ty) => { assert!(arg.is_none(), "can't cast bits to SimOnly"); - return self.compile_expr_helper( - instantiated_module_or_global, - ty.canonical(), - |_, dest| { - assert_eq!(dest.len(), TypeLen::sim_only_slot()); - vec![] - }, - ); + return self.compile_expr_helper(instantiated_module, ty.canonical(), |_, dest| { + assert_eq!(dest.len(), TypeLen::sim_only_slot()); + vec![] + }); } - CanonicalType::TraceAsString(ty) => Expr::canonical( - ops::ToTraceAsString::new( - match arg { - Some(arg) => arg.cast_bits_to(ty.inner_ty()), - None => ty.inner_ty().uninit(), - }, - ty, - ) - .to_expr(), - ), }; - let retval = self.compile_expr(instantiated_module_or_global, Expr::canonical(retval)); - self.compiled_expr_to_value( - retval, - instantiated_module_or_global.leaf_module_source_location(), - ) + let retval = self.compile_expr(instantiated_module, Expr::canonical(retval)); + self.compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location()) } fn compile_aggregate_literal( &mut self, - instantiated_module_or_global: InstantiatedModuleOrGlobal, + instantiated_module: InstantiatedModule, dest_ty: CanonicalType, inputs: Interned<[Expr]>, ) -> CompiledValue { - self.compile_expr_helper(instantiated_module_or_global, dest_ty, |this, dest| { + self.compile_expr_helper(instantiated_module, dest_ty, |this, dest| { let mut insns = Vec::new(); let mut offset = TypeIndex::ZERO; for input in inputs { - let input = this.compile_expr(instantiated_module_or_global, input); + let input = this.compile_expr(instantiated_module, input); let input = this .compiled_expr_to_value( input, - instantiated_module_or_global.leaf_module_source_location(), + instantiated_module.leaf_module().source_location(), ) .range; insns.extend( @@ -3147,10 +2942,9 @@ impl Compiler { } fn compile_expr( &mut self, - instantiated_module_or_global: impl Into, + instantiated_module: InstantiatedModule, expr: Expr, ) -> CompiledExpr { - let instantiated_module_or_global = instantiated_module_or_global.into(); if let Some(&retval) = self.compiled_exprs.get(&expr) { return retval; } @@ -3168,7 +2962,6 @@ impl Compiler { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => unreachable!(), - CanonicalType::TraceAsString(_) => unreachable!(), }; let dest_signed = match expr.ty() { CanonicalType::UInt(_) => false, @@ -3183,34 +2976,31 @@ impl Compiler { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => unreachable!(), - CanonicalType::TraceAsString(_) => unreachable!(), }; - self.simple_nary_big_expr( - instantiated_module_or_global, - expr.ty(), - [arg], - |dest, [src]| match (src_signed, dest_signed) { - (false, false) | (true, true) => { - vec![Insn::Copy { dest, src }] - } - (false, true) => vec![Insn::CastToSInt { - dest, - src, - dest_width: 1, - }], - (true, false) => vec![Insn::CastToUInt { - dest, - src, - dest_width: 1, - }], - }, - ) + self.simple_nary_big_expr(instantiated_module, expr.ty(), [arg], |dest, [src]| match ( + src_signed, + dest_signed, + ) { + (false, false) | (true, true) => { + vec![Insn::Copy { dest, src }] + } + (false, true) => vec![Insn::CastToSInt { + dest, + src, + dest_width: 1, + }], + (true, false) => vec![Insn::CastToUInt { + dest, + src, + dest_width: 1, + }], + }) .into() }; let retval: CompiledExpr<_> = match *Expr::expr_enum(expr) { ExprEnum::UIntLiteral(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [], |dest, []| { @@ -3223,7 +3013,7 @@ impl Compiler { .into(), ExprEnum::SIntLiteral(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [], |dest, []| { @@ -3235,38 +3025,21 @@ impl Compiler { ) .into(), ExprEnum::BoolLiteral(expr) => self - .simple_nary_big_expr( - instantiated_module_or_global, - Bool.canonical(), - [], - |dest, []| { - vec![Insn::Const { - dest, - value: BigInt::from(expr).intern_sized(), - }] - }, - ) + .simple_nary_big_expr(instantiated_module, Bool.canonical(), [], |dest, []| { + vec![Insn::Const { + dest, + value: BigInt::from(expr).intern_sized(), + }] + }) .into(), ExprEnum::PhantomConst(_) => self - .compile_aggregate_literal( - instantiated_module_or_global, - expr.ty(), - Interned::default(), - ) + .compile_aggregate_literal(instantiated_module, expr.ty(), Interned::default()) .into(), ExprEnum::BundleLiteral(literal) => self - .compile_aggregate_literal( - instantiated_module_or_global, - expr.ty(), - literal.field_values(), - ) + .compile_aggregate_literal(instantiated_module, expr.ty(), literal.field_values()) .into(), ExprEnum::ArrayLiteral(literal) => self - .compile_aggregate_literal( - instantiated_module_or_global, - expr.ty(), - literal.element_values(), - ) + .compile_aggregate_literal(instantiated_module, expr.ty(), literal.element_values()) .into(), ExprEnum::EnumLiteral(expr) => { let enum_bits_ty = UInt[expr.ty().type_properties().bit_width]; @@ -3284,16 +3057,16 @@ impl Compiler { .to_expr() }; self.compile_expr( - instantiated_module_or_global, + instantiated_module, enum_bits.cast_bits_to(expr.ty().canonical()), ) } ExprEnum::Uninit(expr) => self - .compile_cast_bits_to_or_uninit(instantiated_module_or_global, None, expr.ty()) + .compile_cast_bits_to_or_uninit(instantiated_module, None, expr.ty()) .into(), ExprEnum::NotU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.arg().ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3307,7 +3080,7 @@ impl Compiler { .into(), ExprEnum::NotS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.arg().ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| vec![Insn::NotS { dest, src }], @@ -3315,7 +3088,7 @@ impl Compiler { .into(), ExprEnum::NotB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.arg().ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3329,7 +3102,7 @@ impl Compiler { .into(), ExprEnum::Neg(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| vec![Insn::Neg { dest, src }], @@ -3337,7 +3110,7 @@ impl Compiler { .into(), ExprEnum::BitAndU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }], @@ -3345,7 +3118,7 @@ impl Compiler { .into(), ExprEnum::BitAndS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }], @@ -3353,7 +3126,7 @@ impl Compiler { .into(), ExprEnum::BitAndB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }], @@ -3361,7 +3134,7 @@ impl Compiler { .into(), ExprEnum::BitOrU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }], @@ -3369,7 +3142,7 @@ impl Compiler { .into(), ExprEnum::BitOrS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }], @@ -3377,7 +3150,7 @@ impl Compiler { .into(), ExprEnum::BitOrB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }], @@ -3385,7 +3158,7 @@ impl Compiler { .into(), ExprEnum::BitXorU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }], @@ -3393,7 +3166,7 @@ impl Compiler { .into(), ExprEnum::BitXorS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }], @@ -3401,7 +3174,7 @@ impl Compiler { .into(), ExprEnum::BitXorB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }], @@ -3409,7 +3182,7 @@ impl Compiler { .into(), ExprEnum::AddU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }], @@ -3417,7 +3190,7 @@ impl Compiler { .into(), ExprEnum::AddS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }], @@ -3425,7 +3198,7 @@ impl Compiler { .into(), ExprEnum::SubU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| { @@ -3440,7 +3213,7 @@ impl Compiler { .into(), ExprEnum::SubS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::SubS { dest, lhs, rhs }], @@ -3448,7 +3221,7 @@ impl Compiler { .into(), ExprEnum::MulU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }], @@ -3456,7 +3229,7 @@ impl Compiler { .into(), ExprEnum::MulS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }], @@ -3464,7 +3237,7 @@ impl Compiler { .into(), ExprEnum::DivU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }], @@ -3472,7 +3245,7 @@ impl Compiler { .into(), ExprEnum::DivS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }], @@ -3480,7 +3253,7 @@ impl Compiler { .into(), ExprEnum::RemU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }], @@ -3488,7 +3261,7 @@ impl Compiler { .into(), ExprEnum::RemS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }], @@ -3496,7 +3269,7 @@ impl Compiler { .into(), ExprEnum::DynShlU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }], @@ -3504,7 +3277,7 @@ impl Compiler { .into(), ExprEnum::DynShlS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }], @@ -3512,7 +3285,7 @@ impl Compiler { .into(), ExprEnum::DynShrU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }], @@ -3520,7 +3293,7 @@ impl Compiler { .into(), ExprEnum::DynShrS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }], @@ -3528,7 +3301,7 @@ impl Compiler { .into(), ExprEnum::FixedShlU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs())], |dest, [lhs]| { @@ -3542,7 +3315,7 @@ impl Compiler { .into(), ExprEnum::FixedShlS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs())], |dest, [lhs]| { @@ -3556,7 +3329,7 @@ impl Compiler { .into(), ExprEnum::FixedShrU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs())], |dest, [lhs]| { @@ -3570,7 +3343,7 @@ impl Compiler { .into(), ExprEnum::FixedShrS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.lhs())], |dest, [lhs]| { @@ -3584,7 +3357,7 @@ impl Compiler { .into(), ExprEnum::CmpLtB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }], @@ -3592,7 +3365,7 @@ impl Compiler { .into(), ExprEnum::CmpLeB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }], @@ -3600,7 +3373,7 @@ impl Compiler { .into(), ExprEnum::CmpGtB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), // swap both comparison direction and lhs/rhs [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())], @@ -3609,7 +3382,7 @@ impl Compiler { .into(), ExprEnum::CmpGeB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), // swap both comparison direction and lhs/rhs [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())], @@ -3618,7 +3391,7 @@ impl Compiler { .into(), ExprEnum::CmpEqB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }], @@ -3626,7 +3399,7 @@ impl Compiler { .into(), ExprEnum::CmpNeB(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }], @@ -3634,7 +3407,7 @@ impl Compiler { .into(), ExprEnum::CmpLtU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }], @@ -3642,7 +3415,7 @@ impl Compiler { .into(), ExprEnum::CmpLeU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }], @@ -3650,7 +3423,7 @@ impl Compiler { .into(), ExprEnum::CmpGtU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), // swap both comparison direction and lhs/rhs [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())], @@ -3659,7 +3432,7 @@ impl Compiler { .into(), ExprEnum::CmpGeU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), // swap both comparison direction and lhs/rhs [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())], @@ -3668,7 +3441,7 @@ impl Compiler { .into(), ExprEnum::CmpEqU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }], @@ -3676,7 +3449,7 @@ impl Compiler { .into(), ExprEnum::CmpNeU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }], @@ -3684,7 +3457,7 @@ impl Compiler { .into(), ExprEnum::CmpLtS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }], @@ -3692,7 +3465,7 @@ impl Compiler { .into(), ExprEnum::CmpLeS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }], @@ -3700,7 +3473,7 @@ impl Compiler { .into(), ExprEnum::CmpGtS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), // swap both comparison direction and lhs/rhs [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())], @@ -3709,7 +3482,7 @@ impl Compiler { .into(), ExprEnum::CmpGeS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), // swap both comparison direction and lhs/rhs [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())], @@ -3718,7 +3491,7 @@ impl Compiler { .into(), ExprEnum::CmpEqS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }], @@ -3726,7 +3499,7 @@ impl Compiler { .into(), ExprEnum::CmpNeS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, Bool.canonical(), [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())], |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }], @@ -3734,7 +3507,7 @@ impl Compiler { .into(), ExprEnum::CastUIntToUInt(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3748,7 +3521,7 @@ impl Compiler { .into(), ExprEnum::CastUIntToSInt(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3762,7 +3535,7 @@ impl Compiler { .into(), ExprEnum::CastSIntToUInt(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3776,7 +3549,7 @@ impl Compiler { .into(), ExprEnum::CastSIntToSInt(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, expr.ty().canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3816,90 +3589,76 @@ impl Compiler { ExprEnum::CastClockToUInt(expr) => cast_bit(Expr::canonical(expr.arg())), ExprEnum::CastClockToSInt(expr) => cast_bit(Expr::canonical(expr.arg())), ExprEnum::FieldAccess(expr) => self - .compile_expr(instantiated_module_or_global, Expr::canonical(expr.base())) + .compile_expr(instantiated_module, Expr::canonical(expr.base())) .map_ty(Bundle::from_canonical) .field_by_index(expr.field_index()), ExprEnum::VariantAccess(variant_access) => { let start = variant_access.base().ty().discriminant_bit_width(); let len = expr.ty().bit_width(); self.compile_expr( - instantiated_module_or_global, + instantiated_module, variant_access.base().cast_to_bits()[start..start + len] .cast_bits_to(expr.ty()), ) } ExprEnum::ArrayIndex(expr) => self - .compile_expr(instantiated_module_or_global, Expr::canonical(expr.base())) + .compile_expr(instantiated_module, Expr::canonical(expr.base())) .map_ty(Array::from_canonical) .element(expr.element_index()), ExprEnum::DynArrayIndex(expr) => { - let element_index = self.compile_expr( - instantiated_module_or_global, - Expr::canonical(expr.element_index()), - ); + let element_index = + self.compile_expr(instantiated_module, Expr::canonical(expr.element_index())); let element_index = self.compiled_expr_to_value( element_index, - instantiated_module_or_global.leaf_module_source_location(), + instantiated_module.leaf_module().source_location(), ); let index_slot = self.compiled_value_to_dyn_array_index( element_index.map_ty(UInt::from_canonical), - instantiated_module_or_global.leaf_module_source_location(), + instantiated_module.leaf_module().source_location(), ); - self.compile_expr(instantiated_module_or_global, Expr::canonical(expr.base())) + self.compile_expr(instantiated_module, Expr::canonical(expr.base())) .map_ty(Array::from_canonical) .element_dyn(index_slot) } ExprEnum::ReduceBitAndU(expr) => if expr.arg().ty().width() == 0 { - self.compile_expr( - instantiated_module_or_global, - Expr::canonical(true.to_expr()), - ) + self.compile_expr(instantiated_module, Expr::canonical(true.to_expr())) } else { self.compile_expr( - instantiated_module_or_global, + instantiated_module, Expr::canonical(expr.arg().cmp_eq(expr.arg().ty().from_int_wrapping(-1))), ) } .into(), ExprEnum::ReduceBitAndS(expr) => if expr.arg().ty().width() == 0 { - self.compile_expr( - instantiated_module_or_global, - Expr::canonical(true.to_expr()), - ) + self.compile_expr(instantiated_module, Expr::canonical(true.to_expr())) } else { self.compile_expr( - instantiated_module_or_global, + instantiated_module, Expr::canonical(expr.arg().cmp_eq(expr.arg().ty().from_int_wrapping(-1))), ) } .into(), ExprEnum::ReduceBitOrU(expr) => if expr.arg().ty().width() == 0 { - self.compile_expr( - instantiated_module_or_global, - Expr::canonical(false.to_expr()), - ) + self.compile_expr(instantiated_module, Expr::canonical(false.to_expr())) } else { self.compile_expr( - instantiated_module_or_global, + instantiated_module, Expr::canonical(expr.arg().cmp_ne(expr.arg().ty().from_int_wrapping(0))), ) } .into(), ExprEnum::ReduceBitOrS(expr) => if expr.arg().ty().width() == 0 { - self.compile_expr( - instantiated_module_or_global, - Expr::canonical(false.to_expr()), - ) + self.compile_expr(instantiated_module, Expr::canonical(false.to_expr())) } else { self.compile_expr( - instantiated_module_or_global, + instantiated_module, Expr::canonical(expr.arg().cmp_ne(expr.arg().ty().from_int_wrapping(0))), ) } .into(), ExprEnum::ReduceBitXorU(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, UInt::<1>::TYPE.canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3913,7 +3672,7 @@ impl Compiler { .into(), ExprEnum::ReduceBitXorS(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, UInt::<1>::TYPE.canonical(), [Expr::canonical(expr.arg())], |dest, [src]| { @@ -3927,7 +3686,7 @@ impl Compiler { .into(), ExprEnum::SliceUInt(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, UInt::new_dyn(expr.range().len()).canonical(), [Expr::canonical(expr.base())], |dest, [src]| { @@ -3942,7 +3701,7 @@ impl Compiler { .into(), ExprEnum::SliceSInt(expr) => self .simple_nary_big_expr( - instantiated_module_or_global, + instantiated_module, UInt::new_dyn(expr.range().len()).canonical(), [Expr::canonical(expr.base())], |dest, [src]| { @@ -3956,75 +3715,54 @@ impl Compiler { ) .into(), ExprEnum::CastToBits(expr) => self - .compile_cast_to_bits(instantiated_module_or_global, expr) + .compile_cast_to_bits(instantiated_module, expr) .map_ty(CanonicalType::UInt) .into(), ExprEnum::CastBitsTo(expr) => self - .compile_cast_bits_to_or_uninit( - instantiated_module_or_global, - Some(expr.arg()), - expr.ty(), - ) + .compile_cast_bits_to_or_uninit(instantiated_module, Some(expr.arg()), expr.ty()) .into(), - ExprEnum::ToTraceAsString(expr) => self - .compile_expr(instantiated_module_or_global, expr.inner()) - .wrap_in_trace_as_string(expr.ty()) - .map_ty(|ty| ty.canonical()), - ExprEnum::TraceAsStringAsInner(expr) => self - .compile_expr(instantiated_module_or_global, Expr::canonical(expr.arg())) - .map_ty(TraceAsString::from_canonical) - .inner(), ExprEnum::ModuleIO(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), ExprEnum::Instance(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), ExprEnum::Wire(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), ExprEnum::Reg(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), ExprEnum::RegSync(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), ExprEnum::RegAsync(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), ExprEnum::MemPort(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) + .compile_value(TargetInInstantiatedModule { + instantiated_module, + target: expr.into(), + }) .into(), - ExprEnum::FormalInput(expr) => self - .compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module_or_global, - expr.into(), - )) - .into(), - ExprEnum::SimIoForGlobal(_) => { - unreachable!("Module is known to not contain SimIoForGlobal from validation"); - } }; self.compiled_exprs.insert(expr, retval); retval @@ -4130,31 +3868,15 @@ impl Compiler { CanonicalType::DynSimOnly(_) => { unreachable!("DynSimOnly mismatch"); } - CanonicalType::TraceAsString(_) => { - let lhs = Expr::::from_canonical(lhs); - let rhs = Expr::::from_canonical(rhs); - let lhs_expr = ops::TraceAsStringAsInner::new(lhs).to_expr(); - let rhs_expr = ops::TraceAsStringAsInner::new(rhs).to_expr(); - return self.compile_connect( - lhs_instantiated_module, - lhs_conditions, - lhs_expr, - rhs_instantiated_module, - rhs_conditions, - rhs_expr, - source_location, - ); - } } } let Some(target) = lhs.target() else { unreachable!("connect lhs must have target"); }; - let lhs_decl_conditions = self.decl_conditions - [&TargetInInstantiatedModuleOrGlobal::from_target( - lhs_instantiated_module, - target.base().into(), - )]; + let lhs_decl_conditions = self.decl_conditions[&TargetInInstantiatedModule { + instantiated_module: lhs_instantiated_module, + target: target.base().into(), + }]; let lhs = self.compile_expr(lhs_instantiated_module, lhs); let rhs = self.compile_expr(rhs_instantiated_module, rhs); let rhs = self.compiled_expr_to_value(rhs, source_location); @@ -4395,8 +4117,10 @@ impl Compiler { StmtDeclaration::RegAsync(v) => v.reg.into(), StmtDeclaration::Instance(v) => v.instance.into(), }; - let target = - TargetInInstantiatedModuleOrGlobal::from_target(*parent_module, target_base.into()); + let target = TargetInInstantiatedModule { + instantiated_module: *parent_module, + target: target_base.into(), + }; self.decl_conditions.insert(target, conditions); let compiled_value = self.compile_value(target); match declaration { @@ -4460,56 +4184,6 @@ impl Compiler { } self.make_trace_decl(*parent_module, target_base) } - fn compile_stmt_formal( - &mut self, - stmt_formal: StmtFormal, - instantiated_module: Interned, - conditions: Interned<[Cond]>, - ) { - let StmtFormal { - kind, - clk, - pred, - en, - text: _, - source_location, - } = stmt_formal; - let clk = self.compile_expr(*instantiated_module, Expr::canonical(clk)); - let clk = self - .compiled_expr_to_value(clk, source_location) - .map_ty(Clock::from_canonical); - let clk = self.compile_clock(clk, source_location); - let pred = self.compile_expr(*instantiated_module, Expr::canonical(pred | !en)); - let pred = self.compiled_expr_to_value(pred, source_location); - let pred_layout = CompiledTypeLayout::get(Bool.canonical()); - let pred_wire = CompiledValue { - layout: pred_layout, - range: self.insns.allocate_variable(&pred_layout.layout), - write: None, - }; - let true_value = self.compile_expr(*instantiated_module, Expr::canonical(true.to_expr())); - let true_value = self.compiled_expr_to_value(true_value, source_location); - self.compile_simple_connect( - [].intern_slice(), - pred_wire.into(), - true_value, - source_location, - ); - self.compile_simple_connect(conditions, pred_wire.into(), pred, source_location); - match kind { - FormalKind::Assert | FormalKind::Assume => {} - FormalKind::Cover => todo!("simulating hdl_cover isn't implemented: {stmt_formal:?}"), - } - let pred = self.compiled_value_bool_dest_is_small(pred_wire, source_location); - self.asserts.push(Assert { - compiled_assert: CompiledAssert { - instantiated_module, - stmt_formal, - }, - clk_triggered: clk.clk_triggered, - pred, - }); - } fn allocate_delay_chain( &mut self, len: usize, @@ -4569,8 +4243,6 @@ impl Compiler { mut read: Option>, mut write: Option>, ) { - let data_layout = data_layout.unwrap_transparent_types(); - let mask_layout = mask_layout.unwrap_transparent_types(); match data_layout.body { CompiledTypeLayoutBody::Scalar => { let CompiledTypeLayoutBody::Scalar = mask_layout.body else { @@ -4589,7 +4261,6 @@ impl Compiler { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::DynSimOnly(_) => false, - CanonicalType::TraceAsString(_) => unreachable!(), }; let width = data_layout.ty.bit_width(); if let Some(MemoryPortReadInsns { @@ -4812,9 +4483,6 @@ impl Compiler { start = start + field.ty.ty.bit_width(); } } - CompiledTypeLayoutBody::Transparent { .. } => { - unreachable!("handled by unwrap_transparent_types") - } } } fn compile_memory_port_rw( @@ -5011,10 +4679,10 @@ impl Compiler { .iter() .map(|&port| { let target_base = TargetBase::MemPort(port); - let target = TargetInInstantiatedModuleOrGlobal::from_target( + let target = TargetInInstantiatedModule { instantiated_module, - target_base.into(), - ); + target: target_base.into(), + }; self.decl_conditions.insert(target, conditions); let TraceDecl::Scope(TraceScope::MemPort(trace_port)) = self.make_trace_decl(instantiated_module, target_base) @@ -5263,9 +4931,7 @@ impl Compiler { rhs, source_location, ), - Stmt::Formal(stmt_formal) => { - self.compile_stmt_formal(stmt_formal, parent_module, conditions); - } + Stmt::Formal(StmtFormal { .. }) => todo!("implement simulating formal statements"), Stmt::If(StmtIf { cond, source_location, @@ -5332,8 +4998,10 @@ impl Compiler { instantiated_module: InstantiatedModule, clock_for_past: Target, ) -> ExternModuleClockForPast { - let clock_for_past = - TargetInInstantiatedModuleOrGlobal::from_target(instantiated_module, clock_for_past); + let clock_for_past = TargetInInstantiatedModule { + instantiated_module, + target: clock_for_past, + }; let clock_for_past = self .compile_value(clock_for_past) .map_ty(Clock::from_canonical); @@ -5377,11 +5045,10 @@ impl Compiler { module_io, }| { let target_base = TargetBase::from(module_io); - let current = - self.compile_value(TargetInInstantiatedModuleOrGlobal::from_target( - instantiated_module, - target_base.into(), - )); + let current = self.compile_value(TargetInInstantiatedModule { + instantiated_module, + target: target_base.into(), + }); let unprefixed_layout = CompiledTypeLayout::get(module_io.ty()); let past_layout = unprefixed_layout.with_prefixed_debug_names(&format!( "{module_prefix}{:?}$past({trimmed_clock_for_past_debug_name})", @@ -5419,10 +5086,10 @@ impl Compiler { annotations: _, module_io, }| { - let target = TargetInInstantiatedModuleOrGlobal::from_target( - *module, - Target::from(module_io), - ); + let target = TargetInInstantiatedModule { + instantiated_module: *module, + target: Target::from(module_io), + }; self.decl_conditions.insert(target, Interned::default()); trace_decls.push(self.make_trace_decl(*module, module_io.into())); self.compile_value(target) @@ -5619,51 +5286,27 @@ impl Compiler { } } } - fn process_asserts(&mut self) { - for (assert_index, assert) in self.asserts.iter().enumerate() { - let Assert { - ref compiled_assert, - clk_triggered, - pred, - } = *assert; - self.insns.push( - Insn::Assert { - clk_triggered, - pred, - assert_index, - }, - compiled_assert.stmt_formal.source_location, - ); - } - } pub fn compile(mut self) -> Compiled { - let mut base_module = + let base_module = *self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized()); self.process_assignments(); self.process_registers(); self.process_memories(); - self.process_asserts(); let clocks_triggered = self.process_clocks(); self.insns .push(Insn::Return, self.base_module.source_location()); - base_module.trace_decls.children = self - .global_trace_decls - .into_iter() - .chain(base_module.trace_decls.children) - .collect(); Compiled { insns: Insns::from(self.insns).intern_sized(), base_module, extern_modules: Intern::intern_owned(self.extern_modules), io: Instance::new_unchecked( ScopedNameId( - NameId("".intern(), Id::new()).into(), + NameId("".intern(), Id::new()), self.original_base_module.name_id(), ), self.original_base_module, self.original_base_module.source_location(), ), - global_io: Interned::from_iter(self.global_io), traces: SimTraces(Intern::intern_owned(self.traces.0)), trace_memories: Interned::from_iter(self.memories.iter().map( |&Memory { @@ -5674,11 +5317,6 @@ impl Compiler { }| (memory, trace), )), clocks_triggered, - asserts: Interned::from_iter( - self.asserts - .into_iter() - .map(|assert| assert.compiled_assert), - ), } } } @@ -5695,11 +5333,9 @@ pub struct Compiled { pub(crate) base_module: CompiledModule, pub(crate) extern_modules: Interned<[CompiledExternModule]>, pub(crate) io: Instance, - pub(crate) global_io: Interned<[(SimIoForGlobal, CompiledValue)]>, pub(crate) traces: SimTraces]>>, pub(crate) trace_memories: Interned<[(StatePartIndex, TraceMem)]>, pub(crate) clocks_triggered: Interned<[StatePartIndex]>, - pub(crate) asserts: Interned<[CompiledAssert]>, } impl Compiled { @@ -5712,22 +5348,18 @@ impl Compiled { base_module, extern_modules, io, - global_io, traces, trace_memories, clocks_triggered, - asserts, } = self; Compiled { insns, base_module, extern_modules, io: Instance::from_canonical(io.canonical()), - global_io, traces, trace_memories, clocks_triggered, - asserts, } } pub fn from_canonical(canonical: Compiled) -> Self { @@ -5736,22 +5368,18 @@ impl Compiled { base_module, extern_modules, io, - global_io, traces, trace_memories, clocks_triggered, - asserts, } = canonical; Self { insns, base_module, extern_modules, io: Instance::from_canonical(io.canonical()), - global_io, traces, trace_memories, clocks_triggered, - asserts, } } } diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index ee3331f..2b121b5 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -6,9 +6,9 @@ use crate::{ int::{BoolOrIntType, SInt, UInt}, intern::{Intern, Interned, Memoize}, sim::interpreter::parts::{ - StateLayout, StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots, - StatePartKindMemories, StatePartKindSimOnlySlots, StatePartKindSmallSlots, StatePartLen, - TypeIndexRange, TypeLayout, get_state_part_kinds, + StateLayout, StatePartIndex, StatePartKind, StatePartKindBigSlots, StatePartKindMemories, + StatePartKindSimOnlySlots, StatePartKindSmallSlots, StatePartLen, TypeIndexRange, + TypeLayout, get_state_part_kinds, }, source_location::SourceLocation, util::{HashMap, HashSet}, @@ -17,11 +17,12 @@ use bitvec::slice::BitSlice; use num_bigint::BigInt; use num_traits::{One, Signed, ToPrimitive, Zero}; use std::{ + borrow::BorrowMut, convert::Infallible, fmt::{self, Write}, hash::Hash, marker::PhantomData, - ops::{ControlFlow, Deref, Index, IndexMut}, + ops::{ControlFlow, Deref, DerefMut, Index, IndexMut}, }; use vec_map::VecMap; @@ -914,21 +915,6 @@ impl StatePart { value: K::borrow_state(&mut self.value), } } - pub(crate) fn state_index_fetch_maybe_modified_flag( - &self, - part_index: StatePartIndex, - ) -> bool { - K::state_index_fetch_maybe_modified_flag(&self.value, part_index) - } - pub(crate) fn state_index_range_fetch_maybe_modified_flags( - &self, - part_index_range: StatePartIndexRange, - ) -> bool { - K::state_index_range_fetch_maybe_modified_flags(&self.value, part_index_range) - } - pub(crate) fn clear_all_maybe_modified_flags(&mut self) { - K::clear_all_maybe_modified_flags(&mut self.value) - } } #[derive(Clone, PartialEq, Eq, Hash, Debug)] @@ -936,38 +922,56 @@ pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> { pub(crate) value: K::BorrowedState<'a>, } -impl BorrowedStatePart<'_, K> { +impl< + 'a, + K: StatePartKind< + BorrowedState<'a>: DerefMut + BorrowMut<[T]>>, + >, + T, +> BorrowedStatePart<'a, K> +{ pub(crate) fn get_disjoint_mut( &mut self, indexes: [StatePartIndex; N], - ) -> [&mut K::StateElement; N] { - K::borrowed_state_get_disjoint_mut(&mut self.value, indexes) + ) -> [&mut T; N] { + (*self.value) + .borrow_mut() + .get_disjoint_mut(indexes.map(|v| v.value as usize)) + .expect("indexes are disjoint") } } -impl Index> for StatePart { - type Output = K::StateElement; +impl>>, T> Index> + for StatePart +{ + type Output = T; fn index(&self, index: StatePartIndex) -> &Self::Output { - K::state_index(&self.value, index) + &self.value[index.value as usize] } } -impl IndexMut> for StatePart { +impl>>, T> + IndexMut> for StatePart +{ fn index_mut(&mut self, index: StatePartIndex) -> &mut Self::Output { - K::state_index_mut(&mut self.value, index) + &mut self.value[index.value as usize] } } -impl Index> for BorrowedStatePart<'_, K> { - type Output = K::StateElement; +impl<'a, K: StatePartKind: Deref>>, T> + Index> for BorrowedStatePart<'a, K> +{ + type Output = T; fn index(&self, index: StatePartIndex) -> &Self::Output { - K::borrowed_state_index(&self.value, index) + &self.value[index.value as usize] } } -impl IndexMut> for BorrowedStatePart<'_, K> { +impl<'a, K: StatePartKind: DerefMut>>, T> + IndexMut> for BorrowedStatePart<'a, K> +{ fn index_mut(&mut self, index: StatePartIndex) -> &mut Self::Output { - K::borrowed_state_index_mut(&mut self.value, index) + &mut self.value[index.value as usize] } } @@ -980,7 +984,6 @@ macro_rules! make_state { pub(crate) insns: Interned>, pub(crate) pc: usize, pub(crate) memory_write_log: Vec<(StatePartIndex, usize)>, - pub(crate) assert_failed_log: Vec, $(pub(crate) $state_plural_field: StatePart<$state_kind>,)* $(pub(crate) $type_plural_field: StatePart<$type_kind>,)* } @@ -991,7 +994,6 @@ macro_rules! make_state { insns: _, pc, memory_write_log, - assert_failed_log, $($state_plural_field,)* $($type_plural_field,)* } = self; @@ -999,7 +1001,6 @@ macro_rules! make_state { .field("insns", &InsnsOfState(self)) .field("pc", pc) .field("memory_write_log", memory_write_log) - .field("assert_failed_log", assert_failed_log) $(.field(stringify!($state_plural_field), $state_plural_field))* $(.field(stringify!($type_plural_field), $type_plural_field))* .finish() @@ -1012,7 +1013,6 @@ macro_rules! make_state { insns, pc: 0, memory_write_log: Vec::with_capacity(32), - assert_failed_log: Vec::new(), $($state_plural_field: StatePart::new(&insns.state_layout.$state_plural_field.layout_data),)* $($type_plural_field: StatePart::new(&insns.state_layout.ty.$type_plural_field.layout_data),)* } @@ -1024,20 +1024,10 @@ macro_rules! make_state { pc: self.pc, orig_pc: &mut self.pc, memory_write_log: &mut self.memory_write_log, - assert_failed_log: &mut self.assert_failed_log, $($state_plural_field: self.$state_plural_field.borrow(),)* $($type_plural_field: self.$type_plural_field.borrow(),)* } } - pub(crate) fn type_index_range_fetch_maybe_modified_flags(&self, range: TypeIndexRange) -> bool { - $(self.$type_plural_field.state_index_range_fetch_maybe_modified_flags( - range.$type_plural_field, - ))||* - } - pub(crate) fn clear_all_maybe_modified_flags(&mut self) { - $(self.$state_plural_field.clear_all_maybe_modified_flags();)* - $(self.$type_plural_field.clear_all_maybe_modified_flags();)* - } } #[derive(Debug)] @@ -1047,7 +1037,6 @@ macro_rules! make_state { pub(crate) orig_pc: &'a mut usize, pub(crate) pc: usize, pub(crate) memory_write_log: &'a mut Vec<(StatePartIndex, usize)>, - pub(crate) assert_failed_log: &'a mut Vec, $(pub(crate) $state_plural_field: BorrowedStatePart<'a, $state_kind>,)* $(pub(crate) $type_plural_field: BorrowedStatePart<'a, $type_kind>,)* } @@ -1305,7 +1294,6 @@ impl State { insns: _, pc, memory_write_log: _, - assert_failed_log: _, memories: _, small_slots: _, big_slots: _, @@ -1345,10 +1333,6 @@ impl BorrowedState<'_> { self.memory_write_log.push(log_entry); } } - #[cold] - fn assert_failed(&mut self, assert_index: usize) { - self.assert_failed_log.push(assert_index); - } } fn bigint_pow2(width: usize) -> Interned { @@ -2116,19 +2100,6 @@ impl_insns! { state.log_memory_write(memory, addr); next!(); } - Assert { - #[kind = Input] - clk_triggered: StatePartIndex, - #[kind = Input] - pred: StatePartIndex, - #[kind = Immediate] - assert_index: usize, - } => { - if state.small_slots[clk_triggered] != 0 && state.small_slots[pred] == 0 { - state.assert_failed(assert_index); - } - next!(); - } Return => { break RunResult::Return(()); } diff --git a/crates/fayalite/src/sim/interpreter/parts.rs b/crates/fayalite/src/sim/interpreter/parts.rs index 0d98c06..75427c9 100644 --- a/crates/fayalite/src/sim/interpreter/parts.rs +++ b/crates/fayalite/src/sim/interpreter/parts.rs @@ -236,7 +236,6 @@ pub(crate) trait StatePartKind: type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy; type State: fmt::Debug + 'static + Clone; type BorrowedState<'a>: 'a; - type StateElement; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State; fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>; fn part_debug_data( @@ -248,35 +247,6 @@ pub(crate) trait StatePartKind: index: StatePartIndex, f: &mut impl fmt::Write, ) -> fmt::Result; - fn state_index<'a>( - state: &'a Self::State, - part_index: StatePartIndex, - ) -> &'a Self::StateElement; - fn state_index_mut<'a>( - state: &'a mut Self::State, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement; - fn state_index_fetch_maybe_modified_flag( - state: &Self::State, - part_index: StatePartIndex, - ) -> bool; - fn state_index_range_fetch_maybe_modified_flags( - state: &Self::State, - part_index_range: StatePartIndexRange, - ) -> bool; - fn clear_all_maybe_modified_flags(state: &mut Self::State); - fn borrowed_state_index<'a, 'b>( - state: &'a Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a Self::StateElement; - fn borrowed_state_index_mut<'a, 'b>( - state: &'a mut Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement; - fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( - state: &'a mut Self::BorrowedState<'b>, - part_indexes: [StatePartIndex; N], - ) -> [&'a mut Self::StateElement; N]; } macro_rules! make_state_part_kinds { @@ -302,7 +272,6 @@ impl StatePartKind for StatePartKindMemories { type LayoutData = MemoryData>; type State = Box<[MemoryData]>; type BorrowedState<'a> = &'a mut [MemoryData]; - type StateElement = MemoryData; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { layout_data .iter() @@ -328,95 +297,19 @@ impl StatePartKind for StatePartKindMemories { ) -> fmt::Result { write!(f, "{:#?}", &state.memories[index]) } - fn state_index<'a>( - state: &'a Self::State, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state[part_index.as_usize()] - } - fn state_index_mut<'a>( - state: &'a mut Self::State, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - &mut state[part_index.as_usize()] - } - fn state_index_fetch_maybe_modified_flag( - _state: &Self::State, - _part_index: StatePartIndex, - ) -> bool { - true - } - fn state_index_range_fetch_maybe_modified_flags( - _state: &Self::State, - part_index_range: StatePartIndexRange, - ) -> bool { - part_index_range.len.value > 0 - } - fn clear_all_maybe_modified_flags(_state: &mut Self::State) {} - fn borrowed_state_index<'a, 'b>( - state: &'a Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state[part_index.as_usize()] - } - fn borrowed_state_index_mut<'a, 'b>( - state: &'a mut Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - &mut state[part_index.as_usize()] - } - fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( - state: &'a mut Self::BorrowedState<'b>, - part_indexes: [StatePartIndex; N], - ) -> [&'a mut Self::StateElement; N] { - state - .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) - .expect("indexes are disjoint") - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash, Default)] -pub(crate) struct StateAndModified { - pub(crate) state: T, - pub(crate) modified: M, -} - -impl, M: Deref, E: fmt::Debug> fmt::Debug - for StateAndModified -{ - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_list() - .entries(self.state.iter().zip(self.modified.iter().copied()).map( - |(state, modified)| { - fmt::from_fn(move |f| { - state.fmt(f)?; - if modified { - f.write_str(" (modified)")?; - } - Ok(()) - }) - }, - )) - .finish() - } } impl StatePartKind for StatePartKindSmallSlots { const NAME: &'static str = "SmallSlots"; type DebugData = SlotDebugData; type LayoutData = (); - type State = StateAndModified, Box<[bool]>>; - type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; - type StateElement = SmallUInt; + type State = Box<[SmallUInt]>; + type BorrowedState<'a> = &'a mut [SmallUInt]; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - StateAndModified { - state: vec![0; layout_data.len()].into_boxed_slice(), - modified: vec![false; layout_data.len()].into_boxed_slice(), - } + vec![0; layout_data.len()].into_boxed_slice() } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - let StateAndModified { state, modified } = state; - StateAndModified { state, modified } + state } fn part_debug_data( state_layout: &StateLayout, @@ -437,80 +330,19 @@ impl StatePartKind for StatePartKindSmallSlots { write!(f, "{value:#x} {}", value as SmallSInt)?; Ok(()) } - fn state_index<'a>( - state: &'a Self::State, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state.state[part_index.as_usize()] - } - fn state_index_mut<'a>( - state: &'a mut Self::State, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - state.modified[part_index.as_usize()] = true; - &mut state.state[part_index.as_usize()] - } - fn state_index_fetch_maybe_modified_flag( - state: &Self::State, - part_index: StatePartIndex, - ) -> bool { - state.modified[part_index.as_usize()] - } - fn state_index_range_fetch_maybe_modified_flags( - state: &Self::State, - part_index_range: StatePartIndexRange, - ) -> bool { - state.modified[part_index_range.start.as_usize()..] - [..part_index_range.len.as_index().as_usize()] - .contains(&true) - } - fn clear_all_maybe_modified_flags(state: &mut Self::State) { - state.modified.fill(false); - } - fn borrowed_state_index<'a, 'b>( - state: &'a Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state.state[part_index.as_usize()] - } - fn borrowed_state_index_mut<'a, 'b>( - state: &'a mut Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - state.modified[part_index.as_usize()] = true; - &mut state.state[part_index.as_usize()] - } - fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( - state: &'a mut Self::BorrowedState<'b>, - part_indexes: [StatePartIndex; N], - ) -> [&'a mut Self::StateElement; N] { - for part_index in part_indexes { - state.modified[part_index.as_usize()] = true; - } - state - .state - .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) - .expect("indexes are disjoint") - } } impl StatePartKind for StatePartKindBigSlots { const NAME: &'static str = "BigSlots"; type DebugData = SlotDebugData; type LayoutData = (); - type State = StateAndModified, Box<[bool]>>; - type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; - type StateElement = BigInt; + type State = Box<[BigInt]>; + type BorrowedState<'a> = &'a mut [BigInt]; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - let state: Box<[_]> = layout_data.iter().map(|_| BigInt::default()).collect(); - StateAndModified { - modified: vec![false; state.len()].into_boxed_slice(), - state, - } + layout_data.iter().map(|_| BigInt::default()).collect() } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - let StateAndModified { state, modified } = state; - StateAndModified { state, modified } + state } fn part_debug_data( state_layout: &StateLayout, @@ -529,80 +361,19 @@ impl StatePartKind for StatePartKindBigSlots { ) -> fmt::Result { write!(f, "{:#x}", state.big_slots[index]) } - fn state_index<'a>( - state: &'a Self::State, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state.state[part_index.as_usize()] - } - fn state_index_mut<'a>( - state: &'a mut Self::State, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - state.modified[part_index.as_usize()] = true; - &mut state.state[part_index.as_usize()] - } - fn state_index_fetch_maybe_modified_flag( - state: &Self::State, - part_index: StatePartIndex, - ) -> bool { - state.modified[part_index.as_usize()] - } - fn state_index_range_fetch_maybe_modified_flags( - state: &Self::State, - part_index_range: StatePartIndexRange, - ) -> bool { - state.modified[part_index_range.start.as_usize()..] - [..part_index_range.len.as_index().as_usize()] - .contains(&true) - } - fn clear_all_maybe_modified_flags(state: &mut Self::State) { - state.modified.fill(false); - } - fn borrowed_state_index<'a, 'b>( - state: &'a Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state.state[part_index.as_usize()] - } - fn borrowed_state_index_mut<'a, 'b>( - state: &'a mut Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - state.modified[part_index.as_usize()] = true; - &mut state.state[part_index.as_usize()] - } - fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( - state: &'a mut Self::BorrowedState<'b>, - part_indexes: [StatePartIndex; N], - ) -> [&'a mut Self::StateElement; N] { - for part_index in part_indexes { - state.modified[part_index.as_usize()] = true; - } - state - .state - .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) - .expect("indexes are disjoint") - } } impl StatePartKind for StatePartKindSimOnlySlots { const NAME: &'static str = "SimOnlySlots"; type DebugData = SlotDebugData; type LayoutData = DynSimOnly; - type State = StateAndModified, Box<[bool]>>; - type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; - type StateElement = DynSimOnlyValue; + type State = Box<[DynSimOnlyValue]>; + type BorrowedState<'a> = &'a mut [DynSimOnlyValue]; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - let state: Box<[_]> = layout_data.iter().map(|ty| ty.default_value()).collect(); - StateAndModified { - modified: vec![false; state.len()].into_boxed_slice(), - state, - } + layout_data.iter().map(|ty| ty.default_value()).collect() } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - let StateAndModified { state, modified } = state; - StateAndModified { state, modified } + state } fn part_debug_data( state_layout: &StateLayout, @@ -621,61 +392,6 @@ impl StatePartKind for StatePartKindSimOnlySlots { ) -> fmt::Result { write!(f, "{:?}", state.sim_only_slots[index]) } - fn state_index<'a>( - state: &'a Self::State, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state.state[part_index.as_usize()] - } - fn state_index_mut<'a>( - state: &'a mut Self::State, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - state.modified[part_index.as_usize()] = true; - &mut state.state[part_index.as_usize()] - } - fn state_index_fetch_maybe_modified_flag( - state: &Self::State, - part_index: StatePartIndex, - ) -> bool { - state.modified[part_index.as_usize()] - } - fn state_index_range_fetch_maybe_modified_flags( - state: &Self::State, - part_index_range: StatePartIndexRange, - ) -> bool { - state.modified[part_index_range.start.as_usize()..] - [..part_index_range.len.as_index().as_usize()] - .contains(&true) - } - fn clear_all_maybe_modified_flags(state: &mut Self::State) { - state.modified.fill(false); - } - fn borrowed_state_index<'a, 'b>( - state: &'a Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a Self::StateElement { - &state.state[part_index.as_usize()] - } - fn borrowed_state_index_mut<'a, 'b>( - state: &'a mut Self::BorrowedState<'b>, - part_index: StatePartIndex, - ) -> &'a mut Self::StateElement { - state.modified[part_index.as_usize()] = true; - &mut state.state[part_index.as_usize()] - } - fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( - state: &'a mut Self::BorrowedState<'b>, - part_indexes: [StatePartIndex; N], - ) -> [&'a mut Self::StateElement; N] { - for part_index in part_indexes { - state.modified[part_index.as_usize()] = true; - } - state - .state - .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) - .expect("indexes are disjoint") - } } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index 24bc1ef..b6a4e4b 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -15,23 +15,23 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSlice, - OpaqueSimValueWriter, SimValueDebug, StaticType, Type, TypeProperties, - impl_match_variant_as_self, + OpaqueSimValueWriter, StaticType, Type, TypeProperties, impl_match_variant_as_self, }, util::{ - ConstUsize, + ConstUsize, HashMap, alternating_cell::{AlternatingCell, AlternatingCellMethods}, - serde_by_id::{SerdeById, SerdeByIdProperties, SerdeByIdTable, SerdeByIdTrait}, }, }; use bitvec::{slice::BitSlice, vec::BitVec}; +use hashbrown::hash_map::Entry; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error as _, ser::Error as _}; use std::{ borrow::{Borrow, BorrowMut, Cow}, - fmt, + fmt::{self, Write}, + hash::{BuildHasher, Hash, Hasher, RandomState}, num::NonZero, ops::{Deref, DerefMut, Index, IndexMut}, - sync::Arc, + sync::{Arc, Mutex}, }; pub(crate) mod sim_only_value_unsafe; @@ -551,119 +551,113 @@ impl_sim_value_cmp_as_bool!(AsyncReset); #[doc(hidden)] pub mod match_sim_value { - use crate::{sim::value::SimValue, ty::Type}; - use std::ops::{Deref, DerefMut}; - - macro_rules! wrapper { - ( - $(pub struct $wrapper:ident<$T:ident>($inner:ty);)* - ) => { - $(#[doc(hidden)] - pub struct $wrapper<$T>($inner); - - impl<$T> $wrapper<$T> { - #[inline(always)] - pub fn new(value: $T) -> Self { - Self(<$inner>::new(value)) - } - } - - impl<$T> Deref for $wrapper<$T> { - type Target = $inner; - - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } - } - - impl<$T> DerefMut for $wrapper<$T> { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } - })* - }; - } - - wrapper! { - pub struct MatchSimValueHelperCheckSimValue(MatchSimValueHelperCheckMutSimValue); - pub struct MatchSimValueHelperCheckMutSimValue(MatchSimValueHelperCheckRefSimValue); - pub struct MatchSimValueHelperCheckRefSimValue(MatchSimValueHelperCheckRefRefSimValue); - pub struct MatchSimValueHelperCheckRefRefSimValue(MatchSimValueHelperCheckRefMutSimValue); - pub struct MatchSimValueHelperCheckRefMutSimValue(MatchSimValueHelperCheckMutRefSimValue); - pub struct MatchSimValueHelperCheckMutRefSimValue(MatchSimValueHelperCheckMutMutSimValue); - pub struct MatchSimValueHelperCheckMutMutSimValue(MatchSimValueHelperIdentity); - } - - impl MatchSimValueHelperCheckSimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> T::SimValue { - SimValue::into_value(self.take()) - } - } - - impl<'a, T: Type> MatchSimValueHelperCheckMutSimValue<&'a mut SimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue { - self.take() - } - } - - impl<'a, T: Type> MatchSimValueHelperCheckRefSimValue<&'a SimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue { - self.take() - } - } - - impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefRefSimValue<&'a &'b SimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue { - self.take() - } - } - - impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefMutSimValue<&'a &'b mut SimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue { - self.take() - } - } - - impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutRefSimValue<&'a mut &'b SimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue { - self.take() - } - } - - impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutMutSimValue<&'a mut &'b mut SimValue> { - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue { - self.take() - } - } + use crate::{ + sim::value::{SimValue, ToSimValue}, + ty::Type, + }; #[doc(hidden)] - pub struct MatchSimValueHelperIdentity(Option); + pub struct MatchSimValueHelper(Option); - impl MatchSimValueHelperIdentity { - fn new(v: T) -> Self { + impl MatchSimValueHelper { + pub fn new(v: T) -> Self { Self(Some(v)) } - #[inline(always)] - fn take(&mut self) -> T { - self.0.take().expect("known to be Some") + } + + #[doc(hidden)] + pub trait MatchSimValue { + type MatchValue; + + /// use `self` so it comes first in the method resolution order + fn __fayalite_match_sim_value(self) -> Self::MatchValue + where + Self: Sized; + } + + impl MatchSimValue for MatchSimValueHelper> { + type MatchValue = T::SimValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + SimValue::into_value(self.0.expect("should be Some")) } - #[inline(always)] - pub fn __fayalite_match_sim_value(&mut self) -> T { - self.take() + } + + impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a SimValue> { + type MatchValue = &'a T::SimValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + SimValue::value(self.0.expect("should be Some")) + } + } + + impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a mut SimValue> { + type MatchValue = &'a mut T::SimValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + SimValue::value_mut(self.0.expect("should be Some")) + } + } + + impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ &'a T> + where + MatchSimValueHelper<&'a T>: MatchSimValue, + { + type MatchValue = as MatchSimValue>::MatchValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) + } + } + + impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ mut &'a T> + where + MatchSimValueHelper<&'a T>: MatchSimValue, + { + type MatchValue = as MatchSimValue>::MatchValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) + } + } + + impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a &'_ mut T> + where + MatchSimValueHelper<&'a T>: MatchSimValue, + { + type MatchValue = as MatchSimValue>::MatchValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &**v))) + } + } + + impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a mut &'_ mut T> + where + MatchSimValueHelper<&'a mut T>: MatchSimValue, + { + type MatchValue = as MatchSimValue>::MatchValue; + + fn __fayalite_match_sim_value(self) -> Self::MatchValue { + MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &mut **v))) } } #[doc(hidden)] - pub type MatchSimValueHelper = MatchSimValueHelperCheckSimValue; + pub trait MatchSimValueFallback { + type MatchValue; + + /// use `&mut self` so it comes later in the method resolution order than MatchSimValue + fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue; + } + + impl MatchSimValueFallback for MatchSimValueHelper { + type MatchValue = ::SimValue; + + fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue { + SimValue::into_value(self.0.take().expect("should be Some").into_sim_value()) + } + } } pub trait ToSimValue: ToSimValueWithType<::Type> + ValueType { @@ -1097,8 +1091,7 @@ impl ToSimValueWithType for bool { | CanonicalType::Enum(_) | CanonicalType::Bundle(_) | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) - | CanonicalType::TraceAsString(_) => { + | CanonicalType::DynSimOnly(_) => { panic!("can't create SimValue from bool: expected value of type: {ty:?}"); } CanonicalType::Bool(_) @@ -1227,17 +1220,80 @@ macro_rules! impl_to_sim_value_for_int_value { impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType); impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType); -impl SerdeByIdTrait for DynSimOnly { - fn serde_by_id_properties(&self) -> SerdeByIdProperties { - self.serde_by_id_properties_inner() - } +#[derive(Default)] +struct DynSimOnlySerdeTableRest { + from_serde: HashMap, + serde_id_random_state: RandomState, + buffer: String, +} - fn static_table() -> &'static SerdeByIdTable { - static TABLE: SerdeByIdTable = SerdeByIdTable::new(); - &TABLE +impl DynSimOnlySerdeTableRest { + #[cold] + fn add_new(&mut self, ty: DynSimOnly) -> DynSimOnlySerdeId { + let mut try_number = 0u64; + let mut hasher = self.serde_id_random_state.build_hasher(); + // extract more bits of randomness from TypeId -- its Hash impl only hashes 64-bits + write!(self.buffer, "{:?}", ty.type_id()).expect("shouldn't ever fail"); + self.buffer.hash(&mut hasher); + loop { + let mut hasher = hasher.clone(); + try_number.hash(&mut hasher); + try_number += 1; + let retval = DynSimOnlySerdeId(std::array::from_fn(|i| { + let mut hasher = hasher.clone(); + i.hash(&mut hasher); + hasher.finish() as u32 + })); + match self.from_serde.entry(retval) { + Entry::Occupied(_) => continue, + Entry::Vacant(e) => { + e.insert(ty); + return retval; + } + } + } } +} - const NAME: &'static str = "DynSimOnly"; +#[derive(Default)] +struct DynSimOnlySerdeTable { + to_serde: HashMap, + rest: DynSimOnlySerdeTableRest, +} + +static DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE: Mutex> = Mutex::new(None); + +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] +#[serde(transparent)] +struct DynSimOnlySerdeId([u32; 4]); + +impl From for DynSimOnlySerdeId { + fn from(ty: DynSimOnly) -> Self { + let mut locked = DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE + .lock() + .expect("shouldn't be poison"); + let DynSimOnlySerdeTable { to_serde, rest } = locked.get_or_insert_default(); + match to_serde.entry(ty) { + Entry::Occupied(occupied_entry) => *occupied_entry.get(), + Entry::Vacant(vacant_entry) => *vacant_entry.insert(rest.add_new(ty)), + } + } +} + +impl DynSimOnlySerdeId { + fn ty(self) -> Option { + let locked = DYN_SIM_ONLY_VALUE_TYPE_SERDE_TABLE + .lock() + .expect("shouldn't be poison"); + Some(*locked.as_ref()?.rest.from_serde.get(&self)?) + } +} + +#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] +struct DynSimOnlySerde<'a> { + random_id: DynSimOnlySerdeId, + #[serde(borrow)] + type_name: Cow<'a, str>, } impl Serialize for DynSimOnly { @@ -1245,7 +1301,11 @@ impl Serialize for DynSimOnly { where S: Serializer, { - SerdeById { inner: *self }.serialize(serializer) + DynSimOnlySerde { + random_id: (*self).into(), + type_name: Cow::Borrowed(self.type_name()), + } + .serialize(serializer) } } @@ -1254,7 +1314,16 @@ impl<'de> Deserialize<'de> for DynSimOnly { where D: Deserializer<'de>, { - Ok(SerdeById::deserialize(deserializer)?.inner) + let deserialized = DynSimOnlySerde::deserialize(deserializer)?; + let retval = deserialized + .random_id + .ty() + .filter(|ty| ty.type_name() == deserialized.type_name); + retval.ok_or_else(|| { + D::Error::custom( + "doesn't match any DynSimOnly that was serialized this time this program was run", + ) + }) } } @@ -1325,15 +1394,6 @@ impl Type for DynSimOnly { } } -impl SimValueDebug for DynSimOnly { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl Type for SimOnly { type BaseType = DynSimOnly; type MaskType = Bool; @@ -1399,15 +1459,6 @@ impl Type for SimOnly { } } -impl SimValueDebug for SimOnly { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - impl StaticType for SimOnly { const TYPE: Self = Self::new(); diff --git a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs index bcbcdc6..2424c03 100644 --- a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs +++ b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs @@ -3,10 +3,7 @@ //! `unsafe` parts of [`DynSimOnlyValue`] -use crate::{ - expr::{ValueType, value_category::ValueCategoryValue}, - util::serde_by_id::SerdeByIdProperties, -}; +use crate::expr::{ValueType, value_category::ValueCategoryValue}; use serde::{Serialize, de::DeserializeOwned}; use std::{ any::{self, TypeId}, @@ -36,7 +33,6 @@ unsafe trait DynSimOnlyTrait: 'static + Send + Sync { &self, json_str: &str, ) -> serde_json::Result>; - fn serde_by_id_properties_inner(&self) -> SerdeByIdProperties; } /// Safety: `type_id_dyn` is implemented correctly @@ -59,9 +55,6 @@ unsafe impl DynSimOnlyTrait for SimOnly { ) -> serde_json::Result> { Ok(Rc::::new(serde_json::from_str(json_str)?)) } - fn serde_by_id_properties_inner(&self) -> SerdeByIdProperties { - SerdeByIdProperties::of::() - } } /// Safety: @@ -158,9 +151,6 @@ impl DynSimOnly { pub fn default_value(self) -> DynSimOnlyValue { DynSimOnlyValue(self.ty.default_value()) } - pub(super) fn serde_by_id_properties_inner(self) -> SerdeByIdProperties { - self.ty.serde_by_id_properties_inner() - } } impl PartialEq for DynSimOnly { diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs index 17ad206..ad3e974 100644 --- a/crates/fayalite/src/sim/vcd.rs +++ b/crates/fayalite/src/sim/vcd.rs @@ -9,15 +9,14 @@ use crate::{ prelude::PhantomConst, sim::{ TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl, - TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceFormalInput, - TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, - TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar, - TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceTraceAsString, TraceUInt, - TraceWire, TraceWriter, TraceWriterDecls, + TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, + TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule, + TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar, TraceScalarId, + TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, + TraceWriterDecls, time::{SimDuration, SimInstant}, value::DynSimOnlyValue, }, - ty::{OpaqueSimValueSlice, TraceAsString}, util::HashMap, }; use bitvec::{order::Lsb0, slice::BitSlice}; @@ -332,7 +331,6 @@ impl WriteTrace for TraceScalar { Self::AsyncReset(v) => v.write_trace(writer, arg), Self::PhantomConst(v) => v.write_trace(writer, arg), Self::SimOnly(v) => v.write_trace(writer, arg), - Self::TraceAsString(v) => v.write_trace(writer, arg), } } } @@ -728,34 +726,6 @@ impl WriteTrace for TraceSimOnly { } } -impl WriteTrace for TraceTraceAsString { - fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { - let ArgInType { - source_var_type: _, - sink_var_type: _, - duplex_var_type: _, - properties, - scope, - } = arg.in_type(); - let Self { - location, - name, - ty, - flow: _, - } = self; - write_vcd_var( - properties, - scope, - MemoryElementPartBody::TraceAsString { ty }, - writer, - "string", - 1, - location, - name, - ) - } -} - impl WriteTrace for TraceScope { fn write_trace(self, writer: &mut W, arg: A) -> io::Result<()> { match self { @@ -766,7 +736,6 @@ impl WriteTrace for TraceScope { Self::Wire(v) => v.write_trace(writer, arg), Self::Reg(v) => v.write_trace(writer, arg), Self::ModuleIO(v) => v.write_trace(writer, arg), - Self::FormalInput(v) => v.write_trace(writer, arg), Self::Bundle(v) => v.write_trace(writer, arg), Self::Array(v) => v.write_trace(writer, arg), Self::EnumWithFields(v) => v.write_trace(writer, arg), @@ -964,27 +933,6 @@ impl WriteTrace for TraceModuleIO { } } -impl WriteTrace for TraceFormalInput { - fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { - let ArgModuleBody { properties, scope } = arg.module_body(); - let Self { - name: _, - child, - formal_input: _, - } = self; - child.write_trace( - writer, - ArgInType { - source_var_type: "wire", - sink_var_type: "wire", - duplex_var_type: "wire", - properties, - scope: Some(scope), - }, - ) - } -} - impl WriteTrace for TraceBundle { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { let ArgInType { @@ -1145,7 +1093,6 @@ impl TraceWriterDecls for VcdWriterDecls { finished_init: false, timescale, properties, - trace_as_string_buf: String::with_capacity(256), }) } } @@ -1153,7 +1100,6 @@ impl TraceWriterDecls for VcdWriterDecls { enum MemoryElementPartBody { Scalar, EnumDiscriminant { ty: Enum }, - TraceAsString { ty: TraceAsString }, } struct MemoryElementPart { @@ -1271,7 +1217,6 @@ pub struct VcdWriter { finished_init: bool, timescale: SimDuration, properties: VcdWriterProperties, - trace_as_string_buf: String, } impl VcdWriter { @@ -1381,21 +1326,6 @@ impl TraceWriter for VcdWriter { .built_scalar_id_to_vcd_id(first_id + element_index), )? } - MemoryElementPartBody::TraceAsString { ty } => { - self.trace_as_string_buf.clear(); - ty.trace_fmt_append_to_string( - &mut self.trace_as_string_buf, - OpaqueSimValueSlice::from_bitslice(&element_data[start..start + len]), - ); - write_string_value_change( - &mut self.writer, - &self.trace_as_string_buf, - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(first_id + element_index), - )?; - self.trace_as_string_buf.clear(); - } } } Ok(()) @@ -1489,16 +1419,6 @@ impl TraceWriter for VcdWriter { .built_scalar_id_to_vcd_id(id.as_usize()), ) } - - fn set_signal_string(&mut self, id: TraceScalarId, value: &str) -> Result<(), Self::Error> { - write_string_value_change( - &mut self.writer, - value, - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(id.as_usize()), - ) - } } impl fmt::Debug for VcdWriter { @@ -1508,7 +1428,6 @@ impl fmt::Debug for VcdWriter { finished_init, timescale, properties: _, - trace_as_string_buf: _, } = self; f.debug_struct("VcdWriter") .field("finished_init", finished_init) diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs index cb9db9c..bc7a0b1 100644 --- a/crates/fayalite/src/testing.rs +++ b/crates/fayalite/src/testing.rs @@ -12,13 +12,11 @@ use crate::{ bundle::BundleType, firrtl::ExportOptions, module::Module, - sim::{Simulation, vcd::VcdWriterDecls}, - util::{HashMap, RcWriter}, + util::HashMap, }; use serde::{Deserialize, Serialize}; use std::{ fmt::{self, Write}, - panic::Location, path::{Path, PathBuf}, process::Command, sync::{Mutex, OnceLock}, @@ -224,190 +222,3 @@ pub fn assert_formal>, T: BundleType>( ) .expect("testing::assert_formal() failed"); } - -pub struct CheckedVcdOutput { - writer: Option, - expected_path: PathBuf, - expected_contents: Result, std::io::Error)>, - location: &'static Location<'static>, -} - -impl CheckedVcdOutput { - #[must_use] - #[track_caller] - pub fn new(sim: &mut Simulation, expected_path: PathBuf) -> Self { - let writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - Self { - writer: Some(writer), - expected_contents: std::fs::read_to_string(&expected_path).map_err(|e| { - eprintln!( - "error: failed to read expected VCD from: {}", - expected_path.display(), - ); - (std::env::current_dir().ok(), e) - }), - expected_path, - location: Location::caller(), - } - } - #[must_use] - #[track_caller] - #[doc(hidden)] - pub fn __checked_vcd_output_macro_helper( - sim: &mut Simulation, - cargo_manifest_dir: &'static str, - path: &'static str, - ) -> Self { - Self::new(sim, Path::new(cargo_manifest_dir).join(path)) - } - pub fn with_vcd_output(&self, f: impl FnOnce(&str) -> R) -> R { - let Some(writer) = &self.writer else { - unreachable!(); - }; - writer.clone().borrow(|output| { - let Ok(output) = str::from_utf8(output) else { - unreachable!("VcdWriter writes valid UTF-8"); - }; - f(output) - }) - } - #[track_caller] - pub fn finish(mut self) { - let Ok(()) = self.finish_impl(|msg| panic!("{msg}")); - } - fn finish_impl( - &mut self, - error: impl FnOnce(std::fmt::Arguments<'_>) -> E, - ) -> Result<(), E> { - let Self { - writer: Some(writer), - expected_path, - expected_contents, - location, - } = self - else { - // already finished - return Ok(()); - }; - let Ok(vcd) = String::from_utf8(writer.take()) else { - unreachable!("VcdWriter writes valid UTF-8"); - }; - let expected_path_d = expected_path.display(); - if expected_contents - .as_ref() - .is_ok_and(|expected_contents| *expected_contents == vcd) - { - // avoid written output from being split from threads interleaving writes to stdout - let _stdout = std::io::stderr().lock(); - // use println to get output captured by tests - println!("\n{location}: generated VCD matches the expected VCD in {expected_path_d}"); - return Ok(()); - } - // avoid written output from being split from threads interleaving writes to stderr - let _stderr = std::io::stderr().lock(); - let error = |msg: std::fmt::Arguments<'_>| { - // print msg at both beginning and end so it's easier to find when the vcd is huge - Err(error(format_args!( - "\n{msg}####### VCD:\n{vcd}\n#######\n{msg}" - ))) - }; - let error = |msg: std::fmt::Arguments<'_>| match &*expected_contents { - Ok(_) => error(format_args!( - "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\ - {msg}", - )), - Err((Some(current_dir), e)) => error(format_args!( - "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\ - error: failed to read: {e}\n\ - current dir: {current_dir}\n\ - {msg}", - current_dir = current_dir.display(), - )), - Err((None, e)) => error(format_args!( - "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\ - error: failed to read: {e}\n\ - {msg}", - )), - }; - const OVERWRITE_VAR_NAME: &str = "OVERWRITE_EXPECTED_VCD"; - const OVERWRITE_VAR_VALUE: &str = "overwrite"; - match std::env::var_os(OVERWRITE_VAR_NAME) { - Some(v) if v == OVERWRITE_VAR_VALUE => match std::fs::write(&expected_path, &vcd) { - Ok(()) => error(format_args!( - "warning: since `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}` is set -- writing the generated VCD to {expected_path_d}\n" - )), - Err(e) => error(format_args!( - "error: since `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}` is set -- tried to write the generated VCD to {expected_path_d}\n\ - error: failed to write: {e}" - )), - }, - _ => error(format_args!( - "note: rerun the test with the environment variable `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}`\n\ - to update the expected output to match the generated output.\n" - )), - } - } -} - -impl Drop for CheckedVcdOutput { - #[track_caller] - fn drop(&mut self) { - let _ = self.finish_impl(|msg| { - if std::thread::panicking() { - eprintln!("{msg}"); // use eprintln to get output captured by tests - } else { - panic!("{msg}"); - } - }); - } -} - -#[macro_export] -/// Use in tests to check that [`Simulation`] generates the expected VCD traces, by comparing to a `.vcd` file containing the expected traces. -/// -/// Use like so: -/// ``` -/// # use fayalite::prelude::*; -/// # -/// # #[hdl_module] -/// # fn my_module() { -/// # #[hdl] -/// # let a: UInt<8> = m.input(); -/// # #[hdl] -/// # let b: UInt<8> = m.output(); -/// # connect(b, 0u8); -/// # #[hdl] -/// # if a.cmp_eq(100u8) { -/// # connect(b, 42u8); -/// # } -/// # } -/// // inside your #[test] fn my_test(): -/// -/// // get the module to simulate: -/// let m = my_module(); -/// // create a simulation of the module: -/// let mut sim = Simulation::new(m); -/// // set up the expected VCD traces, the given .vcd path is relative to env!("CARGO_MANIFEST_DIR") -/// let _checked_vcd_output = checked_vcd_output!( -/// &mut sim, -/// "tests/expected/my_test.vcd", -/// ); -/// // now run the simulation like normal: -/// sim.write(sim.io().a, 0u8); -/// assert_eq!(sim.read(sim.io().b).as_int(), 0); -/// sim.advance_time(SimDuration::from_micros(1)); -/// sim.write(sim.io().a, 100u8); -/// assert_eq!(sim.read(sim.io().b).as_int(), 42); -/// ``` -macro_rules! checked_vcd_output { - ($sim:expr, $path_relative_to_manifest_dir:expr $(,)?) => { - $crate::testing::CheckedVcdOutput::__checked_vcd_output_macro_helper( - $sim, - $crate::__std::env!("CARGO_MANIFEST_DIR"), - $crate::__std::concat!($path_relative_to_manifest_dir), - ) - }; -} - -pub use checked_vcd_output; diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs index 843aedb..76c0955 100644 --- a/crates/fayalite/src/ty.rs +++ b/crates/fayalite/src/ty.rs @@ -3,28 +3,22 @@ use crate::{ array::Array, - bundle::{Bundle, BundleField, BundleType}, + bundle::Bundle, clock::Clock, - enum_::{Enum, EnumType, EnumVariant}, - expr::{Expr, HdlPartialEqImpl, HdlPartialOrdImpl, ToExpr, ValueType, Valueless, ops}, + enum_::Enum, + expr::Expr, int::{Bool, SInt, UInt, UIntValue}, - intern::{Intern, Interned, LazyInterned, Memoize, SupportsPtrEqWithTypeId}, - module::transform::visit::{Fold, Folder, Visit, Visitor}, + intern::{Intern, Interned}, phantom_const::PhantomConst, reset::{AsyncReset, Reset, SyncReset}, - sim::value::{DynSimOnly, DynSimOnlyValue, SimValue, ToSimValue, ToSimValueWithType}, + sim::value::{DynSimOnly, DynSimOnlyValue, SimValue, ToSimValueWithType}, source_location::SourceLocation, - util::{ - ConstUsize, iter_eq_by, - serde_by_id::{SerdeByIdProperties, SerdeByIdTable, SerdeByIdTrait}, - slice_range, try_slice_range, - }, + util::{ConstUsize, slice_range, try_slice_range}, }; use bitvec::{slice::BitSlice, vec::BitVec}; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::DeserializeOwned}; use std::{ - borrow::Cow, - fmt::{self, Write}, + fmt, hash::Hash, iter::{FusedIterator, Sum}, marker::PhantomData, @@ -75,7 +69,6 @@ pub enum CanonicalType { Clock(Clock), PhantomConst(PhantomConst), DynSimOnly(DynSimOnly), - TraceAsString(TraceAsString), } impl fmt::Debug for CanonicalType { @@ -93,7 +86,6 @@ impl fmt::Debug for CanonicalType { Self::Clock(v) => v.fmt(f), Self::PhantomConst(v) => v.fmt(f), Self::DynSimOnly(v) => v.fmt(f), - Self::TraceAsString(v) => v.fmt(f), } } } @@ -131,7 +123,6 @@ impl CanonicalType { CanonicalType::Clock(v) => v.type_properties(), CanonicalType::PhantomConst(v) => v.type_properties(), CanonicalType::DynSimOnly(v) => v.type_properties(), - CanonicalType::TraceAsString(v) => v.type_properties(), } } pub fn is_passive(self) -> bool { @@ -226,134 +217,11 @@ impl CanonicalType { }; lhs.can_connect(rhs) } - CanonicalType::TraceAsString(lhs) => { - let CanonicalType::TraceAsString(rhs) = rhs else { - return false; - }; - lhs.can_connect(rhs) - } } } pub(crate) fn as_serde_unexpected_str(self) -> &'static str { serde_impls::SerdeCanonicalType::from(self).as_serde_unexpected_str() } - /// Unwrap transparent types until reaching a non-transparent type. Currently [`TraceAsString`] is the only transparent type. - /// - /// [`TraceAsString`]: struct@TraceAsString - pub fn unwrap_transparent_types(mut self) -> Self { - loop { - self = match self { - Self::UInt(_) - | Self::SInt(_) - | Self::Bool(_) - | Self::Array(_) - | Self::Enum(_) - | Self::Bundle(_) - | Self::AsyncReset(_) - | Self::SyncReset(_) - | Self::Reset(_) - | Self::Clock(_) - | Self::PhantomConst(_) - | Self::DynSimOnly(_) => return self, - Self::TraceAsString(ty) => ty.inner_ty(), - }; - } - } - pub fn is_layout_equivalent(self, other: Self) -> bool { - fn is_bit(ty: CanonicalType) -> bool { - match ty { - CanonicalType::UInt(ty) => ty.width() == 1, - CanonicalType::SInt(_) => false, // SInt<1> doesn't count since it would be -1/0 instead of 1/0 - CanonicalType::Bool(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) => true, - CanonicalType::Array(_) - | CanonicalType::Enum(_) - | CanonicalType::Bundle(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => false, - CanonicalType::TraceAsString(_) => { - unreachable!("handled by unwrap_transparent_types") - } - } - } - #[derive(Copy, Clone, PartialEq, Eq, Hash)] - struct MyMemoize; - impl Memoize for MyMemoize { - type Input = (CanonicalType, CanonicalType); - type InputOwned = (CanonicalType, CanonicalType); - type Output = bool; - - fn inner(self, input: &Self::Input) -> Self::Output { - let (this, other) = *input; - let this = this.unwrap_transparent_types(); - let other = other.unwrap_transparent_types(); - let this_is_bit = is_bit(this); - let other_is_bit = is_bit(other); - if this_is_bit || other_is_bit { - return this_is_bit && other_is_bit; - } - let this_is_empty = this.size().is_empty(); - let other_is_empty = other.size().is_empty(); - if this_is_empty || other_is_empty { - return this_is_empty && other_is_empty; - } - match this { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::DynSimOnly(_) => this == other, - CanonicalType::Array(this) => { - let CanonicalType::Array(other) = other else { - return false; - }; - this.len() == other.len() - && this.element().is_layout_equivalent(other.element()) - } - CanonicalType::Enum(this) => { - let CanonicalType::Enum(other) = other else { - return false; - }; - iter_eq_by( - this.variants(), - other.variants(), - |EnumVariant { name, ty }, other_variant| { - name == other_variant.name - && ty.unwrap_or_else(|| ().canonical()).is_layout_equivalent( - other_variant.ty.unwrap_or_else(|| ().canonical()), - ) - }, - ) - } - CanonicalType::Bundle(this) => { - let CanonicalType::Bundle(other) = other else { - return false; - }; - iter_eq_by( - this.fields().iter().filter(|f| !f.ty.size().is_empty()), - other.fields().iter().filter(|f| !f.ty.size().is_empty()), - |&BundleField { name, flipped, ty }, other_field| { - name == other_field.name - && flipped == other_field.flipped - && ty.is_layout_equivalent(other_field.ty) - }, - ) - } - CanonicalType::Bool(_) - | CanonicalType::AsyncReset(_) - | CanonicalType::SyncReset(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) => unreachable!("handled by is_bit"), - CanonicalType::PhantomConst(_) => unreachable!("handled by is_empty"), - CanonicalType::TraceAsString(_) => { - unreachable!("handled by unwrap_transparent_types") - } - } - } - } - MyMemoize.get_owned((self, other)) - } } pub trait MatchVariantAndInactiveScope: Sized { @@ -460,7 +328,6 @@ impl_base_type!(Reset); impl_base_type!(Clock); impl_base_type!(PhantomConst); impl_base_type!(DynSimOnly); -impl_base_type!(TraceAsString); impl_base_type_serde!(Bool, "a Bool"); impl_base_type_serde!(Enum, "an Enum"); @@ -469,7 +336,6 @@ impl_base_type_serde!(AsyncReset, "an AsyncReset"); impl_base_type_serde!(SyncReset, "a SyncReset"); impl_base_type_serde!(Reset, "a Reset"); impl_base_type_serde!(Clock, "a Clock"); -impl_base_type_serde!(TraceAsString, "a TraceAsString"); impl sealed::BaseTypeSealed for CanonicalType {} @@ -501,15 +367,7 @@ impl TypeOrDefault for crate::__ { } pub trait Type: - Copy - + Hash - + Eq - + fmt::Debug - + Send - + Sync - + 'static - + FillInDefaultedGenerics - + SimValueDebug + Copy + Hash + Eq + fmt::Debug + Send + Sync + 'static + FillInDefaultedGenerics { type BaseType: BaseType; type MaskType: Type; @@ -544,16 +402,6 @@ pub trait Type: ) -> OpaqueSimValueWritten<'w>; } -pub trait SimValueDebug { - fn sim_value_debug(value: &::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result - where - Self: Type; -} - -pub trait SimValueDisplay: Type { - fn sim_value_display(value: &Self::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result; -} - pub trait BaseType: Type< BaseType = Self, @@ -607,7 +455,6 @@ impl Type for CanonicalType { CanonicalType::Clock(v) => v.mask_type().canonical(), CanonicalType::PhantomConst(v) => v.mask_type().canonical(), CanonicalType::DynSimOnly(v) => v.mask_type().canonical(), - CanonicalType::TraceAsString(v) => v.mask_type().canonical(), } } fn canonical(&self) -> CanonicalType { @@ -643,15 +490,6 @@ impl Type for CanonicalType { } } -impl SimValueDebug for CanonicalType { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(value, f) - } -} - #[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize, Default)] #[non_exhaustive] pub struct OpaqueSimValueSizeRange { @@ -892,34 +730,13 @@ impl Sum for OpaqueSimValueSize { } } -#[derive(PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] +#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] pub struct OpaqueSimValue { bits: UIntValue, #[serde(skip_serializing_if = "Vec::is_empty", default)] sim_only_values: Vec, } -impl Clone for OpaqueSimValue { - fn clone(&self) -> Self { - Self { - bits: self.bits.clone(), - sim_only_values: self.sim_only_values.clone(), - } - } - fn clone_from(&mut self, source: &Self) { - let Self { - bits, - sim_only_values, - } = self; - if let Some(bits) = Arc::get_mut(bits.arc_bitvec_mut()) { - bits.clone_from(source.bits.bits()); - } else { - *bits = source.bits.clone(); - } - sim_only_values.clone_from(&source.sim_only_values); - } -} - impl OpaqueSimValue { pub fn empty() -> Self { Self { @@ -1299,822 +1116,3 @@ impl Index for AsMaskWithoutGenerics { Interned::into_inner(Intern::intern_sized(ty.mask_type())) } } - -trait TraceAsStringTrait: fmt::Debug + 'static + Send + Sync + SupportsPtrEqWithTypeId { - fn trace_fmt(&self, opaque: OpaqueSimValueSlice<'_>, f: &mut fmt::Formatter<'_>) - -> fmt::Result; - fn serde_by_id_properties(&self) -> SerdeByIdProperties> { - SerdeByIdProperties::of::() - } - fn can_substitute_type(&self, new_type: CanonicalType) -> bool; -} - -#[derive(Clone, PartialEq, Eq, Hash)] -struct TraceAsStringState { - ty: Interned, - canonical_ty: CanonicalType, -} - -impl TraceAsStringState { - fn new(ty: Interned) -> Interned { - #[derive(Copy, Clone, PartialEq, Eq, Hash)] - struct MyMemoize(PhantomData); - impl Memoize for MyMemoize { - type Input = Interned; - type InputOwned = Interned; - type Output = Interned>; - - fn inner(self, input: &Self::Input) -> Self::Output { - TraceAsStringState { - ty: *input, - canonical_ty: input.canonical(), - } - .intern_sized() - } - } - MyMemoize(PhantomData).get_owned(ty) - } -} - -impl fmt::Debug for TraceAsStringState { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.ty.fmt(f) - } -} - -impl TraceAsStringTrait for TraceAsStringState { - fn trace_fmt( - &self, - opaque: OpaqueSimValueSlice<'_>, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - fmt::Debug::fmt(&Type::sim_value_from_opaque(&*self.ty, opaque), f) - } - fn can_substitute_type(&self, new_type: CanonicalType) -> bool { - self.canonical_ty.is_layout_equivalent(new_type) - } -} - -impl crate::intern::InternedCompare for dyn TraceAsStringTrait { - type InternedCompareKey = crate::intern::PtrEqWithTypeId; - - fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey { - this.get_ptr_eq_with_type_id() - } -} - -impl SerdeByIdTrait for Interned { - fn serde_by_id_properties(&self) -> SerdeByIdProperties { - TraceAsStringTrait::serde_by_id_properties(&**self) - } - - fn static_table() -> &'static SerdeByIdTable { - static TABLE: SerdeByIdTable> = SerdeByIdTable::new(); - &TABLE - } - - const NAME: &'static str = "dyn TraceAsStringTrait"; -} - -/// When running the fayalite simulator, outputs a single string signal containing a formatted version of the inner value (uses [`fmt::Debug`] by default). -/// This is a transparent type, meaning [`CanonicalType::unwrap_transparent_types`] will unwrap this type. -#[derive(Copy, Clone, PartialEq, Eq, Hash)] -pub struct TraceAsString { - inner_ty: LazyInterned, - trace_as_string: LazyInterned, -} - -#[expect(non_upper_case_globals)] -pub const TraceAsString: TraceAsStringWithoutGenerics = TraceAsStringWithoutGenerics; - -impl fmt::Debug for TraceAsString { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - inner_ty, - trace_as_string: _, - } = self; - f.debug_struct("TraceAsString") - .field("inner_ty", &inner_ty.interned()) - .finish_non_exhaustive() - } -} - -impl TraceAsString { - pub fn new(inner_ty: T) -> Self { - Self::new_interned(inner_ty.intern_sized()) - } - pub fn new_interned(inner_ty: Interned) -> Self { - Self { - inner_ty: LazyInterned::Interned(inner_ty), - trace_as_string: LazyInterned::Interned(Interned::cast_unchecked( - TraceAsStringState::new(inner_ty), - |v| -> &dyn TraceAsStringTrait { v }, - )), - } - } - pub fn interned_inner_ty(self) -> Interned { - self.inner_ty.interned() - } - pub fn inner_ty(self) -> T { - *self.interned_inner_ty() - } - /// create a new `TraceAsString` but try to keep the old formatting method - pub fn with_new_inner_ty(self, inner_ty: Interned) -> TraceAsString { - if self - .trace_as_string - .can_substitute_type(inner_ty.canonical()) - { - TraceAsString { - inner_ty: LazyInterned::Interned(inner_ty), - trace_as_string: self.trace_as_string, - } - } else { - TraceAsString::new_interned(inner_ty) - } - } - pub fn canonical_trace_as_string(self) -> TraceAsString { - let Self { - inner_ty, - trace_as_string, - } = self; - TraceAsString { - inner_ty: LazyInterned::Interned(inner_ty.interned().canonical().intern_sized()), - trace_as_string, - } - } - pub fn from_canonical_trace_as_string(canonical: TraceAsString) -> Self { - let TraceAsString { - inner_ty, - trace_as_string, - } = canonical; - Self { - inner_ty: LazyInterned::Interned( - T::from_canonical(*inner_ty.interned()).intern_sized(), - ), - trace_as_string, - } - } - pub fn type_properties(self) -> TypeProperties { - self.interned_inner_ty().canonical().type_properties() - } - pub fn can_connect(self, rhs: TraceAsString) -> bool { - self.interned_inner_ty() - .canonical() - .can_connect(rhs.interned_inner_ty().canonical()) - } - pub fn trace_fmt( - self, - opaque: OpaqueSimValueSlice<'_>, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - self.trace_as_string.interned().trace_fmt(opaque, f) - } - pub fn trace_fmt_append_to_string(self, output: &mut String, opaque: OpaqueSimValueSlice<'_>) { - fn impl_fn( - trace_as_string: Interned, - output: &mut String, - opaque: OpaqueSimValueSlice<'_>, - ) { - let initial_len = output.len(); - if let Err(fmt::Error {}) = write!( - output, - "{}", - fmt::from_fn(|f| trace_as_string.trace_fmt(opaque, f)) - ) { - output.truncate(initial_len); - output.push_str(""); - } - } - impl_fn(self.trace_as_string.interned(), output, opaque) - } -} - -impl SimValueDebug for TraceAsString { - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - T::sim_value_debug(value.inner(), f) - } -} - -impl Type for TraceAsString { - type BaseType = TraceAsString; - type MaskType = T::MaskType; - type SimValue = TraceAsStringSimValue; - type MatchVariant = Expr; - type MatchActiveScope = (); - type MatchVariantAndInactiveScope = MatchVariantWithoutScope; - type MatchVariantsIter = std::iter::Once; - - fn match_variants( - this: Expr, - source_location: SourceLocation, - ) -> Self::MatchVariantsIter { - let _ = source_location; - std::iter::once(MatchVariantWithoutScope( - ops::TraceAsStringAsInner::new(this).to_expr(), - )) - } - - fn mask_type(&self) -> Self::MaskType { - self.inner_ty.mask_type() - } - - fn canonical(&self) -> CanonicalType { - CanonicalType::TraceAsString(self.canonical_trace_as_string()) - } - - fn from_canonical(canonical_type: CanonicalType) -> Self { - let CanonicalType::TraceAsString(canonical) = canonical_type else { - panic!("expected TraceAsString"); - }; - Self::from_canonical_trace_as_string(canonical) - } - - fn source_location() -> SourceLocation { - SourceLocation::builtin() - } - - fn sim_value_from_opaque(&self, opaque: OpaqueSimValueSlice<'_>) -> Self::SimValue { - TraceAsStringSimValue { - inner: SimValue::from_opaque(self.inner_ty(), opaque.to_owned()), - trace_as_string: self.trace_as_string.interned(), - } - } - - fn sim_value_clone_from_opaque( - &self, - value: &mut Self::SimValue, - opaque: OpaqueSimValueSlice<'_>, - ) { - self.inner_ty - .sim_value_clone_from_opaque(&mut value.inner, opaque); - } - - fn sim_value_to_opaque<'w>( - &self, - value: &Self::SimValue, - writer: OpaqueSimValueWriter<'w>, - ) -> OpaqueSimValueWritten<'w> { - self.inner_ty.sim_value_to_opaque(&value.inner, writer) - } -} - -impl TypeWithDeref for TraceAsString { - fn expr_deref(this: &Expr) -> &Self::MatchVariant { - Interned::into_inner( - ops::TraceAsStringAsInner::new(*this) - .to_expr() - .intern_sized(), - ) - } -} - -struct TraceAsStringStaticTypeHelper(PhantomData); - -impl Default for TraceAsStringStaticTypeHelper { - fn default() -> Self { - Self(PhantomData) - } -} - -impl From> for Interned { - fn from(_value: TraceAsStringStaticTypeHelper) -> Self { - Interned::cast_unchecked( - TraceAsStringState::new(T::TYPE.intern_sized()), - |v| -> &dyn TraceAsStringTrait { v }, - ) - } -} - -impl Default for TraceAsString { - fn default() -> Self { - Self::TYPE - } -} - -struct MakeType(Interned); - -impl From> for Interned { - fn from(value: MakeType) -> Self { - value.0 - } -} - -impl Default for MakeType { - fn default() -> Self { - Self(T::TYPE.intern_sized()) - } -} - -impl StaticType for TraceAsString { - const TYPE: Self = Self { - inner_ty: LazyInterned::new_const::>(), - trace_as_string: LazyInterned::new_const::>(), - }; - const MASK_TYPE: Self::MaskType = T::MASK_TYPE; - const TYPE_PROPERTIES: TypeProperties = T::TYPE_PROPERTIES; - const MASK_TYPE_PROPERTIES: TypeProperties = T::MASK_TYPE_PROPERTIES; -} - -#[doc(hidden)] -pub struct TraceAsStringWithoutGenerics; - -impl Index for TraceAsStringWithoutGenerics { - type Output = TraceAsString; - - fn index(&self, inner_ty: T) -> &Self::Output { - Interned::into_inner(TraceAsString::new(inner_ty).intern_sized()) - } -} - -#[derive(Clone)] -pub struct TraceAsStringSimValue { - inner: SimValue, - trace_as_string: Interned, -} - -#[derive(Serialize, Deserialize)] -#[serde(rename = "TraceAsStringSimValue")] -struct TraceAsStringSimValueSerde { - inner: T, - trace_as_string: crate::util::serde_by_id::SerdeById>, -} - -impl + Serialize> Serialize for TraceAsStringSimValue { - fn serialize(&self, serializer: S) -> Result - where - S: Serializer, - { - let Self { - inner, - trace_as_string, - } = self; - TraceAsStringSimValueSerde { - inner, - trace_as_string: crate::util::serde_by_id::SerdeById { - inner: *trace_as_string, - }, - } - .serialize(serializer) - } -} - -impl<'de, T: Type> + Deserialize<'de>> Deserialize<'de> - for TraceAsStringSimValue -{ - fn deserialize(deserializer: D) -> Result - where - D: Deserializer<'de>, - { - let TraceAsStringSimValueSerde { - inner, - trace_as_string: - crate::util::serde_by_id::SerdeById { - inner: trace_as_string, - }, - } = Deserialize::deserialize(deserializer)?; - Ok(Self { - inner, - trace_as_string, - }) - } -} - -impl TraceAsStringSimValue { - pub fn new_with_ty(inner: impl ToSimValueWithType, ty: TraceAsString) -> Self { - Self { - inner: inner.into_sim_value_with_type(ty.inner_ty()), - trace_as_string: ty.trace_as_string.interned(), - } - } - pub fn new(inner: impl ToSimValue) -> Self { - let inner = inner.into_sim_value(); - Self { - trace_as_string: TraceAsString::new(inner.ty()).trace_as_string.interned(), - inner, - } - } - pub fn into_inner(self) -> SimValue { - self.inner - } - pub fn inner(&self) -> &SimValue { - &self.inner - } - pub fn inner_mut(&mut self) -> &mut SimValue { - &mut self.inner - } -} - -impl ValueType for TraceAsStringSimValue { - type Type = TraceAsString; - type ValueCategory = crate::expr::value_category::ValueCategoryValue; - - fn ty(&self) -> Self::Type { - let inner_ty = self.inner.ty().intern_sized(); - if self - .trace_as_string - .can_substitute_type(inner_ty.canonical()) - { - TraceAsString { - inner_ty: LazyInterned::Interned(inner_ty), - trace_as_string: LazyInterned::Interned(self.trace_as_string), - } - } else { - TraceAsString::new_interned(inner_ty) - } - } -} - -impl ToExpr for TraceAsStringSimValue { - #[track_caller] - fn to_expr(&self) -> Expr { - let inner = self.inner.to_expr(); - let inner_canonical = Expr::canonical(inner); - let inner_ty = inner.ty().intern_sized(); - let ty = if self - .trace_as_string - .can_substitute_type(inner_canonical.ty()) - { - TraceAsString { - inner_ty: LazyInterned::Interned(inner_ty), - trace_as_string: LazyInterned::Interned(self.trace_as_string), - } - } else { - TraceAsString::new_interned(inner_ty) - }; - ops::ToTraceAsString::new(inner_canonical, ty).to_expr() - } -} - -impl ToSimValueWithType> for TraceAsStringSimValue { - fn to_sim_value_with_type(&self, ty: TraceAsString) -> SimValue> { - let inner = self.inner.to_sim_value_with_type(ty.inner_ty()); - SimValue::from_value( - ty, - TraceAsStringSimValue { - inner, - trace_as_string: ty.trace_as_string.interned(), - }, - ) - } - fn into_sim_value_with_type(self, ty: TraceAsString) -> SimValue> { - let inner = self.inner.into_sim_value_with_type(ty.inner_ty()); - SimValue::from_value( - ty, - TraceAsStringSimValue { - inner, - trace_as_string: ty.trace_as_string.interned(), - }, - ) - } -} - -impl ToSimValue for TraceAsStringSimValue { - fn to_sim_value(&self) -> SimValue { - SimValue::from_value(self.ty(), self.clone()) - } - fn into_sim_value(self) -> SimValue { - SimValue::from_value(self.ty(), self) - } -} - -impl fmt::Debug for TraceAsStringSimValue { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Debug::fmt(&self.inner, f) - } -} - -impl> fmt::Display for TraceAsStringSimValue { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fmt::Display::fmt(&self.inner, f) - } -} - -impl Ord for TraceAsStringSimValue -where - SimValue: Ord, -{ - fn cmp(&self, other: &Self) -> std::cmp::Ordering { - self.inner.cmp(&other.inner) - } -} - -impl PartialOrd> for TraceAsStringSimValue -where - SimValue: PartialOrd>, -{ - fn partial_cmp(&self, other: &TraceAsStringSimValue) -> Option { - self.inner.partial_cmp(&other.inner) - } -} - -impl Eq for TraceAsStringSimValue where SimValue: Eq {} - -impl Hash for TraceAsStringSimValue -where - SimValue: Hash, -{ - fn hash(&self, state: &mut H) { - self.inner.hash(state); - } -} - -impl Default for TraceAsStringSimValue -where - SimValue: Default, -{ - fn default() -> Self { - let inner = SimValue::default(); - Self { - trace_as_string: TraceAsString::new(inner.ty()).trace_as_string.interned(), - inner, - } - } -} - -impl PartialEq> for TraceAsStringSimValue -where - SimValue: PartialEq>, -{ - fn eq(&self, other: &TraceAsStringSimValue) -> bool { - self.inner == other.inner - } -} - -impl, State: ?Sized + Folder> Fold for TraceAsString { - fn fold(self, state: &mut State) -> Result { - state.fold_trace_as_string(self) - } - - fn default_fold(self, state: &mut State) -> Result { - Ok(self.with_new_inner_ty(self.interned_inner_ty().fold(state)?)) - } -} - -impl, State: ?Sized + Visitor> Visit for TraceAsString { - fn visit(&self, state: &mut State) -> Result<(), ::Error> { - state.visit_trace_as_string(self) - } - - fn default_visit(&self, state: &mut State) -> Result<(), ::Error> { - self.interned_inner_ty().visit(state) - } -} - -fn trace_as_string_cow_into_inner( - this: Cow<'_, SimValue>>, -) -> Cow<'_, SimValue> { - match this { - Cow::Borrowed(v) => Cow::Borrowed(&v.inner), - Cow::Owned(v) => Cow::Owned(SimValue::into_value(v).inner), - } -} - -fn trace_as_string_cow_into_inner_value( - this: Cow<'_, TraceAsStringSimValue>, -) -> Cow<'_, T::SimValue> { - match this { - Cow::Borrowed(v) => Cow::Borrowed(&v.inner), - Cow::Owned(v) => Cow::Owned(SimValue::into_value(v.inner)), - } -} - -impl, U: Type> HdlPartialEqImpl> for TraceAsString { - #[track_caller] - fn cmp_value_eq( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: TraceAsString, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - HdlPartialEqImpl::cmp_value_eq( - lhs.inner_ty(), - trace_as_string_cow_into_inner_value(lhs_value), - rhs.inner_ty(), - trace_as_string_cow_into_inner_value(rhs_value), - ) - } - - #[track_caller] - fn cmp_value_ne( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: TraceAsString, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - HdlPartialEqImpl::cmp_value_ne( - lhs.inner_ty(), - trace_as_string_cow_into_inner_value(lhs_value), - rhs.inner_ty(), - trace_as_string_cow_into_inner_value(rhs_value), - ) - } - - #[track_caller] - fn cmp_sim_value_eq( - lhs: Cow<'_, SimValue>, - rhs: Cow<'_, SimValue>>, - ) -> SimValue { - HdlPartialEqImpl::cmp_sim_value_eq( - trace_as_string_cow_into_inner(lhs), - trace_as_string_cow_into_inner(rhs), - ) - } - - #[track_caller] - fn cmp_sim_value_ne( - lhs: Cow<'_, SimValue>, - rhs: Cow<'_, SimValue>>, - ) -> SimValue { - HdlPartialEqImpl::cmp_sim_value_ne( - trace_as_string_cow_into_inner(lhs), - trace_as_string_cow_into_inner(rhs), - ) - } - - #[track_caller] - fn cmp_expr_eq(lhs: Expr, rhs: Expr>) -> Expr { - HdlPartialEqImpl::cmp_expr_eq(*lhs, *rhs) - } - - #[track_caller] - fn cmp_expr_ne(lhs: Expr, rhs: Expr>) -> Expr { - HdlPartialEqImpl::cmp_expr_ne(*lhs, *rhs) - } - - #[track_caller] - fn cmp_valueless_eq(lhs: Valueless, rhs: Valueless>) -> Valueless { - HdlPartialEqImpl::cmp_valueless_eq( - Valueless::new(lhs.ty().inner_ty()), - Valueless::new(rhs.ty().inner_ty()), - ) - } - - #[track_caller] - fn cmp_valueless_ne(lhs: Valueless, rhs: Valueless>) -> Valueless { - HdlPartialEqImpl::cmp_valueless_ne( - Valueless::new(lhs.ty().inner_ty()), - Valueless::new(rhs.ty().inner_ty()), - ) - } -} - -impl, U: Type> HdlPartialOrdImpl> for TraceAsString { - #[track_caller] - fn cmp_value_lt( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: TraceAsString, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - HdlPartialOrdImpl::cmp_value_lt( - lhs.inner_ty(), - trace_as_string_cow_into_inner_value(lhs_value), - rhs.inner_ty(), - trace_as_string_cow_into_inner_value(rhs_value), - ) - } - - #[track_caller] - fn cmp_value_le( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: TraceAsString, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - HdlPartialOrdImpl::cmp_value_le( - lhs.inner_ty(), - trace_as_string_cow_into_inner_value(lhs_value), - rhs.inner_ty(), - trace_as_string_cow_into_inner_value(rhs_value), - ) - } - - #[track_caller] - fn cmp_value_gt( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: TraceAsString, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - HdlPartialOrdImpl::cmp_value_gt( - lhs.inner_ty(), - trace_as_string_cow_into_inner_value(lhs_value), - rhs.inner_ty(), - trace_as_string_cow_into_inner_value(rhs_value), - ) - } - - #[track_caller] - fn cmp_value_ge( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: TraceAsString, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - HdlPartialOrdImpl::cmp_value_ge( - lhs.inner_ty(), - trace_as_string_cow_into_inner_value(lhs_value), - rhs.inner_ty(), - trace_as_string_cow_into_inner_value(rhs_value), - ) - } - - #[track_caller] - fn cmp_sim_value_lt( - lhs: Cow<'_, SimValue>, - rhs: Cow<'_, SimValue>>, - ) -> SimValue { - HdlPartialOrdImpl::cmp_sim_value_lt( - trace_as_string_cow_into_inner(lhs), - trace_as_string_cow_into_inner(rhs), - ) - } - - #[track_caller] - fn cmp_sim_value_le( - lhs: Cow<'_, SimValue>, - rhs: Cow<'_, SimValue>>, - ) -> SimValue { - HdlPartialOrdImpl::cmp_sim_value_le( - trace_as_string_cow_into_inner(lhs), - trace_as_string_cow_into_inner(rhs), - ) - } - - #[track_caller] - fn cmp_sim_value_gt( - lhs: Cow<'_, SimValue>, - rhs: Cow<'_, SimValue>>, - ) -> SimValue { - HdlPartialOrdImpl::cmp_sim_value_gt( - trace_as_string_cow_into_inner(lhs), - trace_as_string_cow_into_inner(rhs), - ) - } - - #[track_caller] - fn cmp_sim_value_ge( - lhs: Cow<'_, SimValue>, - rhs: Cow<'_, SimValue>>, - ) -> SimValue { - HdlPartialOrdImpl::cmp_sim_value_ge( - trace_as_string_cow_into_inner(lhs), - trace_as_string_cow_into_inner(rhs), - ) - } - - #[track_caller] - fn cmp_expr_lt(lhs: Expr, rhs: Expr>) -> Expr { - HdlPartialOrdImpl::cmp_expr_lt(*lhs, *rhs) - } - - #[track_caller] - fn cmp_expr_le(lhs: Expr, rhs: Expr>) -> Expr { - HdlPartialOrdImpl::cmp_expr_le(*lhs, *rhs) - } - - #[track_caller] - fn cmp_expr_gt(lhs: Expr, rhs: Expr>) -> Expr { - HdlPartialOrdImpl::cmp_expr_gt(*lhs, *rhs) - } - - #[track_caller] - fn cmp_expr_ge(lhs: Expr, rhs: Expr>) -> Expr { - HdlPartialOrdImpl::cmp_expr_ge(*lhs, *rhs) - } - - #[track_caller] - fn cmp_valueless_lt(lhs: Valueless, rhs: Valueless>) -> Valueless { - HdlPartialOrdImpl::cmp_valueless_lt( - Valueless::new(lhs.ty().inner_ty()), - Valueless::new(rhs.ty().inner_ty()), - ) - } - - #[track_caller] - fn cmp_valueless_le(lhs: Valueless, rhs: Valueless>) -> Valueless { - HdlPartialOrdImpl::cmp_valueless_le( - Valueless::new(lhs.ty().inner_ty()), - Valueless::new(rhs.ty().inner_ty()), - ) - } - - #[track_caller] - fn cmp_valueless_gt(lhs: Valueless, rhs: Valueless>) -> Valueless { - HdlPartialOrdImpl::cmp_valueless_gt( - Valueless::new(lhs.ty().inner_ty()), - Valueless::new(rhs.ty().inner_ty()), - ) - } - - #[track_caller] - fn cmp_valueless_ge(lhs: Valueless, rhs: Valueless>) -> Valueless { - HdlPartialOrdImpl::cmp_valueless_ge( - Valueless::new(lhs.ty().inner_ty()), - Valueless::new(rhs.ty().inner_ty()), - ) - } -} diff --git a/crates/fayalite/src/ty/serde_impls.rs b/crates/fayalite/src/ty/serde_impls.rs index d5b5551..af324f9 100644 --- a/crates/fayalite/src/ty/serde_impls.rs +++ b/crates/fayalite/src/ty/serde_impls.rs @@ -12,8 +12,7 @@ use crate::{ prelude::PhantomConst, reset::{AsyncReset, Reset, SyncReset}, sim::value::DynSimOnly, - ty::{BaseType, CanonicalType, TraceAsString, TraceAsStringTrait}, - util::serde_by_id::SerdeById, + ty::{BaseType, CanonicalType}, }; use serde::{Deserialize, Deserializer, Serialize, Serializer}; @@ -39,7 +38,6 @@ impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for SerdePhantomConst< #[derive(Serialize, Deserialize)] #[serde(rename = "CanonicalType")] -#[expect(private_interfaces)] pub(crate) enum SerdeCanonicalType< ArrayElement = CanonicalType, ThePhantomConst = SerdePhantomConst>, @@ -67,10 +65,6 @@ pub(crate) enum SerdeCanonicalType< Clock, PhantomConst(ThePhantomConst), DynSimOnly(DynSimOnly), - TraceAsString { - inner_ty: Interned, - trace_as_string: SerdeById>, - }, } impl SerdeCanonicalType { @@ -88,7 +82,6 @@ impl SerdeCanonicalType "a Clock", Self::PhantomConst(_) => "a PhantomConst", Self::DynSimOnly(_) => "a SimOnlyValue", - Self::TraceAsString { .. } => "a TraceAsString", } } } @@ -116,15 +109,6 @@ impl From for SerdeCanonicalType { CanonicalType::Clock(Clock {}) => Self::Clock, CanonicalType::PhantomConst(ty) => Self::PhantomConst(SerdePhantomConst(ty.get())), CanonicalType::DynSimOnly(ty) => Self::DynSimOnly(ty), - CanonicalType::TraceAsString(TraceAsString { - inner_ty, - trace_as_string, - }) => Self::TraceAsString { - inner_ty: inner_ty.interned(), - trace_as_string: SerdeById { - inner: trace_as_string.interned(), - }, - }, } } } @@ -146,13 +130,6 @@ impl From for CanonicalType { Self::PhantomConst(PhantomConst::new_interned(value.0)) } SerdeCanonicalType::DynSimOnly(value) => Self::DynSimOnly(value), - SerdeCanonicalType::TraceAsString { - inner_ty, - trace_as_string, - } => Self::TraceAsString(TraceAsString { - inner_ty: crate::intern::LazyInterned::Interned(inner_ty), - trace_as_string: crate::intern::LazyInterned::Interned(trace_as_string.inner), - }), } } } diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs index 6845d3c..f1457de 100644 --- a/crates/fayalite/src/util.rs +++ b/crates/fayalite/src/util.rs @@ -46,4 +46,3 @@ pub(crate) use misc::{InternedStrCompareAsStr, chain, copy_le_bytes_to_bitslice} pub mod job_server; pub mod prefix_sum; pub mod ready_valid; -pub(crate) mod serde_by_id; diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs index 66f0aea..a15b837 100644 --- a/crates/fayalite/src/util/ready_valid.rs +++ b/crates/fayalite/src/util/ready_valid.rs @@ -241,13 +241,15 @@ mod tests { /// happens to be in phase with the offending input or output). #[hdl_module] fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) { + #[hdl] + let clk: Clock = m.input(); #[hdl] let cd = wire(); connect( cd, #[hdl] ClockDomain { - clk: formal_global_clock(), + clk, rst: formal_reset().to_reset(), }, ); @@ -278,7 +280,7 @@ mod tests { #[hdl] let index_to_check = wire(index_ty); connect(index_to_check, any_const(index_ty)); - hdl_assume(cd.clk, index_to_check.cmp_lt(capacity.get()), ""); + hdl_assume(clk, index_to_check.cmp_lt(capacity.get()), ""); // instantiate and connect the queue #[hdl] @@ -298,13 +300,13 @@ mod tests { let expected_count_reg = reg_builder().clock_domain(cd).reset(count_ty.zero()); #[hdl] if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) { - hdl_assert(cd.clk, expected_count_reg.cmp_ne(capacity.get()), ""); + hdl_assert(clk, expected_count_reg.cmp_ne(capacity.get()), ""); connect_any(expected_count_reg, expected_count_reg + 1u8); } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) { - hdl_assert(cd.clk, expected_count_reg.cmp_ne(count_ty.zero()), ""); + hdl_assert(clk, expected_count_reg.cmp_ne(count_ty.zero()), ""); connect_any(expected_count_reg, expected_count_reg - 1u8); } - hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), ""); + hdl_assert(clk, expected_count_reg.cmp_eq(dut.count), ""); // keep an independent write index into the FIFO's circular buffer #[hdl] @@ -372,7 +374,7 @@ mod tests { match inp_firing_data { // ... and we are not receiving data, then we must not // transmit any data. - HdlNone => hdl_assert(cd.clk, HdlOption::is_none(out_firing_data), ""), + HdlNone => hdl_assert(clk, HdlOption::is_none(out_firing_data), ""), // If we are indeed receiving some data... HdlSome(data_in) => { #[hdl] @@ -380,9 +382,7 @@ mod tests { // ... and transmitting at the same time, we // must be transmitting the input data itself, // since the holding register is empty. - HdlSome(data_out) => { - hdl_assert(cd.clk, data_out.cmp_eq(data_in), "") - } + HdlSome(data_out) => hdl_assert(clk, data_out.cmp_eq(data_in), ""), // If we are receiving, but not transmitting, // store the received data in the holding // register. @@ -397,11 +397,11 @@ mod tests { match out_firing_data { // ... and we are not transmitting it, we cannot // receive any more data. - HdlNone => hdl_assert(cd.clk, HdlOption::is_none(inp_firing_data), ""), + HdlNone => hdl_assert(clk, HdlOption::is_none(inp_firing_data), ""), // If we are transmitting a previously stored value... HdlSome(data_out) => { // ... it must be the same data we stored earlier. - hdl_assert(cd.clk, data_out.cmp_eq(stored), ""); + hdl_assert(clk, data_out.cmp_eq(stored), ""); // Also, accept new data, if any. Otherwise, // let the holding register become empty. connect(stored_reg, inp_firing_data); @@ -417,17 +417,17 @@ mod tests { connect(dut.dbg.index_to_check, index_to_check); #[hdl] if let HdlSome(stored) = stored_reg { - hdl_assert(cd.clk, stored.cmp_eq(dut.dbg.stored), ""); + hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), ""); } // sync the read and write indices - hdl_assert(cd.clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), ""); - hdl_assert(cd.clk, out_index_reg.cmp_eq(dut.dbg.out_index), ""); + hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), ""); + hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), ""); // the indices should never go past the capacity, but induction // doesn't know that... - hdl_assert(cd.clk, inp_index_reg.cmp_lt(capacity.get()), ""); - hdl_assert(cd.clk, out_index_reg.cmp_lt(capacity.get()), ""); + hdl_assert(clk, inp_index_reg.cmp_lt(capacity.get()), ""); + hdl_assert(clk, out_index_reg.cmp_lt(capacity.get()), ""); // strongly constrain the state of the holding register // @@ -455,7 +455,7 @@ mod tests { connect(expected_stored, pending_reads.cmp_lt(dut.count)); // sync with the state of the holding register hdl_assert( - cd.clk, + clk, expected_stored.cmp_eq(HdlOption::is_some(stored_reg)), "", ); diff --git a/crates/fayalite/src/util/serde_by_id.rs b/crates/fayalite/src/util/serde_by_id.rs deleted file mode 100644 index 3db4ab6..0000000 --- a/crates/fayalite/src/util/serde_by_id.rs +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information - -use crate::util::HashMap; -use hashbrown::hash_map::Entry; -use serde::{Deserialize, Serialize, de::Error}; -use std::{ - any::TypeId, - borrow::Cow, - fmt::Write, - hash::{BuildHasher, Hash, Hasher}, - marker::PhantomData, - sync::Mutex, -}; - -pub(crate) struct SerdeByIdProperties { - type_id: TypeId, - type_name: &'static str, - _phantom: PhantomData T>, -} - -impl Clone for SerdeByIdProperties { - fn clone(&self) -> Self { - *self - } -} - -impl Copy for SerdeByIdProperties {} - -impl SerdeByIdProperties { - pub fn of() -> Self { - Self { - type_id: TypeId::of::(), - type_name: std::any::type_name::(), - _phantom: PhantomData, - } - } -} - -pub(crate) trait SerdeByIdTrait: Hash + Eq + Clone + 'static + Send { - fn serde_by_id_properties(&self) -> SerdeByIdProperties; - fn static_table() -> &'static SerdeByIdTable; - const NAME: &'static str; -} - -#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] -#[serde(transparent)] -struct SerdeRandomId([u32; 4]); - -#[derive(Serialize, Deserialize)] -pub(crate) struct SerdeId<'a, T: SerdeByIdTrait> { - random_id: SerdeRandomId, - #[serde(borrow)] - type_name: Cow<'a, str>, - #[serde(skip)] - _phantom: PhantomData T>, -} - -impl<'a, T: SerdeByIdTrait> Clone for SerdeId<'a, T> { - fn clone(&self) -> Self { - Self { - random_id: self.random_id, - type_name: self.type_name.clone(), - _phantom: PhantomData, - } - } -} - -impl<'a, T: SerdeByIdTrait> Eq for SerdeId<'a, T> {} - -impl<'a, 'b, T: SerdeByIdTrait> PartialEq> for SerdeId<'a, T> { - fn eq(&self, other: &SerdeId<'b, T>) -> bool { - let Self { - random_id, - type_name, - _phantom: _, - } = self; - *random_id == other.random_id && *type_name == other.type_name - } -} - -impl<'a, T: SerdeByIdTrait> Hash for SerdeId<'a, T> { - fn hash(&self, state: &mut H) { - let Self { - random_id, - type_name: _, - _phantom: _, - } = self; - random_id.hash(state); - } -} - -struct SerdeByIdTableRest { - from_serde: HashMap, T>, - serde_id_random_state: std::hash::RandomState, - buffer: String, -} - -impl Default for SerdeByIdTableRest { - fn default() -> Self { - Self { - from_serde: Default::default(), - serde_id_random_state: Default::default(), - buffer: Default::default(), - } - } -} - -impl SerdeByIdTableRest { - fn add_new(&mut self, value: T) -> SerdeId<'static, T> { - let properties = value.serde_by_id_properties(); - let mut try_number = 0u64; - let mut hasher = self.serde_id_random_state.build_hasher(); - // extract more bits of randomness from TypeId -- its Hash impl only hashes 64-bits - write!(self.buffer, "{:?}", properties.type_id).expect("shouldn't ever fail"); - self.buffer.hash(&mut hasher); - loop { - let mut hasher = hasher.clone(); - try_number.hash(&mut hasher); - try_number += 1; - let key = SerdeId { - random_id: SerdeRandomId(std::array::from_fn(|i| { - let mut hasher = hasher.clone(); - i.hash(&mut hasher); - hasher.finish() as u32 - })), - type_name: Cow::Borrowed(properties.type_name), - _phantom: PhantomData, - }; - match self.from_serde.entry(key) { - Entry::Occupied(_) => continue, - Entry::Vacant(e) => { - let key = e.key().clone(); - e.insert(value); - return key; - } - } - } - } -} - -pub(crate) struct SerdeByIdTableMut { - to_serde: HashMap>, - rest: SerdeByIdTableRest, -} - -impl Default for SerdeByIdTableMut { - fn default() -> Self { - Self { - to_serde: Default::default(), - rest: Default::default(), - } - } -} - -impl SerdeByIdTableMut { - pub(crate) fn to_serde(&mut self, value: &T) -> SerdeId<'static, T> { - if let Some(retval) = self.to_serde.get(value) { - return retval.clone(); - } - self.to_serde_insert(value) - } - #[cold] - fn to_serde_insert(&mut self, value: &T) -> SerdeId<'static, T> { - let value = value.clone(); - let retval = self.rest.add_new(value.clone()); - self.to_serde.insert(value, retval.clone()); - retval - } - pub(crate) fn from_serde(&self, id: &SerdeId<'_, T>) -> Option { - self.rest.from_serde.get(id).cloned() - } -} - -pub(crate) struct SerdeByIdTable(Mutex>>); - -impl SerdeByIdTable { - pub(crate) const fn new() -> Self { - Self(Mutex::new(None)) - } - pub(crate) fn to_serde(&self, value: &T) -> SerdeId<'static, T> { - self.0 - .lock() - .expect("shouldn't be poison") - .get_or_insert_with( - #[cold] - || Default::default(), - ) - .to_serde(value) - } - pub(crate) fn from_serde(&self, id: &SerdeId<'_, T>) -> Option { - self.0 - .lock() - .expect("shouldn't be poison") - .get_or_insert_with( - #[cold] - || Default::default(), - ) - .from_serde(id) - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default, Ord, PartialOrd)] -pub(crate) struct SerdeById { - pub(crate) inner: T, -} - -impl<'de, T: SerdeByIdTrait> Deserialize<'de> for SerdeById { - fn deserialize(deserializer: D) -> Result - where - D: serde::Deserializer<'de>, - { - let id = SerdeId::deserialize(deserializer)?; - let inner = T::static_table().from_serde(&id).ok_or_else(|| { - D::Error::custom(format_args!( - "doesn't match any {} that was serialized this time this program was run: type_name={:?}", - T::NAME, - id.type_name, - )) - })?; - Ok(Self { inner }) - } -} - -impl Serialize for SerdeById { - fn serialize(&self, serializer: S) -> Result - where - S: serde::Serializer, - { - T::static_table() - .to_serde(&self.inner) - .serialize(serializer) - } -} diff --git a/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs b/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs index 620e78c..3e1ac0c 100644 --- a/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs +++ b/crates/fayalite/src/vendor/xilinx/yosys_nextpnr_prjxray.rs @@ -546,7 +546,7 @@ impl Visitor for XdcFileWriter { base.source_location(), )? {}, } - match base.canonical_ty().unwrap_transparent_types() { + match base.canonical_ty() { CanonicalType::UInt(_) | CanonicalType::SInt(_) | CanonicalType::Bool(_) @@ -563,9 +563,6 @@ impl Visitor for XdcFileWriter { v, base.source_location(), )? {}, - CanonicalType::TraceAsString(_) => { - unreachable!("handled by unwrap_transparent_types") - } } self.required_dont_touch_targets.insert(target); match v { @@ -595,9 +592,6 @@ impl Visitor for XdcFileWriter { v, instance.source_location(), )? {}, - TargetBase::FormalInput(_) | TargetBase::SimIoForGlobal(_) => { - unreachable!("base.is_valid_annotation_target() is known to be false") - } } } } diff --git a/crates/fayalite/src/wire.rs b/crates/fayalite/src/wire.rs index d167c5f..a350d9a 100644 --- a/crates/fayalite/src/wire.rs +++ b/crates/fayalite/src/wire.rs @@ -58,13 +58,11 @@ impl Wire { ty: T::from_canonical(ty), } } - #[track_caller] pub fn new_unchecked( scoped_name: ScopedNameId, source_location: SourceLocation, ty: T, ) -> Self { - scoped_name.0.assert_is_name_id(); Self { name: scoped_name, source_location, @@ -78,7 +76,7 @@ impl Wire { self.containing_module_name_id().0 } pub fn containing_module_name_id(&self) -> NameId { - self.name.0.unwrap_name_id() + self.name.0 } pub fn name(&self) -> Interned { self.name_id().0 diff --git a/crates/fayalite/tests/expected/my_test.md b/crates/fayalite/tests/expected/my_test.md deleted file mode 100644 index a3b52ae..0000000 --- a/crates/fayalite/tests/expected/my_test.md +++ /dev/null @@ -1,6 +0,0 @@ - - -`my_test.vcd` is used in the doctest of `fayalite::testing::checked_vcd_output` diff --git a/crates/fayalite/tests/expected/my_test.vcd b/crates/fayalite/tests/expected/my_test.vcd deleted file mode 100644 index 3df1caf..0000000 --- a/crates/fayalite/tests/expected/my_test.vcd +++ /dev/null @@ -1,13 +0,0 @@ -$timescale 1 ps $end -$scope module my_module $end -$var wire 8 gAF7X a $end -$var wire 8 QS=a/ b $end -$upscope $end -$enddefinitions $end -$dumpvars -b0 gAF7X -b0 QS=a/ -$end -#1000000 -b1100100 gAF7X -b101010 QS=a/ diff --git a/crates/fayalite/tests/hdl_types_fmt.rs b/crates/fayalite/tests/hdl_types_fmt.rs deleted file mode 100644 index 382f64d..0000000 --- a/crates/fayalite/tests/hdl_types_fmt.rs +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information -use fayalite::{prelude::*, ty::SimValueDebug}; -use std::fmt; - -#[hdl(outline_generated)] -struct MyStruct0 { - v: T, - a: ArrayType, S>, -} - -#[hdl] -#[test] -fn check_my_struct0() { - let ty = MyStruct0[UInt[8]][3]; - assert_eq!( - format!("{ty:?}"), - "MyStruct0 { v: UInt<8>, a: Array, 3> }", - ); - assert_eq!( - format!("{:?}", ty.mask_type()), - "MaskType { v: Bool, a: Array }", - ); - let v = #[hdl(sim)] - MyStruct0::<_, _> { - v: 0x23u8, - a: [1u8, 2, 3], - }; - assert_eq!( - format!("{v:?}"), - "MyStruct0 { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }", - ); -} - -#[hdl(outline_generated, custom_debug())] -struct MyStruct1 { - v: T, - a: ArrayType, S>, -} - -impl fmt::Debug for MyStruct1 { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { v, a } = self; - f.debug_struct("Custom") - .field("v", v) - .field("a", a) - .finish() - } -} - -impl SimValueDebug for MyStruct1 { - #[hdl] - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - #[hdl(sim)] - let Self { v, a } = value; - f.debug_struct("Custom") - .field("v", &v) - .field("a", &a) - .finish() - } -} - -#[hdl] -#[test] -fn check_my_struct1() { - let ty = MyStruct1[UInt[8]][3]; - assert_eq!( - format!("{ty:?}"), - "Custom { v: UInt<8>, a: Array, 3> }", - ); - assert_eq!( - format!("{:?}", ty.mask_type()), - "MaskType { v: Bool, a: Array }", - ); - let v = #[hdl(sim)] - MyStruct1::<_, _> { - v: 0x23u8, - a: [1u8, 2, 3], - }; - assert_eq!( - format!("{v:?}"), - "Custom { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }", - ); -} - -#[hdl(outline_generated)] -enum MyEnum0 { - Unit, - V(T), - A(ArrayType, S>), -} - -#[hdl] -#[test] -fn check_my_enum0() { - let ty = MyEnum0[UInt[8]][3]; - assert_eq!( - format!("{ty:?}"), - "MyEnum0 { Unit: (), V: UInt<8>, A: Array, 3> }", - ); - let v = #[hdl(sim)] - ty.Unit(); - assert_eq!(format!("{v:?}"), "Unit"); - let v = #[hdl(sim)] - ty.V(0x23u8); - assert_eq!(format!("{v:?}"), "V(0x23_u8)"); - let v = #[hdl(sim)] - ty.A([1u8, 2, 3]); - assert_eq!(format!("{v:?}"), "A([0x1_u8, 0x2_u8, 0x3_u8])"); -} - -#[hdl(outline_generated, custom_debug())] -enum MyEnum1 { - Unit, - V(T), - A(ArrayType, S>), -} - -impl fmt::Debug for MyEnum1 { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { Unit, V, A } = self; - f.debug_struct("Custom") - .field("Unit", Unit) - .field("V", V) - .field("A", A) - .finish() - } -} - -impl SimValueDebug for MyEnum1 { - #[hdl] - fn sim_value_debug( - value: &::SimValue, - f: &mut fmt::Formatter<'_>, - ) -> fmt::Result { - type SimValueT = ::SimValue; - match value { - SimValueT::::Unit(_) => f.write_str("MyEnum1::Unit"), - SimValueT::::V(v, _) => f.debug_tuple("MyEnum1::V").field(v).finish(), - SimValueT::::A(a, _) => f.debug_tuple("MyEnum1::A").field(a).finish(), - SimValueT::::Unknown(_) => f.write_str("MyEnum1::Unknown"), - } - } -} - -#[hdl] -#[test] -fn check_my_enum1() { - let ty = MyEnum1[UInt[8]][3]; - assert_eq!( - format!("{ty:?}"), - "Custom { Unit: (), V: UInt<8>, A: Array, 3> }", - ); - let v = #[hdl(sim)] - ty.Unit(); - assert_eq!(format!("{v:?}"), "MyEnum1::Unit"); - let v = #[hdl(sim)] - ty.V(0x23u8); - assert_eq!(format!("{v:?}"), "MyEnum1::V(0x23_u8)"); - let v = #[hdl(sim)] - ty.A([1u8, 2, 3]); - assert_eq!(format!("{v:?}"), "MyEnum1::A([0x1_u8, 0x2_u8, 0x3_u8])"); -} diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs index aa028f4..2761cba 100644 --- a/crates/fayalite/tests/module.rs +++ b/crates/fayalite/tests/module.rs @@ -13,7 +13,7 @@ use fayalite::{ }; use serde_json::json; -#[hdl(outline_generated, cmp_eq)] +#[hdl(outline_generated)] pub enum TestEnum { A, B(UInt<8>), @@ -679,270 +679,6 @@ circuit check_enum_literals: }; } -#[hdl_module(outline_generated)] -pub fn check_enum_cmp_eq() { - #[hdl] - let lhs: TestEnum = m.input(); - #[hdl] - let rhs: TestEnum = m.input(); - #[hdl] - let eq: Bool = m.output(); - connect(eq, lhs.cmp_eq(rhs)); -} - -#[test] -fn test_enum_cmp_eq() { - let _n = SourceLocation::normalize_files_for_tests(); - let m = check_enum_cmp_eq(); - dbg!(m); - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_enums: None, - ..ExportOptions::default() - }, - "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 -circuit check_enum_cmp_eq: - type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|} - module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] - input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1] - input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1] - output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] - wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] - match lhs: @[module-XXXXXXXXXX.rs 5:1] - A: - match rhs: @[module-XXXXXXXXXX.rs 5:1] - A: - connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] - B(_match_arm_value): - skip - C(_match_arm_value_1): - skip - B(_match_arm_value_2): - match rhs: @[module-XXXXXXXXXX.rs 5:1] - A: - skip - B(_match_arm_value_3): - connect TestEnum_cmp_eq, eq(_match_arm_value_2, _match_arm_value_3) @[module-XXXXXXXXXX.rs 5:1] - C(_match_arm_value_4): - skip - C(_match_arm_value_5): - match rhs: @[module-XXXXXXXXXX.rs 5:1] - A: - skip - B(_match_arm_value_6): - skip - C(_match_arm_value_7): - wire _array_literal_expr: UInt<1>[3] - connect _array_literal_expr[0], eq(_match_arm_value_5[0], _match_arm_value_7[0]) - connect _array_literal_expr[1], eq(_match_arm_value_5[1], _match_arm_value_7[1]) - connect _array_literal_expr[2], eq(_match_arm_value_5[2], _match_arm_value_7[2]) - wire _cast_array_to_bits_expr: UInt<1>[3] - connect _cast_array_to_bits_expr[0], _array_literal_expr[0] - connect _cast_array_to_bits_expr[1], _array_literal_expr[1] - connect _cast_array_to_bits_expr[2], _array_literal_expr[2] - wire _cast_to_bits_expr: UInt<3> - connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) - connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] - connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] -", - }; - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), - ..ExportOptions::default() - }, - "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 -circuit check_enum_cmp_eq: - type Ty0 = {|A, B, C|} - type Ty1 = {tag: Ty0, body: UInt<8>} - module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] - input lhs: Ty1 @[module-XXXXXXXXXX.rs 2:1] - input rhs: Ty1 @[module-XXXXXXXXXX.rs 3:1] - output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] - wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] - match lhs.tag: @[module-XXXXXXXXXX.rs 5:1] - A: - match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] - A: - connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] - B: - skip - C: - skip - B: - match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] - A: - skip - B: - connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1] - C: - skip - C: - match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] - A: - skip - B: - skip - C: - wire _array_literal_expr: UInt<1>[3] - wire _cast_bits_to_array_expr: UInt<1>[3] - wire _cast_bits_to_array_expr_flattened: UInt<1>[3] - connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0) - connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] - connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1) - connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] - connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2) - connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] - wire _cast_bits_to_array_expr_1: UInt<1>[3] - wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] - connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0) - connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] - connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1) - connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] - connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2) - connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] - connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) - connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1]) - connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2]) - wire _cast_array_to_bits_expr: UInt<1>[3] - connect _cast_array_to_bits_expr[0], _array_literal_expr[0] - connect _cast_array_to_bits_expr[1], _array_literal_expr[1] - connect _cast_array_to_bits_expr[2], _array_literal_expr[2] - wire _cast_to_bits_expr: UInt<3> - connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) - connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] - connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] -", - }; - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts), - ..ExportOptions::default() - }, - "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 -circuit check_enum_cmp_eq: - type Ty0 = {tag: UInt<2>, body: UInt<8>} - module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] - input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1] - input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1] - output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] - wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] - when eq(lhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] - else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - skip - else when eq(lhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - skip - else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1] - else when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - skip - else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - skip - else: - wire _array_literal_expr: UInt<1>[3] - wire _cast_bits_to_array_expr: UInt<1>[3] - wire _cast_bits_to_array_expr_flattened: UInt<1>[3] - connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0) - connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] - connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1) - connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] - connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2) - connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] - wire _cast_bits_to_array_expr_1: UInt<1>[3] - wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] - connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0) - connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] - connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1) - connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] - connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2) - connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] - connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) - connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1]) - connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2]) - wire _cast_array_to_bits_expr: UInt<1>[3] - connect _cast_array_to_bits_expr[0], _array_literal_expr[0] - connect _cast_array_to_bits_expr[1], _array_literal_expr[1] - connect _cast_array_to_bits_expr[2], _array_literal_expr[2] - wire _cast_to_bits_expr: UInt<3> - connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) - connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] - connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] -", - }; - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt), - ..ExportOptions::default() - }, - "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 -circuit check_enum_cmp_eq: - module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] - input lhs: UInt<10> @[module-XXXXXXXXXX.rs 2:1] - input rhs: UInt<10> @[module-XXXXXXXXXX.rs 3:1] - output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] - wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] - when eq(bits(lhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] - else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - skip - else when eq(bits(lhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - skip - else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - connect TestEnum_cmp_eq, eq(bits(bits(lhs, 9, 2), 7, 0), bits(bits(rhs, 9, 2), 7, 0)) @[module-XXXXXXXXXX.rs 5:1] - else when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] - skip - else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] - skip - else: - wire _array_literal_expr: UInt<1>[3] - wire _cast_bits_to_array_expr: UInt<1>[3] - wire _cast_bits_to_array_expr_flattened: UInt<1>[3] - connect _cast_bits_to_array_expr_flattened[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) - connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] - connect _cast_bits_to_array_expr_flattened[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) - connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] - connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) - connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] - wire _cast_bits_to_array_expr_1: UInt<1>[3] - wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] - connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) - connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] - connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) - connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] - connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) - connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] - connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) - connect _array_literal_expr[1], eq(_cast_bits_to_array_expr[1], _cast_bits_to_array_expr_1[1]) - connect _array_literal_expr[2], eq(_cast_bits_to_array_expr[2], _cast_bits_to_array_expr_1[2]) - wire _cast_array_to_bits_expr: UInt<1>[3] - connect _cast_array_to_bits_expr[0], _array_literal_expr[0] - connect _cast_array_to_bits_expr[1], _array_literal_expr[1] - connect _cast_array_to_bits_expr[2], _array_literal_expr[2] - wire _cast_to_bits_expr: UInt<3> - connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) - connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] - connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] -", - }; -} - #[hdl_module(outline_generated)] pub fn check_struct_enum_match() { #[hdl] @@ -3683,176 +3419,20 @@ circuit check_formal: %[[ input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1] input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1] input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1] - inst formal_reset of formal_reset @[builtin 1:1] + inst formal_reset of formal_reset @[formal.rs 185:24] assert(clk, pred1, and(en1, not(formal_reset.rst)), "en check 1") @[module-XXXXXXXXXX.rs 9:1] - assume(clk, pred2, and(en2, not(formal_reset.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1] - cover(clk, pred3, and(en3, not(formal_reset.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1] - assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1] - assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1] - cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1] - extmodule formal_reset: @[builtin 1:1] - output rst: UInt<1> @[builtin 1:1] - defname = __fayalite_formal_reset -"#, - }; -} - -#[hdl_module(outline_generated)] -pub fn check_formal_input() { - #[hdl] - let bool_in: Bool = m.input(); - #[hdl] - let bool_out: Bool = m.output(); - #[hdl] - let any_const_out1: Bool = m.output(); - #[hdl] - let any_const_out2: UInt<16> = m.output(); - #[hdl] - let any_const_out3: SInt<12> = m.output(); - #[hdl] - let any_seq_out: UInt<10> = m.output(); - #[hdl] - let all_const_out: UInt<10> = m.output(); - #[hdl] - let all_seq_out: UInt<10> = m.output(); - - #[hdl] - let bool_reg = reg_builder() - .clock_domain( - #[hdl] - ClockDomain { - clk: formal_global_clock(), - rst: formal_reset(), - }, - ) - .reset(false); - - connect(bool_reg, bool_in); - connect(bool_out, bool_reg); - connect(any_const_out1, any_const(StaticType::TYPE)); - connect(any_const_out2, any_const(StaticType::TYPE)); - connect(any_const_out3, any_const(StaticType::TYPE)); - connect(any_seq_out, any_seq(StaticType::TYPE)); - connect(all_const_out, all_const(StaticType::TYPE)); - connect(all_seq_out, all_seq(StaticType::TYPE)); -} - -#[test] -fn test_formal_input() { - let _n = SourceLocation::normalize_files_for_tests(); - let m = check_formal_input(); - dbg!(m); - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - "/test/check_formal_input.fir": r#"FIRRTL version 3.2.0 -circuit check_formal_input: %[[ - { - "class": "firrtl.AttributeAnnotation", - "description": "gclk", - "target": "~check_formal_input|check_formal_input>formal_global_clock" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>formal_global_clock" - }, - { - "class": "firrtl.AttributeAnnotation", - "description": "anyconst", - "target": "~check_formal_input|check_formal_input>any_const" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>any_const" - }, - { - "class": "firrtl.AttributeAnnotation", - "description": "anyconst", - "target": "~check_formal_input|check_formal_input>any_const_1" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>any_const_1" - }, - { - "class": "firrtl.AttributeAnnotation", - "description": "anyconst", - "target": "~check_formal_input|check_formal_input>any_const_2" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>any_const_2" - }, - { - "class": "firrtl.AttributeAnnotation", - "description": "anyseq", - "target": "~check_formal_input|check_formal_input>any_seq" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>any_seq" - }, - { - "class": "firrtl.AttributeAnnotation", - "description": "allconst", - "target": "~check_formal_input|check_formal_input>all_const" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>all_const" - }, - { - "class": "firrtl.AttributeAnnotation", - "description": "allseq", - "target": "~check_formal_input|check_formal_input>all_seq" - }, - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~check_formal_input|check_formal_input>all_seq" - }, - { - "class": "firrtl.transforms.BlackBoxInlineAnno", - "name": "fayalite_formal_reset.v", - "text": "module __fayalite_formal_reset(output rst);\n assign rst = $initstate;\nendmodule\n", - "target": "~check_formal_input|formal_reset" - } -]] - type Ty0 = {clk: Clock, rst: UInt<1>} - type Ty1 = {rst: UInt<1>} - module check_formal_input: @[module-XXXXXXXXXX.rs 1:1] - input bool_in: UInt<1> @[module-XXXXXXXXXX.rs 2:1] - output bool_out: UInt<1> @[module-XXXXXXXXXX.rs 3:1] - output any_const_out1: UInt<1> @[module-XXXXXXXXXX.rs 4:1] - output any_const_out2: UInt<16> @[module-XXXXXXXXXX.rs 5:1] - output any_const_out3: SInt<12> @[module-XXXXXXXXXX.rs 6:1] - output any_seq_out: UInt<10> @[module-XXXXXXXXXX.rs 7:1] - output all_const_out: UInt<10> @[module-XXXXXXXXXX.rs 8:1] - output all_seq_out: UInt<10> @[module-XXXXXXXXXX.rs 9:1] - wire _bundle_literal_expr_1: Ty0 - connect _bundle_literal_expr_1.clk, asClock(UInt<1>(0h0)) - connect _bundle_literal_expr_1.rst, UInt<1>(0h0) - reg formal_global_clock: UInt<1>, _bundle_literal_expr_1.clk @[builtin 1:1] - inst formal_reset of formal_reset @[builtin 1:1] - reg any_const: UInt<1>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 13:1] - reg any_const_1: UInt<16>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 15:1] - reg any_const_2: SInt<12>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 17:1] - reg any_seq: UInt<10>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 19:1] - reg all_const: UInt<10>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 21:1] - reg all_seq: UInt<10>, _bundle_literal_expr_1.clk @[module-XXXXXXXXXX.rs 23:1] - wire _bundle_literal_expr: Ty0 - connect _bundle_literal_expr.clk, asClock(formal_global_clock) - connect _bundle_literal_expr.rst, formal_reset.rst - regreset bool_reg: UInt<1>, _bundle_literal_expr.clk, _bundle_literal_expr.rst, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 10:1] - connect bool_reg, bool_in @[module-XXXXXXXXXX.rs 11:1] - connect bool_out, bool_reg @[module-XXXXXXXXXX.rs 12:1] - connect any_const_out1, any_const @[module-XXXXXXXXXX.rs 14:1] - connect any_const_out2, any_const_1 @[module-XXXXXXXXXX.rs 16:1] - connect any_const_out3, any_const_2 @[module-XXXXXXXXXX.rs 18:1] - connect any_seq_out, any_seq @[module-XXXXXXXXXX.rs 20:1] - connect all_const_out, all_const @[module-XXXXXXXXXX.rs 22:1] - connect all_seq_out, all_seq @[module-XXXXXXXXXX.rs 24:1] - extmodule formal_reset: @[builtin 1:1] - output rst: UInt<1> @[builtin 1:1] + inst formal_reset_1 of formal_reset @[formal.rs 185:24] + assume(clk, pred2, and(en2, not(formal_reset_1.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1] + inst formal_reset_2 of formal_reset @[formal.rs 185:24] + cover(clk, pred3, and(en3, not(formal_reset_2.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1] + inst formal_reset_3 of formal_reset @[formal.rs 185:24] + assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset_3.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1] + inst formal_reset_4 of formal_reset @[formal.rs 185:24] + assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset_4.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1] + inst formal_reset_5 of formal_reset @[formal.rs 185:24] + cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset_5.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1] + extmodule formal_reset: @[formal.rs 169:5] + output rst: UInt<1> @[formal.rs 172:32] defname = __fayalite_formal_reset "#, }; @@ -3985,10 +3565,21 @@ circuit check_enum_connect_any: connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1] HdlSome: wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1] + wire _cast_bits_to_bundle_expr_1: Ty5 + wire _cast_bits_to_bundle_expr_flattened_1: Ty6 + connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0) + wire _cast_bits_to_enum_expr_1: Ty3 + when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)): + connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone) + else: + connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome) + connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1 + connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1) + connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body ; connect different types: ; lhs: SInt<1> ; rhs: SInt<2> - connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1] + connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1] wire _bundle_literal_expr_2: Ty4 connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome) connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2) @@ -4010,18 +3601,18 @@ circuit check_enum_connect_any: connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1] C: wire __connect_variant_body_3: Ty8 @[module-XXXXXXXXXX.rs 8:1] - wire _cast_bits_to_bundle_expr_1: Ty8 - wire _cast_bits_to_bundle_expr_flattened_1: Ty9 - connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0) - wire _cast_bits_to_enum_expr_1: Ty3 - when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)): - connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone) + wire _cast_bits_to_bundle_expr_2: Ty8 + wire _cast_bits_to_bundle_expr_flattened_2: Ty9 + connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0) + wire _cast_bits_to_enum_expr_2: Ty3 + when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)): + connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone) else: - connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome) - connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1 - connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0) - connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body - connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1] + connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome) + connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2 + connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0) + connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body + connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1] wire _bundle_literal_expr_4: Ty1 connect _bundle_literal_expr_4.tag, {|A, B, C|}(C) wire _cast_bundle_to_bits_expr_1: Ty9 @@ -4050,18 +3641,18 @@ circuit check_enum_connect_any: connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1] B: wire __connect_variant_body_5: Ty5 @[module-XXXXXXXXXX.rs 9:1] - wire _cast_bits_to_bundle_expr_2: Ty4 - wire _cast_bits_to_bundle_expr_flattened_2: Ty7 - connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0) - wire _cast_bits_to_enum_expr_2: Ty3 - when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)): - connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone) + wire _cast_bits_to_bundle_expr_3: Ty4 + wire _cast_bits_to_bundle_expr_flattened_3: Ty7 + connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0) + wire _cast_bits_to_enum_expr_3: Ty3 + when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)): + connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone) else: - connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome) - connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2 - connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1) - connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body - match _cast_bits_to_bundle_expr_2.tag: @[module-XXXXXXXXXX.rs 9:1] + connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome) + connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3 + connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1) + connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body + match _cast_bits_to_bundle_expr_3.tag: @[module-XXXXXXXXXX.rs 9:1] HdlNone: wire _bundle_literal_expr_6: Ty5 connect _bundle_literal_expr_6.tag, {|HdlNone, HdlSome|}(HdlNone) @@ -4069,10 +3660,21 @@ circuit check_enum_connect_any: connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1] HdlSome: wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1] + wire _cast_bits_to_bundle_expr_4: Ty4 + wire _cast_bits_to_bundle_expr_flattened_4: Ty7 + connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0) + wire _cast_bits_to_enum_expr_4: Ty3 + when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_4.tag, 0)): + connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlNone) + else: + connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlSome) + connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4 + connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1) + connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body ; connect different types: ; lhs: SInt<2> ; rhs: SInt<1> - connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1] + connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1] wire _bundle_literal_expr_7: Ty5 connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome) connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6) @@ -4094,18 +3696,18 @@ circuit check_enum_connect_any: connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1] C: wire __connect_variant_body_7: Ty8 @[module-XXXXXXXXXX.rs 9:1] - wire _cast_bits_to_bundle_expr_3: Ty8 - wire _cast_bits_to_bundle_expr_flattened_3: Ty9 - connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0) - wire _cast_bits_to_enum_expr_3: Ty3 - when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)): - connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone) + wire _cast_bits_to_bundle_expr_5: Ty8 + wire _cast_bits_to_bundle_expr_flattened_5: Ty9 + connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0) + wire _cast_bits_to_enum_expr_5: Ty3 + when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_5.tag, 0)): + connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlNone) else: - connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome) - connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3 - connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0) - connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body - connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1] + connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlSome) + connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_enum_expr_5 + connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0) + connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body + connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1] wire _bundle_literal_expr_9: Ty2 connect _bundle_literal_expr_9.tag, {|A, B, C|}(C) wire _cast_bundle_to_bits_expr_3: Ty9 @@ -4172,10 +3774,16 @@ circuit check_enum_connect_any: connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1] else: wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1] + wire _cast_bits_to_bundle_expr_1: Ty3 + wire _cast_bits_to_bundle_expr_flattened_1: Ty3 + connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0) + connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag + connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1) + connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body ; connect different types: ; lhs: SInt<1> ; rhs: SInt<2> - connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1] + connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1] wire _bundle_literal_expr_2: Ty2 connect _bundle_literal_expr_2.tag, UInt<1>(0h1) connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2) @@ -4191,13 +3799,13 @@ circuit check_enum_connect_any: connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1] else: wire __connect_variant_body_3: Ty4 @[module-XXXXXXXXXX.rs 8:1] - wire _cast_bits_to_bundle_expr_1: Ty4 - wire _cast_bits_to_bundle_expr_flattened_1: Ty4 - connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 0, 0), 0, 0) - connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag - connect _cast_bits_to_bundle_expr_flattened_1.body, UInt<0>(0) - connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body - connect __connect_variant_body_3, _cast_bits_to_bundle_expr_1 @[module-XXXXXXXXXX.rs 8:1] + wire _cast_bits_to_bundle_expr_2: Ty4 + wire _cast_bits_to_bundle_expr_flattened_2: Ty4 + connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0) + connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag + connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0) + connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body + connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1] wire _bundle_literal_expr_4: Ty0 connect _bundle_literal_expr_4.tag, UInt<2>(0h2) wire _cast_bundle_to_bits_expr_1: Ty4 @@ -4219,23 +3827,29 @@ circuit check_enum_connect_any: connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1] else when eq(i1.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1] wire __connect_variant_body_5: Ty3 @[module-XXXXXXXXXX.rs 9:1] - wire _cast_bits_to_bundle_expr_2: Ty2 - wire _cast_bits_to_bundle_expr_flattened_2: Ty2 - connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i1.body, 1, 0), 0, 0) - connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag - connect _cast_bits_to_bundle_expr_flattened_2.body, bits(bits(i1.body, 1, 0), 1, 1) - connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body - when eq(_cast_bits_to_bundle_expr_2.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1] + wire _cast_bits_to_bundle_expr_3: Ty2 + wire _cast_bits_to_bundle_expr_flattened_3: Ty2 + connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0) + connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag + connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1) + connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body + when eq(_cast_bits_to_bundle_expr_3.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1] wire _bundle_literal_expr_6: Ty3 connect _bundle_literal_expr_6.tag, UInt<1>(0h0) connect _bundle_literal_expr_6.body, UInt<2>(0h0) connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1] else: wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1] + wire _cast_bits_to_bundle_expr_4: Ty2 + wire _cast_bits_to_bundle_expr_flattened_4: Ty2 + connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0) + connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag + connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1) + connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body ; connect different types: ; lhs: SInt<2> ; rhs: SInt<1> - connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_2.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1] + connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1] wire _bundle_literal_expr_7: Ty3 connect _bundle_literal_expr_7.tag, UInt<1>(0h1) connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6) @@ -4251,13 +3865,13 @@ circuit check_enum_connect_any: connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1] else: wire __connect_variant_body_7: Ty4 @[module-XXXXXXXXXX.rs 9:1] - wire _cast_bits_to_bundle_expr_3: Ty4 - wire _cast_bits_to_bundle_expr_flattened_3: Ty4 - connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 0, 0), 0, 0) - connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag - connect _cast_bits_to_bundle_expr_flattened_3.body, UInt<0>(0) - connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body - connect __connect_variant_body_7, _cast_bits_to_bundle_expr_3 @[module-XXXXXXXXXX.rs 9:1] + wire _cast_bits_to_bundle_expr_5: Ty4 + wire _cast_bits_to_bundle_expr_flattened_5: Ty4 + connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0) + connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_bundle_expr_flattened_5.tag + connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0) + connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body + connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1] wire _bundle_literal_expr_9: Ty1 connect _bundle_literal_expr_9.tag, UInt<2>(0h2) wire _cast_bundle_to_bits_expr_3: Ty4 diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 223c4bc..e57c064 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -1,28 +1,15 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information -use bitvec::{order::Lsb0, view::BitView}; use fayalite::{ - assert_export_firrtl, - firrtl::ExportOptions, - formal::FormalInputKind, - memory::{ReadStruct, ReadWriteStruct, WriteStruct, splat_mask}, - module::{ - instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc, - transform::simplify_enums::SimplifyEnumsKind, - }, + memory::{ReadStruct, ReadWriteStruct, WriteStruct}, + module::{instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc}, prelude::*, reset::ResetType, sim::vcd::VcdWriterDecls, - ty::SimValueDebug, util::{RcWriter, ready_valid::queue}, }; -use std::{ - collections::BTreeMap, - num::NonZeroUsize, - panic::{AssertUnwindSafe, catch_unwind, resume_unwind}, - rc::Rc, -}; +use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc}; #[hdl_module(outline_generated)] pub fn connect_const() { @@ -563,150 +550,6 @@ fn test_enums() { } } -#[hdl] -pub enum EnumWithSimpleBody { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), -} - -#[hdl_module(outline_generated)] -pub fn enum_with_simple_body() { - #[hdl] - let which_in: UInt<8> = m.input(); - #[hdl] - let data_in: UInt<8> = m.input(); - #[hdl] - let which_out: UInt<8> = m.output(); - #[hdl] - let data_out: UInt<8> = m.output(); - #[hdl] - let enum_out: EnumWithSimpleBody = m.output(); - - #[hdl] - if which_in.cmp_eq(0u8) { - connect(enum_out, EnumWithSimpleBody.A(data_in)); - } else if which_in.cmp_eq(1u8) { - connect(enum_out, EnumWithSimpleBody.B(data_in)); - } else { - connect(enum_out, EnumWithSimpleBody.C(data_in)); - } - - #[hdl] - match enum_out { - EnumWithSimpleBody::A(v) => { - connect(which_out, 0u8); - connect(data_out, v); - } - EnumWithSimpleBody::B(v) => { - connect(which_out, 1u8); - connect(data_out, v); - } - EnumWithSimpleBody::C(v) => { - connect(which_out, 2u8); - connect(data_out, v); - } - } -} - -#[hdl] -#[test] -fn test_enum_with_simple_body() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(enum_with_simple_body()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - for which in 0u8..=2 { - for data in (0..u8::MAX).step_by(45) { - sim.write(sim.io().which_in, which); - sim.write(sim.io().data_in, data); - sim.advance_time(SimDuration::from_micros(1)); - assert_eq!(sim.read(sim.io().which_out).as_int(), which); - assert_eq!(sim.read(sim.io().data_out).as_int(), data); - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - #[derive(Debug)] - struct WireState<'a> { - name: &'a str, - space_then_id: Option<&'a str>, - value: Option<&'a str>, - } - impl<'a> WireState<'a> { - fn new(name: &'a str) -> Self { - Self { - name, - space_then_id: None, - value: None, - } - } - } - let mut variant_wires = [ - WireState::new("A"), - WireState::new("B"), - WireState::new("C"), - ]; - // check that output .vcd has the proper values for all variants' wires - for (is_last, line) in vcd.lines().map(|line| (false, line)).chain([(true, "")]) { - if let Some(line) = line.strip_prefix("$var wire 8") - && let Some(line) = line.strip_suffix(" $end") - && let Some((space_then_id, state)) = variant_wires - .iter_mut() - .find_map(|state| Some((line.strip_suffix(state.name)?.strip_suffix(" ")?, state))) - { - assert_eq!(space_then_id.chars().next(), Some(' ')); - assert!( - space_then_id - .chars() - .skip(1) - .all(|ch| matches!(ch, '!'..='~')) - ); - assert_eq!(state.space_then_id.replace(space_then_id), None); - } else if line.starts_with("#") || is_last { - let Some(expected_value) = variant_wires[0].value else { - panic!( - "variant {} hasn't been initialized before a timestamp or EOF: {variant_wires:#?}\n\ - line={line:?}", - variant_wires[0].name, - ); - }; - for state in &variant_wires { - assert_eq!( - state.value, - Some(expected_value), - "at a timestamp or EOF: variant value for {} doesn't match expected value.\n\ - {variant_wires:#?}\nline={line:?}", - state.name, - ); - } - } else if line.starts_with("b") { - for state in &mut variant_wires { - let Some(space_then_id) = state.space_then_id else { - let name = state.name; - panic!( - "variant {name} hasn't had an id assigned yet: {variant_wires:#?}\n\ - line={line:?}", - ); - }; - if let Some(value) = line.strip_suffix(space_then_id) { - state.value = Some(value); - break; - } - } - } - } - if vcd != include_str!("sim/expected/enum_with_simple_body.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/enum_with_simple_body.txt") { - panic!(); - } -} - #[hdl_module(outline_generated)] pub fn memories() { #[hdl] @@ -2998,754 +2841,3 @@ fn test_queue_4_true_true() { include_str!("sim/expected/queue_4_true_true.txt"), ); } - -#[hdl(outline_generated, custom_debug(sim), cmp_eq)] -pub enum HasCustomDebug { - Text(UInt<512>), - FmtError, -} - -impl HasCustomDebug { - #[hdl] - pub fn new_sim(text: Result<&str, std::fmt::Error>) -> SimValue { - match text { - Ok(text) => { - let mut retval = HasCustomDebug.Text.zero(); - let src = text.as_bytes().view_bits::(); - let dest = retval.bits_mut(); - let len = src.len().min(dest.len()); - dest[..len].clone_from_bitslice(&src[..len]); - #[hdl(sim)] - HasCustomDebug.Text(retval) - } - Err(std::fmt::Error) => - { - #[hdl(sim)] - HasCustomDebug.FmtError() - } - } - } - pub fn new(text: Result<&str, std::fmt::Error>) -> Expr { - Self::new_sim(text).to_expr() - } -} - -impl SimValueDebug for HasCustomDebug { - #[hdl] - fn sim_value_debug( - value: &::SimValue, - f: &mut std::fmt::Formatter<'_>, - ) -> std::fmt::Result { - if f.alternate() { - return #[hdl(sim)] - match value { - Self::FmtError => f.write_str("FmtError"), - Self::Text(text) => f.debug_tuple("Text").field(text).finish(), - }; - } - #[hdl(sim)] - match value { - Self::FmtError => Err(std::fmt::Error), - Self::Text(text) => { - assert_eq!(text.ty().width() % u8::BITS as usize, 0); - let mut bytes = vec![0u8; text.ty().width() / u8::BITS as usize]; - bytes - .view_bits_mut::() - .clone_from_bitslice(text.bits()); - if let Some(len) = bytes.iter().position(|b| *b == 0) { - bytes.truncate(len); - } - f.write_str(&String::from_utf8_lossy(&bytes)) - } - } - } -} - -#[hdl_module(outline_generated)] -pub fn sim_trace_as_string() { - #[hdl] - let clk: Clock = m.input(); - #[hdl] - let read: ReadStruct>, ConstUsize<8>> = m.input(); - #[hdl] - let write: WriteStruct, 2>, ConstUsize<8>> = m.input(); - #[hdl] - let mut mem = memory_with_init([[HasCustomDebug::new(Ok("")).to_trace_as_string(); 2]; 4]); - let read_port = mem.new_read_port(); - connect(read_port.clk, clk); - connect_any(read_port.addr, read.addr); - connect(read_port.en, read.en); - for (l, r) in read.data.iter().zip(read_port.data.iter()) { - connect(l, &**r); - } - let write_port = mem.new_write_port(); - connect(write_port.clk, clk); - connect_any(write_port.addr, write.addr); - connect(write_port.data, write.data); - connect(write_port.en, write.en); - connect(write_port.mask, write.mask); -} - -#[hdl] -#[test] -fn test_sim_trace_as_string() { - let _n = SourceLocation::normalize_files_for_tests(); - let m = sim_trace_as_string(); - let mut sim = Simulation::new(m); - // sim.set_breakpoints_unstable(Default::default(), true); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.write(sim.io().clk, false); - sim.write(sim.io().read.clk, false); - sim.write(sim.io().write.clk, false); - #[derive(Debug)] - struct TestCase { - read: Option<(u8, [Result<&'static str, std::fmt::Error>; 2])>, - write_addr: Option, - write_data: [Result<&'static str, std::fmt::Error>; 2], - write_mask: [bool; 2], - } - const TEST_CASES: &[TestCase] = &[ - TestCase { - read: None, - write_addr: None, - write_data: [Ok(""); 2], - write_mask: [false; 2], - }, - TestCase { - read: None, - write_addr: Some(0), - write_data: [Ok("mem[0][0]"), Ok("mem[0][1]")], - write_mask: [true; 2], - }, - TestCase { - read: None, - write_addr: Some(1), - write_data: [Ok("mem[1][0]"), Ok("mem[1][1]")], - write_mask: [true; 2], - }, - TestCase { - read: None, - write_addr: Some(2), - write_data: [Ok("mem[2][0]"), Ok("mem[2][1]")], - write_mask: [true; 2], - }, - TestCase { - read: None, - write_addr: Some(3), - write_data: [Ok("mem[3][0]"), Ok("mem[3][1]")], - write_mask: [true; 2], - }, - TestCase { - read: Some((1, [Ok("mem[1][0]"), Ok("mem[1][1]")])), - write_addr: None, - write_data: [Err(std::fmt::Error), Err(std::fmt::Error)], - write_mask: [true; 2], - }, - TestCase { - read: Some((1, [Err(std::fmt::Error), Err(std::fmt::Error)])), - write_addr: Some(1), - write_data: [Err(std::fmt::Error), Err(std::fmt::Error)], - write_mask: [true; 2], - }, - ]; - for test_case in TEST_CASES { - let TestCase { - read, - write_addr, - write_data, - write_mask, - } = test_case; - sim.write(sim.io().read.addr, read.map(|v| v.0).unwrap_or(0)); - sim.write(sim.io().read.en, read.is_some()); - sim.write(sim.io().write.addr, write_addr.unwrap_or(0)); - sim.write(sim.io().write.en, write_addr.is_some()); - sim.write( - sim.io().write.data, - write_data.map(|v| HasCustomDebug::new_sim(v).to_trace_as_string()), - ); - sim.write( - sim.io().write.mask, - write_mask.map(|v| splat_mask(TraceAsString[HasCustomDebug], v.to_expr())), - ); - sim.write(sim.io().clk, false); - sim.advance_time(SimDuration::from_nanos(500)); - sim.write(sim.io().clk, true); - sim.advance_time(SimDuration::from_nanos(500)); - if let Some((_, expected_read_data)) = read { - let read_data = sim.read(sim.io().read.data); - let expected_read_data = expected_read_data - .map(HasCustomDebug::new_sim) - .into_sim_value(); - assert!( - *read_data.inner() == expected_read_data, - "{read_data:#?}\n!= {expected_read_data:#?}", - ); - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_trace_as_string.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_trace_as_string.txt") { - panic!(); - } -} - -#[test] -fn test_firrtl_trace_as_string() { - let _n = SourceLocation::normalize_files_for_tests(); - let m = sim_trace_as_string(); - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_memories: false, - simplify_enums: None, - ..ExportOptions::default() - }, - "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 -circuit sim_trace_as_string: %[[ - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem.mem", - "hexOrBinary": "b", - "target": "~sim_trace_as_string|sim_trace_as_string>mem" - } -]] - type Ty0 = {|Text: UInt<512>, FmtError|} - type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} - type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} - type Ty3 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} - type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} - module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] - input clk: Clock @[module-XXXXXXXXXX.rs 2:1] - input `read`: Ty1 @[module-XXXXXXXXXX.rs 3:1] - input `write`: Ty2 @[module-XXXXXXXXXX.rs 4:1] - mem `mem`: @[module-XXXXXXXXXX.rs 5:1] - data-type => Ty0[2] - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect `mem`.r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] - connect `mem`.r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] - connect `read`.data[0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 10:1] - connect `read`.data[1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 10:1] - connect `mem`.w1.clk, clk @[module-XXXXXXXXXX.rs 12:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect `mem`.w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] - connect `mem`.w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] - connect `mem`.w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] - connect `mem`.w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] -"#, - "/test/sim_trace_as_string/mem.mem": r"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 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-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -", - }; - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_memories: true, - simplify_enums: None, - ..ExportOptions::default() - }, - "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 -circuit sim_trace_as_string: %[[ - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem.mem", - "hexOrBinary": "b", - "target": "~sim_trace_as_string|sim_trace_as_string>mem" - } -]] - type Ty0 = {|Text: UInt<512>, FmtError|} - type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} - type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} - type Ty3 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty0[2]} - type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty0[2], mask: UInt<1>[2]} - type Ty5 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<513>[2]} - type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<513>[2], mask: UInt<1>[2]} - module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] - input clk: Clock @[module-XXXXXXXXXX.rs 2:1] - input `read`: Ty1 @[module-XXXXXXXXXX.rs 3:1] - input `write`: Ty2 @[module-XXXXXXXXXX.rs 4:1] - mem `mem`: @[module-XXXXXXXXXX.rs 5:1] - data-type => UInt<513>[2] - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - wire mem_r0: Ty3 @[module-XXXXXXXXXX.rs 6:1] - wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 11:1] - wire _cast_bits_to_enum_expr: Ty0 - wire _cast_bits_to_enum_expr_body: UInt<512> - connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 512) - when eq(UInt<1>(0), tail(`mem`.r0.data[0], 512)): - connect _cast_bits_to_enum_expr, {|Text: UInt<512>, FmtError|}(Text, _cast_bits_to_enum_expr_body) - else: - connect _cast_bits_to_enum_expr, {|Text: UInt<512>, FmtError|}(FmtError) - connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 6:1] - wire _cast_bits_to_enum_expr_1: Ty0 - wire _cast_bits_to_enum_expr_body_1: UInt<512> - connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 512) - when eq(UInt<1>(0), tail(`mem`.r0.data[1], 512)): - connect _cast_bits_to_enum_expr_1, {|Text: UInt<512>, FmtError|}(Text, _cast_bits_to_enum_expr_body_1) - else: - connect _cast_bits_to_enum_expr_1, {|Text: UInt<512>, FmtError|}(FmtError) - connect mem_r0.data[1], _cast_bits_to_enum_expr_1 @[module-XXXXXXXXXX.rs 6:1] - wire _cast_enum_to_bits_expr: UInt<513> - match mem_w1.data[0]: - Text(_cast_enum_to_bits_expr_Text): - connect _cast_enum_to_bits_expr, pad(cat(_cast_enum_to_bits_expr_Text, UInt<1>(0)), 513) - FmtError: - connect _cast_enum_to_bits_expr, UInt<513>(1) - connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1] - wire _cast_enum_to_bits_expr_1: UInt<513> - match mem_w1.data[1]: - Text(_cast_enum_to_bits_expr_Text_1): - connect _cast_enum_to_bits_expr_1, pad(cat(_cast_enum_to_bits_expr_Text_1, UInt<1>(0)), 513) - FmtError: - connect _cast_enum_to_bits_expr_1, UInt<513>(1) - connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] - connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] - connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] - connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] - connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect mem_r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] - connect mem_r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] - connect `read`.data[0], mem_r0.data[0] @[module-XXXXXXXXXX.rs 10:1] - connect `read`.data[1], mem_r0.data[1] @[module-XXXXXXXXXX.rs 10:1] - connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 12:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect mem_w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] - connect mem_w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] - connect mem_w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] - connect mem_w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] -"#, - "/test/sim_trace_as_string/mem.mem": r"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 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-", - }; - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_memories: false, - simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), - ..ExportOptions::default() - }, - "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 -circuit sim_trace_as_string: %[[ - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem.mem", - "hexOrBinary": "b", - "target": "~sim_trace_as_string|sim_trace_as_string>mem" - } -]] - type Ty0 = {|Text, FmtError|} - type Ty1 = {tag: Ty0, body: UInt<512>} - type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} - type Ty3 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} - type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} - type Ty5 = {tag: UInt<1>, body: UInt<1>} - type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: Ty5[2]} - type Ty7 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} - module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] - input clk: Clock @[module-XXXXXXXXXX.rs 2:1] - input `read`: Ty2 @[module-XXXXXXXXXX.rs 3:1] - input `write`: Ty3 @[module-XXXXXXXXXX.rs 4:1] - mem `mem`: @[module-XXXXXXXXXX.rs 5:1] - data-type => Ty1[2] - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.data, mem_w1.data @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.mask[0].tag, mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.mask[0].body, mem_w1.mask[0] @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.mask[1].tag, mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.w1.mask[1].body, mem_w1.mask[1] @[module-XXXXXXXXXX.rs 11:1] - connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect `mem`.r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] - connect `mem`.r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] - connect `read`.data[0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 10:1] - connect `read`.data[1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 10:1] - connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 12:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect mem_w1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] - connect mem_w1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] - connect mem_w1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] - connect mem_w1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] -"#, - "/test/sim_trace_as_string/mem.mem": r"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 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-", - }; - #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 - assert_export_firrtl! { - m => - options: ExportOptions { - simplify_memories: true, - simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), - ..ExportOptions::default() - }, - "/test/sim_trace_as_string.fir": r#"FIRRTL version 3.2.0 -circuit sim_trace_as_string: %[[ - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem_0_tag.mem", - "hexOrBinary": "b", - "target": "~sim_trace_as_string|sim_trace_as_string>mem_0_tag" - }, - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem_0_body.mem", - "hexOrBinary": "h", - "target": "~sim_trace_as_string|sim_trace_as_string>mem_0_body" - }, - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem_1_tag.mem", - "hexOrBinary": "b", - "target": "~sim_trace_as_string|sim_trace_as_string>mem_1_tag" - }, - { - "class": "firrtl.annotations.MemoryFileInlineAnnotation", - "filename": "/test/sim_trace_as_string/mem_1_body.mem", - "hexOrBinary": "h", - "target": "~sim_trace_as_string|sim_trace_as_string>mem_1_body" - } -]] - type Ty0 = {|Text, FmtError|} - type Ty1 = {tag: Ty0, body: UInt<512>} - type Ty2 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} - type Ty3 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} - type Ty4 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: Ty1[2]} - type Ty5 = {tag: UInt<1>, body: UInt<1>} - type Ty6 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: Ty5[2]} - type Ty7 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<1>} - type Ty8 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<1>, mask: UInt<1>} - type Ty9 = {addr: UInt<2>, en: UInt<1>, clk: Clock, flip data: UInt<512>} - type Ty10 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: UInt<512>, mask: UInt<1>} - type Ty11 = {addr: UInt<2>, en: UInt<1>, clk: Clock, data: Ty1[2], mask: UInt<1>[2]} - module sim_trace_as_string: @[module-XXXXXXXXXX.rs 1:1] - input clk: Clock @[module-XXXXXXXXXX.rs 2:1] - input `read`: Ty2 @[module-XXXXXXXXXX.rs 3:1] - input `write`: Ty3 @[module-XXXXXXXXXX.rs 4:1] - mem mem_0_tag: @[module-XXXXXXXXXX.rs 5:1] - data-type => UInt<1> - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - mem mem_0_body: @[module-XXXXXXXXXX.rs 5:1] - data-type => UInt<512> - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - mem mem_1_tag: @[module-XXXXXXXXXX.rs 5:1] - data-type => UInt<1> - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - mem mem_1_body: @[module-XXXXXXXXXX.rs 5:1] - data-type => UInt<512> - depth => 4 - read-latency => 0 - write-latency => 1 - read-under-write => old - reader => r0 - writer => w1 - wire mem_r0: Ty4 @[module-XXXXXXXXXX.rs 6:1] - wire mem_w1: Ty6 @[module-XXXXXXXXXX.rs 11:1] - wire _cast_bits_to_enum_expr: Ty0 - when eq(UInt<1>(0), tail(mem_0_tag.r0.data, 0)): - connect _cast_bits_to_enum_expr, {|Text, FmtError|}(Text) - else: - connect _cast_bits_to_enum_expr, {|Text, FmtError|}(FmtError) - connect mem_r0.data[0].tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 6:1] - wire _cast_enum_to_bits_expr: UInt<1> - match mem_w1.data[0].tag: - Text: - connect _cast_enum_to_bits_expr, UInt<1>(0) - FmtError: - connect _cast_enum_to_bits_expr, UInt<1>(1) - connect mem_0_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_tag.w1.mask, mem_w1.mask[0].tag @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] - connect mem_r0.data[0].body, mem_0_body.r0.data @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_body.w1.data, mem_w1.data[0].body @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_body.w1.mask, mem_w1.mask[0].body @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] - connect mem_0_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] - connect mem_0_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] - wire _cast_bits_to_enum_expr_1: Ty0 - when eq(UInt<1>(0), tail(mem_1_tag.r0.data, 0)): - connect _cast_bits_to_enum_expr_1, {|Text, FmtError|}(Text) - else: - connect _cast_bits_to_enum_expr_1, {|Text, FmtError|}(FmtError) - connect mem_r0.data[1].tag, _cast_bits_to_enum_expr_1 @[module-XXXXXXXXXX.rs 6:1] - wire _cast_enum_to_bits_expr_1: UInt<1> - match mem_w1.data[1].tag: - Text: - connect _cast_enum_to_bits_expr_1, UInt<1>(0) - FmtError: - connect _cast_enum_to_bits_expr_1, UInt<1>(1) - connect mem_1_tag.w1.data, _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_tag.w1.mask, mem_w1.mask[1].tag @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] - connect mem_r0.data[1].body, mem_1_body.r0.data @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_body.w1.data, mem_w1.data[1].body @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_body.w1.mask, mem_w1.mask[1].body @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 6:1] - connect mem_1_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 11:1] - connect mem_1_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 11:1] - wire mem_w1_1: Ty11 @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.mask[0].tag, mem_w1_1.mask[0] @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.mask[0].body, mem_w1_1.mask[0] @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.mask[1].tag, mem_w1_1.mask[1] @[module-XXXXXXXXXX.rs 11:1] - connect mem_w1.mask[1].body, mem_w1_1.mask[1] @[module-XXXXXXXXXX.rs 11:1] - connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 7:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect mem_r0.addr, `read`.addr @[module-XXXXXXXXXX.rs 8:1] - connect mem_r0.en, `read`.en @[module-XXXXXXXXXX.rs 9:1] - connect `read`.data[0], mem_r0.data[0] @[module-XXXXXXXXXX.rs 10:1] - connect `read`.data[1], mem_r0.data[1] @[module-XXXXXXXXXX.rs 10:1] - connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 12:1] - ; connect different types: - ; lhs: UInt<2> - ; rhs: UInt<8> - connect mem_w1_1.addr, `write`.addr @[module-XXXXXXXXXX.rs 13:1] - connect mem_w1_1.data, `write`.data @[module-XXXXXXXXXX.rs 14:1] - connect mem_w1_1.en, `write`.en @[module-XXXXXXXXXX.rs 15:1] - connect mem_w1_1.mask, `write`.mask @[module-XXXXXXXXXX.rs 16:1] -"#, - "/test/sim_trace_as_string/mem_0_body.mem": r"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -", - "/test/sim_trace_as_string/mem_0_tag.mem": r"0 -0 -0 -0 -", - "/test/sim_trace_as_string/mem_1_body.mem": r"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -", - "/test/sim_trace_as_string/mem_1_tag.mem": r"0 -0 -0 -0 -", - }; -} - -#[hdl_module(outline_generated)] -pub fn formal_counter(count_modulus: u8, asserted_max_count: u8) { - #[hdl] - let cd = wire(); - connect( - cd, - #[hdl] - ClockDomain { - clk: formal_global_clock(), - rst: formal_reset(), - }, - ); - #[hdl] - let count_reg: UInt<8> = reg_builder().clock_domain(cd).reset(0u8); - let next_count = count_reg + 1u8; - #[hdl] - if next_count.cmp_lt(count_modulus) { - connect_any(count_reg, next_count); - } else { - connect(count_reg, 0u8); - } - #[hdl] - let count: UInt<8> = m.output(); - connect(count, count_reg); - #[hdl] - let enable_assert: Bool = m.input(); - #[hdl] - if enable_assert { - hdl_assert(cd.clk, count_reg.cmp_le(asserted_max_count), ""); - } - #[hdl] - let any_seq_out: UInt<16> = m.output(); - connect(any_seq_out, any_seq(any_seq_out.ty())); -} - -#[hdl] -#[test] -fn test_formal_counter() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(formal_counter(10, 10)); - let _checked_vcd_output = - checked_vcd_output!(&mut sim, "tests/sim/expected/test_formal_counter.vcd"); - let Some((_, any_seq_in)) = sim - .global_io() - .into_iter() - .find(|(global, _)| global.kind() == FormalInputKind::AnySeq) - else { - panic!("can't find any_seq"); - }; - let any_seq_in = Expr::>::from_canonical(any_seq_in); - sim.write_clock(formal_global_clock(), false); - sim.write_reset(formal_reset(), true); - sim.write(any_seq_in, 0u16); - sim.write(sim.io().enable_assert, true); - sim.advance_time(SimDuration::from_micros(1)); - assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 0u16); - sim.write_clock(formal_global_clock(), true); - sim.write(any_seq_in, 1234u16); - assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 1234u16); - assert_eq!(sim.read(sim.io().count).as_int(), 0); - sim.write_reset(formal_reset(), false); - sim.advance_time(SimDuration::from_micros(1)); - for i in 0..32u8 { - assert_eq!(i % 10, sim.read(sim.io().count).as_int()); - sim.write_clock(formal_global_clock(), false); - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(formal_global_clock(), true); - sim.advance_time(SimDuration::from_micros(1)); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/test_formal_counter.txt") { - panic!(); - } -} - -#[cfg(panic = "unwind")] -#[hdl] -#[test] -fn test_formal_counter_assert() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(formal_counter(10, 8)); - let _checked_vcd_output = checked_vcd_output!( - &mut sim, - "tests/sim/expected/test_formal_counter_assert.vcd" - ); - let Some((_, any_seq_in)) = sim - .global_io() - .into_iter() - .find(|(global, _)| global.kind() == FormalInputKind::AnySeq) - else { - panic!("can't find any_seq"); - }; - let any_seq_in = Expr::>::from_canonical(any_seq_in); - let half_us = SimDuration::from_nanos(500); - sim.write_clock(formal_global_clock(), false); - sim.write_reset(formal_reset(), true); - sim.write(any_seq_in, 0u16); - sim.write(sim.io().enable_assert, false); - sim.advance_time(half_us); - assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 0u16); - sim.write_clock(formal_global_clock(), true); - sim.write(any_seq_in, 1234u16); - assert_eq!(sim.read(sim.io().any_seq_out).as_int(), 1234u16); - assert_eq!(sim.read(sim.io().count).as_int(), 0); - sim.write_reset(formal_reset(), false); - sim.advance_time(half_us); - const PANIC_MSG: &str = "Assertions/Assumptions failed at time 20.500000000000 \u{3bc}s:\n\ -at module-XXXXXXXXXX.rs:12:1: in InstantiatedModule(formal_counter: formal_counter): assert failed: \n"; - const EXPECTED_FAILURE_CYCLE: u8 = 19; - for i in 0.. { - dbg!(i); - assert_eq!(i % 10, sim.read(sim.io().count).as_int()); - sim.write(sim.io().enable_assert, i > 15); - sim.write_clock(formal_global_clock(), false); - sim.advance_time(half_us); - match catch_unwind(AssertUnwindSafe(|| { - sim.write_clock(formal_global_clock(), true); - sim.advance_time(half_us); - })) { - Ok(()) => assert!(i < EXPECTED_FAILURE_CYCLE), - Err(e) => match e.downcast::() { - Ok(e) if *e == PANIC_MSG => { - assert_eq!(i, EXPECTED_FAILURE_CYCLE); - break; - } - Ok(e) => resume_unwind(e), - Err(e) => resume_unwind(e), - }, - } - } -} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index e6a0a7a..27b040d 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -419,7 +419,6 @@ Simulation { }, pc: 38, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -498,7 +497,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1220,7 +1218,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, - maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1230,7 +1227,6 @@ Simulation { index: StatePartIndex(1), ty: UInt<8>, }, - maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1240,7 +1236,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1250,7 +1245,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1260,7 +1254,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, - maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1270,7 +1263,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1280,7 +1272,6 @@ Simulation { index: StatePartIndex(6), ty: UInt<8>, }, - maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1290,7 +1281,6 @@ Simulation { index: StatePartIndex(7), ty: UInt<8>, }, - maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1300,7 +1290,6 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1310,7 +1299,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1320,7 +1308,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, - maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1330,7 +1317,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<8>, }, - maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1340,7 +1326,6 @@ Simulation { index: StatePartIndex(12), ty: UInt<8>, }, - maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1350,7 +1335,6 @@ Simulation { index: StatePartIndex(13), ty: UInt<8>, }, - maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1360,7 +1344,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1370,7 +1353,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, - maybe_changed: true, state: 0xfe, last_state: 0xfe, }, @@ -1380,7 +1362,6 @@ Simulation { index: StatePartIndex(16), ty: UInt<8>, }, - maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1390,7 +1371,6 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, - maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1400,7 +1380,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1410,7 +1389,6 @@ Simulation { index: StatePartIndex(19), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1420,7 +1398,6 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, - maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1430,7 +1407,6 @@ Simulation { index: StatePartIndex(21), ty: UInt<8>, }, - maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1440,7 +1416,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<8>, }, - maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1450,7 +1425,6 @@ Simulation { index: StatePartIndex(23), ty: UInt<8>, }, - maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1460,7 +1434,6 @@ Simulation { index: StatePartIndex(24), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1470,7 +1443,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<8>, }, - maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1480,7 +1452,6 @@ Simulation { index: StatePartIndex(26), ty: UInt<8>, }, - maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1490,7 +1461,6 @@ Simulation { index: StatePartIndex(27), ty: UInt<8>, }, - maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1500,7 +1470,6 @@ Simulation { index: StatePartIndex(28), ty: UInt<8>, }, - maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1510,7 +1479,6 @@ Simulation { index: StatePartIndex(29), ty: UInt<8>, }, - maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1520,7 +1488,6 @@ Simulation { index: StatePartIndex(30), ty: UInt<8>, }, - maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1530,7 +1497,6 @@ Simulation { index: StatePartIndex(31), ty: UInt<8>, }, - maybe_changed: true, state: 0xfe, last_state: 0xe1, }, @@ -1540,7 +1506,6 @@ Simulation { index: StatePartIndex(32), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1550,7 +1515,6 @@ Simulation { index: StatePartIndex(33), ty: UInt<8>, }, - maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1560,7 +1524,6 @@ Simulation { index: StatePartIndex(34), ty: UInt<8>, }, - maybe_changed: true, state: 0x10, last_state: 0x0f, }, @@ -1570,7 +1533,6 @@ Simulation { index: StatePartIndex(35), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0xe1, }, @@ -1579,7 +1541,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1589,7 +1550,6 @@ Simulation { index: StatePartIndex(37), ty: UInt<8>, }, - maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1599,7 +1559,6 @@ Simulation { index: StatePartIndex(38), ty: UInt<8>, }, - maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1609,7 +1568,6 @@ Simulation { index: StatePartIndex(39), ty: UInt<8>, }, - maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1619,7 +1577,6 @@ Simulation { index: StatePartIndex(40), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1629,7 +1586,6 @@ Simulation { index: StatePartIndex(41), ty: UInt<8>, }, - maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1639,7 +1595,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1649,7 +1604,6 @@ Simulation { index: StatePartIndex(43), ty: UInt<8>, }, - maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1659,7 +1613,6 @@ Simulation { index: StatePartIndex(44), ty: UInt<8>, }, - maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1669,7 +1622,6 @@ Simulation { index: StatePartIndex(45), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1679,7 +1631,6 @@ Simulation { index: StatePartIndex(46), ty: UInt<8>, }, - maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1689,7 +1640,6 @@ Simulation { index: StatePartIndex(47), ty: UInt<8>, }, - maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1699,7 +1649,6 @@ Simulation { index: StatePartIndex(48), ty: UInt<8>, }, - maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1709,7 +1658,6 @@ Simulation { index: StatePartIndex(49), ty: UInt<8>, }, - maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1719,7 +1667,6 @@ Simulation { index: StatePartIndex(50), ty: UInt<8>, }, - maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1729,7 +1676,6 @@ Simulation { index: StatePartIndex(51), ty: UInt<8>, }, - maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1739,7 +1685,6 @@ Simulation { index: StatePartIndex(52), ty: UInt<8>, }, - maybe_changed: true, state: 0xfe, last_state: 0xe1, }, @@ -1761,6 +1706,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index 8013727..d470792 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -76,7 +76,6 @@ Simulation { }, pc: 5, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -102,7 +101,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -157,7 +155,6 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -166,7 +163,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -188,6 +184,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index 9ec4a83..56ea4ad 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -54,7 +54,6 @@ Simulation { }, pc: 2, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -78,7 +77,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -126,7 +124,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, - maybe_changed: true, state: 0x05, last_state: 0x05, }, @@ -140,6 +137,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index dfbc3b9..6b5814a 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -80,7 +80,6 @@ Simulation { }, pc: 5, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -107,7 +106,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -177,7 +175,6 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -186,7 +183,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -208,6 +204,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index c05ed80..2bdd665 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -180,7 +180,6 @@ Simulation { }, pc: 19, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -217,7 +216,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -334,7 +332,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -343,7 +340,6 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -353,7 +349,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<4>, }, - maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -363,7 +358,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, - maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -387,6 +381,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 5834877..87c2098 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -162,7 +162,6 @@ Simulation { }, pc: 16, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -198,7 +197,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -315,7 +313,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -324,7 +321,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -334,7 +330,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<4>, }, - maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -344,7 +339,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, - maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -368,6 +362,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 3a4c115..64bbbe6 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -72,7 +72,6 @@ Simulation { }, pc: 4, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -98,7 +97,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [], uninitialized_ios: {}, @@ -139,7 +137,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, - maybe_changed: true, state: 0x05, last_state: 0x05, }, @@ -149,7 +146,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: true, state: 0x06, last_state: 0x06, }, @@ -171,6 +167,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enum_with_simple_body.txt b/crates/fayalite/tests/sim/expected/enum_with_simple_body.txt deleted file mode 100644 index e7c6a85..0000000 --- a/crates/fayalite/tests/sim/expected/enum_with_simple_body.txt +++ /dev/null @@ -1,752 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Enum { - A, - B, - C, - }, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 33, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: ".0", - ty: UInt<2>, - }, - SlotDebugData { - name: ".1", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: ".0", - ty: UInt<2>, - }, - SlotDebugData { - name: ".1", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - }, - SlotDebugData { - name: ".0", - ty: UInt<2>, - }, - SlotDebugData { - name: ".1", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: UInt<10>, - }, - SlotDebugData { - name: "", - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Const { - dest: StatePartIndex(32), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - value: 0x2, - }, - 1: Const { - dest: StatePartIndex(27), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, - value: 0x2, - }, - 2: Copy { - dest: StatePartIndex(25), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, - src: StatePartIndex(27), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, - }, - 3: Copy { - dest: StatePartIndex(26), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, - src: StatePartIndex(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> }, - }, - 4: Shl { - dest: StatePartIndex(28), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - lhs: StatePartIndex(26), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, - rhs: 2, - }, - 5: Or { - dest: StatePartIndex(29), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, - lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, - rhs: StatePartIndex(28), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - }, - 6: CastToUInt { - dest: StatePartIndex(30), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, - src: StatePartIndex(29), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, - dest_width: 10, - }, - 7: Copy { - dest: StatePartIndex(31), // (0x386) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - src: StatePartIndex(30), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, - }, - 8: Const { - dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - value: 0x1, - }, - 9: Copy { - dest: StatePartIndex(18), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, - src: StatePartIndex(20), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - 10: Copy { - dest: StatePartIndex(19), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, - src: StatePartIndex(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> }, - }, - 11: Shl { - dest: StatePartIndex(21), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - lhs: StatePartIndex(19), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, - rhs: 2, - }, - 12: Or { - dest: StatePartIndex(22), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, - lhs: StatePartIndex(18), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, - rhs: StatePartIndex(21), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - }, - 13: CastToUInt { - dest: StatePartIndex(23), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, - src: StatePartIndex(22), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, - dest_width: 10, - }, - 14: Copy { - dest: StatePartIndex(24), // (0x385) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - src: StatePartIndex(23), // (0x385) SlotDebugData { name: "", ty: UInt<10> }, - }, - 15: Const { - dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - value: 0x1, - }, - 16: CmpEq { - dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(0), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", ty: UInt<8> }, - rhs: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - }, - 17: Const { - dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - value: 0x0, - }, - 18: Copy { - dest: StatePartIndex(9), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, - src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - 19: Copy { - dest: StatePartIndex(10), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, - src: StatePartIndex(1), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_in", ty: UInt<8> }, - }, - 20: Shl { - dest: StatePartIndex(12), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - lhs: StatePartIndex(10), // (0xe1) SlotDebugData { name: ".1", ty: UInt<8> }, - rhs: 2, - }, - 21: Or { - dest: StatePartIndex(13), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - lhs: StatePartIndex(9), // (0x0) SlotDebugData { name: ".0", ty: UInt<2> }, - rhs: StatePartIndex(12), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - }, - 22: CastToUInt { - dest: StatePartIndex(14), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - src: StatePartIndex(13), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - dest_width: 10, - }, - 23: Copy { - dest: StatePartIndex(15), // (0x384) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - src: StatePartIndex(14), // (0x384) SlotDebugData { name: "", ty: UInt<10> }, - }, - 24: Const { - dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - value: 0x0, - }, - 25: CmpEq { - dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(0), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_in", ty: UInt<8> }, - rhs: StatePartIndex(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 26: BranchIfZero { - target: 28, - value: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 27: Copy { - dest: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - src: StatePartIndex(15), // (0x384) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 28: BranchIfNonZero { - target: 33, - value: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 29: BranchIfZero { - target: 31, - value: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:10:1 - 30: Copy { - dest: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - src: StatePartIndex(24), // (0x385) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 31: BranchIfNonZero { - target: 33, - value: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:11:1 - 32: Copy { - dest: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - src: StatePartIndex(31), // (0x386) SlotDebugData { name: "", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 33: Copy { - dest: StatePartIndex(5), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, - src: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - }, - 34: SliceInt { - dest: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(5), // (0x386) SlotDebugData { name: "", ty: UInt<10> }, - start: 2, - len: 8, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 35: AndBigWithSmallImmediate { - dest: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, - lhs: StatePartIndex(4), // (0x386) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::enum_out", ty: Enum {A(UInt<8>), B(UInt<8>), C(UInt<8>)} }, - rhs: 0x3, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 36: BranchIfSmallNeImmediate { - target: 39, - lhs: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, - rhs: 0x0, - }, - // at: module-XXXXXXXXXX.rs:13:1 - 37: Copy { - dest: StatePartIndex(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> }, - src: StatePartIndex(7), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:14:1 - 38: Copy { - dest: StatePartIndex(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> }, - src: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 39: BranchIfSmallNeImmediate { - target: 42, - lhs: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:15:1 - 40: Copy { - dest: StatePartIndex(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> }, - src: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:16:1 - 41: Copy { - dest: StatePartIndex(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> }, - src: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 42: BranchIfSmallNeImmediate { - target: 45, - lhs: StatePartIndex(0), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, - rhs: 0x2, - }, - // at: module-XXXXXXXXXX.rs:17:1 - 43: Copy { - dest: StatePartIndex(2), // (0x2) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::which_out", ty: UInt<8> }, - src: StatePartIndex(32), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:18:1 - 44: Copy { - dest: StatePartIndex(3), // (0xe1) SlotDebugData { name: "InstantiatedModule(enum_with_simple_body: enum_with_simple_body).enum_with_simple_body::data_out", ty: UInt<8> }, - src: StatePartIndex(6), // (0xe1) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 45: Return, - ], - .. - }, - pc: 45, - memory_write_log: [], - assert_failed_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [ - 2, - ], - }, - big_slots: StatePart { - value: [ - 2, - 225, - 2 (modified), - 225 (modified), - 902, - 902, - 225, - 0, - 0, - 0, - 225, - 0, - 900, - 900, - 900, - 900, - 1, - 0, - 1, - 225, - 1, - 900, - 901, - 901, - 901, - 2, - 225, - 2, - 900, - 902, - 902, - 902, - 2, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }, - global_io: {}, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.which_in, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.data_in, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.which_out, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.data_out, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.enum_out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.data_in, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.data_out, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.enum_out, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.which_in, - Instance { - name: ::enum_with_simple_body, - instantiated: Module { - name: enum_with_simple_body, - .. - }, - }.which_out, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [], - trace_decls: TraceModule { - name: "enum_with_simple_body", - children: [ - TraceModuleIO { - name: "which_in", - child: TraceUInt { - location: TraceScalarId(0), - name: "which_in", - ty: UInt<8>, - flow: Source, - }, - ty: UInt<8>, - flow: Source, - }, - TraceModuleIO { - name: "data_in", - child: TraceUInt { - location: TraceScalarId(1), - name: "data_in", - ty: UInt<8>, - flow: Source, - }, - ty: UInt<8>, - flow: Source, - }, - TraceModuleIO { - name: "which_out", - child: TraceUInt { - location: TraceScalarId(2), - name: "which_out", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - TraceModuleIO { - name: "data_out", - child: TraceUInt { - location: TraceScalarId(3), - name: "data_out", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - TraceModuleIO { - name: "enum_out", - child: TraceEnumWithFields { - name: "enum_out", - discriminant: TraceEnumDiscriminant { - location: TraceScalarId(4), - name: "$tag", - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - flow: Sink, - }, - non_empty_fields: [ - TraceUInt { - location: TraceScalarId(5), - name: "A", - ty: UInt<8>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(6), - name: "B", - ty: UInt<8>, - flow: Source, - }, - TraceUInt { - location: TraceScalarId(7), - name: "C", - ty: UInt<8>, - flow: Source, - }, - ], - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - flow: Sink, - }, - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigUInt { - index: StatePartIndex(0), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigUInt { - index: StatePartIndex(1), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0xe1, - last_state: 0xb4, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0x02, - last_state: 0x02, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0xe1, - last_state: 0xb4, - }, - SimTrace { - id: TraceScalarId(4), - kind: EnumDiscriminant { - index: StatePartIndex(0), - ty: Enum { - A(UInt<8>), - B(UInt<8>), - C(UInt<8>), - }, - }, - maybe_changed: true, - state: 0x2, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigUInt { - index: StatePartIndex(6), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0xe1, - last_state: 0xb4, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigUInt { - index: StatePartIndex(6), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0xe1, - last_state: 0xb4, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigUInt { - index: StatePartIndex(6), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0xe1, - last_state: 0xb4, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 18 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd b/crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd deleted file mode 100644 index dfe0dc1..0000000 --- a/crates/fayalite/tests/sim/expected/enum_with_simple_body.vcd +++ /dev/null @@ -1,133 +0,0 @@ -$timescale 1 ps $end -$scope module enum_with_simple_body $end -$var wire 8 J&-ne which_in $end -$var wire 8 \7mo/ data_in $end -$var wire 8 ,`>ir which_out $end -$var wire 8 0_gMP data_out $end -$scope struct enum_out $end -$var string 1 kFH/w \$tag $end -$var wire 8 |EI_= A $end -$var wire 8 !pRd4 B $end -$var wire 8 &RAbd C $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -b0 J&-ne -b0 \7mo/ -b0 ,`>ir -b0 0_gMP -sA\x20(0) kFH/w -b0 |EI_= -b0 !pRd4 -b0 &RAbd -$end -#1000000 -b101101 \7mo/ -b101101 0_gMP -b101101 |EI_= -b101101 !pRd4 -b101101 &RAbd -#2000000 -b1011010 \7mo/ -b1011010 0_gMP -b1011010 |EI_= -b1011010 !pRd4 -b1011010 &RAbd -#3000000 -b10000111 \7mo/ -b10000111 0_gMP -b10000111 |EI_= -b10000111 !pRd4 -b10000111 &RAbd -#4000000 -b10110100 \7mo/ -b10110100 0_gMP -b10110100 |EI_= -b10110100 !pRd4 -b10110100 &RAbd -#5000000 -b11100001 \7mo/ -b11100001 0_gMP -b11100001 |EI_= -b11100001 !pRd4 -b11100001 &RAbd -#6000000 -b1 J&-ne -b0 \7mo/ -b1 ,`>ir -b0 0_gMP -sB\x20(1) kFH/w -b0 |EI_= -b0 !pRd4 -b0 &RAbd -#7000000 -b101101 \7mo/ -b101101 0_gMP -b101101 |EI_= -b101101 !pRd4 -b101101 &RAbd -#8000000 -b1011010 \7mo/ -b1011010 0_gMP -b1011010 |EI_= -b1011010 !pRd4 -b1011010 &RAbd -#9000000 -b10000111 \7mo/ -b10000111 0_gMP -b10000111 |EI_= -b10000111 !pRd4 -b10000111 &RAbd -#10000000 -b10110100 \7mo/ -b10110100 0_gMP -b10110100 |EI_= -b10110100 !pRd4 -b10110100 &RAbd -#11000000 -b11100001 \7mo/ -b11100001 0_gMP -b11100001 |EI_= -b11100001 !pRd4 -b11100001 &RAbd -#12000000 -b10 J&-ne -b0 \7mo/ -b10 ,`>ir -b0 0_gMP -sC\x20(2) kFH/w -b0 |EI_= -b0 !pRd4 -b0 &RAbd -#13000000 -b101101 \7mo/ -b101101 0_gMP -b101101 |EI_= -b101101 !pRd4 -b101101 &RAbd -#14000000 -b1011010 \7mo/ -b1011010 0_gMP -b1011010 |EI_= -b1011010 !pRd4 -b1011010 &RAbd -#15000000 -b10000111 \7mo/ -b10000111 0_gMP -b10000111 |EI_= -b10000111 !pRd4 -b10000111 &RAbd -#16000000 -b10110100 \7mo/ -b10110100 0_gMP -b10110100 |EI_= -b10110100 !pRd4 -b10110100 &RAbd -#17000000 -b11100001 \7mo/ -b11100001 0_gMP -b11100001 |EI_= -b11100001 !pRd4 -b11100001 &RAbd -#18000000 diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index a539f96..a3a52cb 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1184,7 +1184,6 @@ Simulation { }, pc: 133, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -1325,7 +1324,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1748,7 +1746,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -1757,7 +1754,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1766,7 +1762,6 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, - maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -1776,7 +1771,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<2>, }, - maybe_changed: false, state: 0x2, last_state: 0x2, }, @@ -1786,7 +1780,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, - maybe_changed: false, state: 0xf, last_state: 0xf, }, @@ -1796,7 +1789,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1806,7 +1798,6 @@ Simulation { index: StatePartIndex(6), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -1819,7 +1810,6 @@ Simulation { HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1829,7 +1819,6 @@ Simulation { index: StatePartIndex(8), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1838,7 +1827,6 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1851,7 +1839,6 @@ Simulation { HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1861,7 +1848,6 @@ Simulation { index: StatePartIndex(16), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1870,7 +1856,6 @@ Simulation { kind: BigBool { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1884,7 +1869,6 @@ Simulation { C(Bundle {a: Array, 2>, b: SInt<2>}), }, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1894,7 +1878,6 @@ Simulation { index: StatePartIndex(27), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1903,7 +1886,6 @@ Simulation { kind: BigBool { index: StatePartIndex(28), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1913,7 +1895,6 @@ Simulation { index: StatePartIndex(34), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1923,7 +1904,6 @@ Simulation { index: StatePartIndex(35), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1933,7 +1913,6 @@ Simulation { index: StatePartIndex(36), ty: SInt<2>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1957,6 +1936,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index fa003d3..f49106f 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -44,7 +44,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -68,7 +67,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -223,7 +221,6 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, - maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -232,7 +229,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -263,6 +259,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 8c03792..365830f 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -48,7 +48,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -58,7 +57,7 @@ Simulation { big_slots: StatePart { value: [ 0, - 1 (modified), + 1, 101, ], }, @@ -73,7 +72,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -282,7 +280,6 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -291,7 +288,6 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -301,7 +297,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: false, state: 0x65, last_state: 0x65, }, @@ -418,6 +413,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/last_connect.txt b/crates/fayalite/tests/sim/expected/last_connect.txt index e62c0b7..6a43497 100644 --- a/crates/fayalite/tests/sim/expected/last_connect.txt +++ b/crates/fayalite/tests/sim/expected/last_connect.txt @@ -407,7 +407,6 @@ Simulation { }, pc: 44, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -434,7 +433,7 @@ Simulation { 1, 1, 1, - 7 (modified), + 7, 7, 3, 0, @@ -465,7 +464,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -616,7 +614,6 @@ Simulation { HdlSome(Array), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -625,7 +622,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -634,7 +630,6 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -643,7 +638,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -652,7 +646,6 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -665,7 +658,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -675,7 +667,6 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, - maybe_changed: true, state: 0x03, last_state: 0x02, }, @@ -685,7 +676,6 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, - maybe_changed: true, state: 0x03, last_state: 0x02, }, @@ -707,6 +697,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index 1cb60ae..c521d72 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -2728,7 +2728,6 @@ Simulation { }, pc: 256, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -3184,7 +3183,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -5547,7 +5545,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5556,7 +5553,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5565,7 +5561,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5574,7 +5569,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5584,7 +5578,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5593,7 +5586,6 @@ Simulation { kind: BigBool { index: StatePartIndex(5), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5602,7 +5594,6 @@ Simulation { kind: BigClock { index: StatePartIndex(6), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5611,7 +5602,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5621,7 +5611,6 @@ Simulation { index: StatePartIndex(8), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5630,7 +5619,6 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5639,7 +5627,6 @@ Simulation { kind: BigClock { index: StatePartIndex(10), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5648,7 +5635,6 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5658,7 +5644,6 @@ Simulation { index: StatePartIndex(12), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5667,7 +5652,6 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5676,7 +5660,6 @@ Simulation { kind: BigClock { index: StatePartIndex(14), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5685,7 +5668,6 @@ Simulation { kind: BigBool { index: StatePartIndex(15), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5695,7 +5677,6 @@ Simulation { index: StatePartIndex(16), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5704,7 +5685,6 @@ Simulation { kind: BigBool { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5713,7 +5693,6 @@ Simulation { kind: BigClock { index: StatePartIndex(18), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5722,7 +5701,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5732,7 +5710,6 @@ Simulation { index: StatePartIndex(20), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5741,7 +5718,6 @@ Simulation { kind: BigBool { index: StatePartIndex(21), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5750,7 +5726,6 @@ Simulation { kind: BigClock { index: StatePartIndex(22), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5759,7 +5734,6 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5769,7 +5743,6 @@ Simulation { index: StatePartIndex(24), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5778,7 +5751,6 @@ Simulation { kind: BigBool { index: StatePartIndex(25), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5787,7 +5759,6 @@ Simulation { kind: BigClock { index: StatePartIndex(26), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5796,7 +5767,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5806,7 +5776,6 @@ Simulation { index: StatePartIndex(28), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5815,7 +5784,6 @@ Simulation { kind: BigBool { index: StatePartIndex(29), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5824,7 +5792,6 @@ Simulation { kind: BigClock { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5833,7 +5800,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5843,7 +5809,6 @@ Simulation { index: StatePartIndex(32), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5852,7 +5817,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5861,7 +5825,6 @@ Simulation { kind: BigClock { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5870,7 +5833,6 @@ Simulation { kind: BigBool { index: StatePartIndex(35), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5879,7 +5841,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5889,7 +5850,6 @@ Simulation { index: StatePartIndex(37), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5898,7 +5858,6 @@ Simulation { kind: BigBool { index: StatePartIndex(38), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5907,7 +5866,6 @@ Simulation { kind: BigClock { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5916,7 +5874,6 @@ Simulation { kind: BigBool { index: StatePartIndex(40), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5925,7 +5882,6 @@ Simulation { kind: BigBool { index: StatePartIndex(41), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5935,7 +5891,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5944,7 +5899,6 @@ Simulation { kind: BigBool { index: StatePartIndex(43), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5953,7 +5907,6 @@ Simulation { kind: BigClock { index: StatePartIndex(44), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5962,7 +5915,6 @@ Simulation { kind: BigBool { index: StatePartIndex(45), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5971,7 +5923,6 @@ Simulation { kind: BigBool { index: StatePartIndex(46), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5981,7 +5932,6 @@ Simulation { index: StatePartIndex(47), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5990,7 +5940,6 @@ Simulation { kind: BigBool { index: StatePartIndex(48), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5999,7 +5948,6 @@ Simulation { kind: BigClock { index: StatePartIndex(49), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6008,7 +5956,6 @@ Simulation { kind: BigBool { index: StatePartIndex(50), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6017,7 +5964,6 @@ Simulation { kind: BigBool { index: StatePartIndex(51), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6027,7 +5973,6 @@ Simulation { index: StatePartIndex(52), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6036,7 +5981,6 @@ Simulation { kind: BigBool { index: StatePartIndex(53), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6045,7 +5989,6 @@ Simulation { kind: BigClock { index: StatePartIndex(54), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6054,7 +5997,6 @@ Simulation { kind: BigBool { index: StatePartIndex(55), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6063,7 +6005,6 @@ Simulation { kind: BigBool { index: StatePartIndex(56), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6073,7 +6014,6 @@ Simulation { index: StatePartIndex(57), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6082,7 +6022,6 @@ Simulation { kind: BigBool { index: StatePartIndex(58), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6091,7 +6030,6 @@ Simulation { kind: BigClock { index: StatePartIndex(59), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6100,7 +6038,6 @@ Simulation { kind: BigBool { index: StatePartIndex(60), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6109,7 +6046,6 @@ Simulation { kind: BigBool { index: StatePartIndex(61), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6119,7 +6055,6 @@ Simulation { index: StatePartIndex(62), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6128,7 +6063,6 @@ Simulation { kind: BigBool { index: StatePartIndex(63), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6137,7 +6071,6 @@ Simulation { kind: BigClock { index: StatePartIndex(64), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6146,7 +6079,6 @@ Simulation { kind: BigBool { index: StatePartIndex(65), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6155,7 +6087,6 @@ Simulation { kind: BigBool { index: StatePartIndex(66), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6165,7 +6096,6 @@ Simulation { index: StatePartIndex(67), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6174,7 +6104,6 @@ Simulation { kind: BigBool { index: StatePartIndex(68), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6183,7 +6112,6 @@ Simulation { kind: BigClock { index: StatePartIndex(69), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6192,7 +6120,6 @@ Simulation { kind: BigBool { index: StatePartIndex(70), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6201,7 +6128,6 @@ Simulation { kind: BigBool { index: StatePartIndex(71), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6211,7 +6137,6 @@ Simulation { index: StatePartIndex(72), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6220,7 +6145,6 @@ Simulation { kind: BigBool { index: StatePartIndex(73), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6229,7 +6153,6 @@ Simulation { kind: BigClock { index: StatePartIndex(74), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6238,7 +6161,6 @@ Simulation { kind: BigBool { index: StatePartIndex(75), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6248,7 +6170,6 @@ Simulation { index: StatePartIndex(76), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6257,7 +6178,6 @@ Simulation { kind: BigBool { index: StatePartIndex(77), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6266,7 +6186,6 @@ Simulation { kind: BigClock { index: StatePartIndex(78), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6275,7 +6194,6 @@ Simulation { kind: BigBool { index: StatePartIndex(79), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6284,7 +6202,6 @@ Simulation { kind: BigBool { index: StatePartIndex(80), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6294,7 +6211,6 @@ Simulation { index: StatePartIndex(83), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6303,7 +6219,6 @@ Simulation { kind: BigBool { index: StatePartIndex(84), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6312,7 +6227,6 @@ Simulation { kind: BigClock { index: StatePartIndex(85), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6321,7 +6235,6 @@ Simulation { kind: BigBool { index: StatePartIndex(86), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6331,7 +6244,6 @@ Simulation { index: StatePartIndex(87), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6340,7 +6252,6 @@ Simulation { kind: BigBool { index: StatePartIndex(88), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6349,7 +6260,6 @@ Simulation { kind: BigClock { index: StatePartIndex(89), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6358,7 +6268,6 @@ Simulation { kind: BigBool { index: StatePartIndex(90), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6367,7 +6276,6 @@ Simulation { kind: BigBool { index: StatePartIndex(91), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6377,7 +6285,6 @@ Simulation { index: StatePartIndex(94), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6386,7 +6293,6 @@ Simulation { kind: BigBool { index: StatePartIndex(95), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6395,7 +6301,6 @@ Simulation { kind: BigClock { index: StatePartIndex(96), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6404,7 +6309,6 @@ Simulation { kind: BigBool { index: StatePartIndex(97), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6414,7 +6318,6 @@ Simulation { index: StatePartIndex(98), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6423,7 +6326,6 @@ Simulation { kind: BigBool { index: StatePartIndex(99), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6432,7 +6334,6 @@ Simulation { kind: BigClock { index: StatePartIndex(100), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6441,7 +6342,6 @@ Simulation { kind: BigBool { index: StatePartIndex(101), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6450,7 +6350,6 @@ Simulation { kind: BigBool { index: StatePartIndex(102), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6460,7 +6359,6 @@ Simulation { index: StatePartIndex(105), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6469,7 +6367,6 @@ Simulation { kind: BigBool { index: StatePartIndex(106), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6478,7 +6375,6 @@ Simulation { kind: BigClock { index: StatePartIndex(107), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6487,7 +6383,6 @@ Simulation { kind: BigBool { index: StatePartIndex(108), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6497,7 +6392,6 @@ Simulation { index: StatePartIndex(109), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6506,7 +6400,6 @@ Simulation { kind: BigBool { index: StatePartIndex(110), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6515,7 +6408,6 @@ Simulation { kind: BigClock { index: StatePartIndex(111), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6524,7 +6416,6 @@ Simulation { kind: BigBool { index: StatePartIndex(112), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6533,7 +6424,6 @@ Simulation { kind: BigBool { index: StatePartIndex(113), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6543,7 +6433,6 @@ Simulation { index: StatePartIndex(116), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6552,7 +6441,6 @@ Simulation { kind: BigBool { index: StatePartIndex(117), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6561,7 +6449,6 @@ Simulation { kind: BigClock { index: StatePartIndex(118), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6570,7 +6457,6 @@ Simulation { kind: BigBool { index: StatePartIndex(119), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6580,7 +6466,6 @@ Simulation { index: StatePartIndex(120), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6589,7 +6474,6 @@ Simulation { kind: BigBool { index: StatePartIndex(121), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6598,7 +6482,6 @@ Simulation { kind: BigClock { index: StatePartIndex(122), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6607,7 +6490,6 @@ Simulation { kind: BigBool { index: StatePartIndex(123), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6616,7 +6498,6 @@ Simulation { kind: BigBool { index: StatePartIndex(124), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6626,7 +6507,6 @@ Simulation { index: StatePartIndex(127), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6635,7 +6515,6 @@ Simulation { kind: BigBool { index: StatePartIndex(128), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6644,7 +6523,6 @@ Simulation { kind: BigClock { index: StatePartIndex(129), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6653,7 +6531,6 @@ Simulation { kind: BigBool { index: StatePartIndex(130), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6663,7 +6540,6 @@ Simulation { index: StatePartIndex(131), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6672,7 +6548,6 @@ Simulation { kind: BigBool { index: StatePartIndex(132), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6681,7 +6556,6 @@ Simulation { kind: BigClock { index: StatePartIndex(133), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6690,7 +6564,6 @@ Simulation { kind: BigBool { index: StatePartIndex(134), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6699,7 +6572,6 @@ Simulation { kind: BigBool { index: StatePartIndex(135), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6709,7 +6581,6 @@ Simulation { index: StatePartIndex(138), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6718,7 +6589,6 @@ Simulation { kind: BigBool { index: StatePartIndex(139), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6727,7 +6597,6 @@ Simulation { kind: BigClock { index: StatePartIndex(140), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6736,7 +6605,6 @@ Simulation { kind: BigBool { index: StatePartIndex(141), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6746,7 +6614,6 @@ Simulation { index: StatePartIndex(142), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6755,7 +6622,6 @@ Simulation { kind: BigBool { index: StatePartIndex(143), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6764,7 +6630,6 @@ Simulation { kind: BigClock { index: StatePartIndex(144), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6773,7 +6638,6 @@ Simulation { kind: BigBool { index: StatePartIndex(145), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6782,7 +6646,6 @@ Simulation { kind: BigBool { index: StatePartIndex(146), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6792,7 +6655,6 @@ Simulation { index: StatePartIndex(149), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6801,7 +6663,6 @@ Simulation { kind: BigBool { index: StatePartIndex(150), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6810,7 +6671,6 @@ Simulation { kind: BigClock { index: StatePartIndex(151), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6819,7 +6679,6 @@ Simulation { kind: BigBool { index: StatePartIndex(152), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6829,7 +6688,6 @@ Simulation { index: StatePartIndex(153), ty: UInt<4>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6838,7 +6696,6 @@ Simulation { kind: BigBool { index: StatePartIndex(154), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6847,7 +6704,6 @@ Simulation { kind: BigClock { index: StatePartIndex(155), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6856,7 +6712,6 @@ Simulation { kind: BigBool { index: StatePartIndex(156), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6865,7 +6720,6 @@ Simulation { kind: BigBool { index: StatePartIndex(157), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -7929,6 +7783,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index f2f4fb6..0358bb3 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -494,7 +494,6 @@ Simulation { }, pc: 41, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -580,7 +579,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1170,7 +1168,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1179,7 +1176,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1188,7 +1184,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1198,7 +1193,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, - maybe_changed: true, state: 0xb0, last_state: 0xb0, }, @@ -1208,7 +1202,6 @@ Simulation { index: StatePartIndex(4), ty: SInt<8>, }, - maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1218,7 +1211,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<4>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1227,7 +1219,6 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1236,7 +1227,6 @@ Simulation { kind: BigClock { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1246,7 +1236,6 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, - maybe_changed: true, state: 0xd0, last_state: 0xd0, }, @@ -1256,7 +1245,6 @@ Simulation { index: StatePartIndex(9), ty: SInt<8>, }, - maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1265,7 +1253,6 @@ Simulation { kind: BigBool { index: StatePartIndex(10), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1274,7 +1261,6 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1284,7 +1270,6 @@ Simulation { index: StatePartIndex(12), ty: UInt<4>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1293,7 +1278,6 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1302,7 +1286,6 @@ Simulation { kind: BigClock { index: StatePartIndex(14), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1312,7 +1295,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, - maybe_changed: true, state: 0xb0, last_state: 0xb0, }, @@ -1322,7 +1304,6 @@ Simulation { index: StatePartIndex(16), ty: SInt<8>, }, - maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1332,7 +1313,6 @@ Simulation { index: StatePartIndex(17), ty: UInt<4>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1341,7 +1321,6 @@ Simulation { kind: BigBool { index: StatePartIndex(18), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1350,7 +1329,6 @@ Simulation { kind: BigClock { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1360,7 +1338,6 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, - maybe_changed: true, state: 0xd0, last_state: 0xd0, }, @@ -1370,7 +1347,6 @@ Simulation { index: StatePartIndex(21), ty: SInt<8>, }, - maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1379,7 +1355,6 @@ Simulation { kind: BigBool { index: StatePartIndex(22), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1388,7 +1363,6 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1652,6 +1626,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index 239802c..b4041ba 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -526,7 +526,6 @@ Simulation { }, pc: 52, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -608,7 +607,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -945,7 +943,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<3>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -954,7 +951,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -963,7 +959,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -973,7 +968,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -982,7 +976,6 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -992,7 +985,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<2>, }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1001,7 +993,6 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1011,7 +1002,6 @@ Simulation { index: StatePartIndex(7), ty: UInt<3>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1020,7 +1010,6 @@ Simulation { kind: BigBool { index: StatePartIndex(8), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1029,7 +1018,6 @@ Simulation { kind: BigClock { index: StatePartIndex(9), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1042,7 +1030,6 @@ Simulation { HdlSome(Bool), }, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1051,7 +1038,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1060,7 +1046,6 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1073,7 +1058,6 @@ Simulation { HdlSome(Bool), }, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1082,7 +1066,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1091,7 +1074,6 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1287,6 +1269,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 1fcbab1..2213912 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1336,7 +1336,6 @@ Simulation { }, pc: 129, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1496,7 +1495,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -2393,7 +2391,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<3>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2402,7 +2399,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2411,7 +2407,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2421,7 +2416,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2431,7 +2425,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2441,7 +2434,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2451,7 +2443,6 @@ Simulation { index: StatePartIndex(6), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2461,7 +2452,6 @@ Simulation { index: StatePartIndex(7), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2471,7 +2461,6 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2481,7 +2470,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2491,7 +2479,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2501,7 +2488,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<3>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2510,7 +2496,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2519,7 +2504,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2529,7 +2513,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2539,7 +2522,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2549,7 +2531,6 @@ Simulation { index: StatePartIndex(16), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2559,7 +2540,6 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2569,7 +2549,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2579,7 +2558,6 @@ Simulation { index: StatePartIndex(19), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2589,7 +2567,6 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2599,7 +2576,6 @@ Simulation { index: StatePartIndex(21), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2608,7 +2584,6 @@ Simulation { kind: BigBool { index: StatePartIndex(22), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2617,7 +2592,6 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2626,7 +2600,6 @@ Simulation { kind: BigBool { index: StatePartIndex(24), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2635,7 +2608,6 @@ Simulation { kind: BigBool { index: StatePartIndex(25), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2644,7 +2616,6 @@ Simulation { kind: BigBool { index: StatePartIndex(26), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2653,7 +2624,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2662,7 +2632,6 @@ Simulation { kind: BigBool { index: StatePartIndex(28), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2671,7 +2640,6 @@ Simulation { kind: BigBool { index: StatePartIndex(29), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2681,7 +2649,6 @@ Simulation { index: StatePartIndex(30), ty: UInt<3>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2690,7 +2657,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2699,7 +2665,6 @@ Simulation { kind: BigClock { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2709,7 +2674,6 @@ Simulation { index: StatePartIndex(33), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2719,7 +2683,6 @@ Simulation { index: StatePartIndex(34), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2729,7 +2692,6 @@ Simulation { index: StatePartIndex(35), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2739,7 +2701,6 @@ Simulation { index: StatePartIndex(36), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2749,7 +2710,6 @@ Simulation { index: StatePartIndex(37), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2759,7 +2719,6 @@ Simulation { index: StatePartIndex(38), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2769,7 +2728,6 @@ Simulation { index: StatePartIndex(39), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2779,7 +2737,6 @@ Simulation { index: StatePartIndex(40), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2789,7 +2746,6 @@ Simulation { index: StatePartIndex(57), ty: UInt<3>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2798,7 +2754,6 @@ Simulation { kind: BigBool { index: StatePartIndex(58), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2807,7 +2762,6 @@ Simulation { kind: BigClock { index: StatePartIndex(59), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2817,7 +2771,6 @@ Simulation { index: StatePartIndex(60), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2827,7 +2780,6 @@ Simulation { index: StatePartIndex(61), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2837,7 +2789,6 @@ Simulation { index: StatePartIndex(62), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2847,7 +2798,6 @@ Simulation { index: StatePartIndex(63), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2857,7 +2807,6 @@ Simulation { index: StatePartIndex(64), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2867,7 +2816,6 @@ Simulation { index: StatePartIndex(65), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2877,7 +2825,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2887,7 +2834,6 @@ Simulation { index: StatePartIndex(67), ty: UInt<8>, }, - maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2896,7 +2842,6 @@ Simulation { kind: BigBool { index: StatePartIndex(68), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2905,7 +2850,6 @@ Simulation { kind: BigBool { index: StatePartIndex(69), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2914,7 +2858,6 @@ Simulation { kind: BigBool { index: StatePartIndex(70), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2923,7 +2866,6 @@ Simulation { kind: BigBool { index: StatePartIndex(71), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2932,7 +2874,6 @@ Simulation { kind: BigBool { index: StatePartIndex(72), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2941,7 +2882,6 @@ Simulation { kind: BigBool { index: StatePartIndex(73), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2950,7 +2890,6 @@ Simulation { kind: BigBool { index: StatePartIndex(74), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2959,7 +2898,6 @@ Simulation { kind: BigBool { index: StatePartIndex(75), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -3347,6 +3285,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index ab144d3..3f7a55e 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -187,7 +187,6 @@ Simulation { }, pc: 17, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -226,7 +225,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -447,7 +445,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, - maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -457,7 +454,6 @@ Simulation { index: StatePartIndex(1), ty: SInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -467,7 +463,6 @@ Simulation { index: StatePartIndex(2), ty: SInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -477,7 +472,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -487,7 +481,6 @@ Simulation { index: StatePartIndex(8), ty: UInt<4>, }, - maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -497,7 +490,6 @@ Simulation { index: StatePartIndex(9), ty: SInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -507,7 +499,6 @@ Simulation { index: StatePartIndex(10), ty: SInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -517,7 +508,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -527,7 +517,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, - maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -537,7 +526,6 @@ Simulation { index: StatePartIndex(5), ty: SInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -547,7 +535,6 @@ Simulation { index: StatePartIndex(6), ty: SInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -557,7 +544,6 @@ Simulation { index: StatePartIndex(7), ty: UInt<4>, }, - maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -579,6 +565,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt index 60ccff5..94072ac 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.txt +++ b/crates/fayalite/tests/sim/expected/phantom_const.txt @@ -172,7 +172,6 @@ Simulation { }, pc: 16, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -216,7 +215,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -375,7 +373,6 @@ Simulation { ["a","b"], ), }, - maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -386,7 +383,6 @@ Simulation { ["a","b"], ), }, - maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -396,7 +392,6 @@ Simulation { index: StatePartIndex(0), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -405,7 +400,6 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -414,7 +408,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -425,7 +418,6 @@ Simulation { "mem_element", ), }, - maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -529,6 +521,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt index 6586ce5..570c08d 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt @@ -1083,7 +1083,6 @@ Simulation { }, pc: 134, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1202,7 +1201,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1724,7 +1722,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1733,7 +1730,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1746,7 +1742,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1756,7 +1751,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1765,7 +1759,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1778,7 +1771,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1788,7 +1780,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1797,7 +1788,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1807,7 +1797,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1817,7 +1806,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1826,7 +1814,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1835,7 +1822,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1845,7 +1831,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1855,7 +1840,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1864,7 +1848,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1873,7 +1856,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1883,7 +1865,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1892,7 +1873,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1902,7 +1882,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1912,7 +1891,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1921,7 +1899,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1930,7 +1907,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1939,7 +1915,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1948,7 +1923,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1957,7 +1931,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1966,7 +1939,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1975,7 +1947,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1984,7 +1955,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1994,7 +1964,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -2004,7 +1973,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2162,6 +2130,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_true.txt b/crates/fayalite/tests/sim/expected/queue_1_false_true.txt index 3fabc74..5bff275 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_false_true.txt @@ -1064,7 +1064,6 @@ Simulation { }, pc: 132, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1181,7 +1180,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1703,7 +1701,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1712,7 +1709,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1725,7 +1721,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1735,7 +1730,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1744,7 +1738,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1757,7 +1750,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1767,7 +1759,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1776,7 +1767,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1786,7 +1776,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1796,7 +1785,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1805,7 +1793,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1814,7 +1801,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1824,7 +1810,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1834,7 +1819,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1843,7 +1827,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1852,7 +1835,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1862,7 +1844,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1871,7 +1852,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1881,7 +1861,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1891,7 +1870,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1900,7 +1878,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1909,7 +1886,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1918,7 +1894,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1927,7 +1902,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1936,7 +1910,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1945,7 +1918,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1954,7 +1926,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1963,7 +1934,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1973,7 +1943,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1983,7 +1952,6 @@ Simulation { index: StatePartIndex(64), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2141,6 +2109,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_false.txt b/crates/fayalite/tests/sim/expected/queue_1_true_false.txt index 54a2d06..d9771dc 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_true_false.txt @@ -1093,7 +1093,6 @@ Simulation { }, pc: 136, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1212,7 +1211,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1734,7 +1732,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1743,7 +1740,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1756,7 +1752,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1766,7 +1761,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1775,7 +1769,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1788,7 +1781,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1798,7 +1790,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1807,7 +1798,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1817,7 +1807,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1827,7 +1816,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1836,7 +1824,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1845,7 +1832,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1855,7 +1841,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1865,7 +1850,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1874,7 +1858,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1883,7 +1866,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1893,7 +1875,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1902,7 +1883,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1912,7 +1892,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1922,7 +1901,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1931,7 +1909,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1940,7 +1917,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1949,7 +1925,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1958,7 +1933,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1967,7 +1941,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1976,7 +1949,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1985,7 +1957,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1994,7 +1965,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2004,7 +1974,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -2014,7 +1983,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2172,6 +2140,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_true.txt b/crates/fayalite/tests/sim/expected/queue_1_true_true.txt index f0e86e5..0e16d2d 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_true_true.txt @@ -1074,7 +1074,6 @@ Simulation { }, pc: 134, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1191,7 +1190,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1713,7 +1711,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1722,7 +1719,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1735,7 +1731,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1745,7 +1740,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1754,7 +1748,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1767,7 +1760,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1777,7 +1769,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1786,7 +1777,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1796,7 +1786,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1806,7 +1795,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1815,7 +1803,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1824,7 +1811,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1834,7 +1820,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1844,7 +1829,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1853,7 +1837,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1862,7 +1845,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1872,7 +1854,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1881,7 +1862,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1891,7 +1871,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1901,7 +1880,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1910,7 +1888,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1919,7 +1896,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1928,7 +1904,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1937,7 +1912,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1946,7 +1920,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1955,7 +1928,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1964,7 +1936,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1973,7 +1944,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1983,7 +1953,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1993,7 +1962,6 @@ Simulation { index: StatePartIndex(64), ty: UInt<0>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2151,6 +2119,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_false.txt b/crates/fayalite/tests/sim/expected/queue_2_false_false.txt index 6bf6992..23b0a7b 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_false_false.txt @@ -1098,7 +1098,6 @@ Simulation { }, pc: 135, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1220,7 +1219,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1742,7 +1740,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1751,7 +1748,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1764,7 +1760,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1774,7 +1769,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1783,7 +1777,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1796,7 +1789,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1806,7 +1798,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1815,7 +1806,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1825,7 +1815,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1835,7 +1824,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1844,7 +1832,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1853,7 +1840,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1863,7 +1849,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1873,7 +1858,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1882,7 +1866,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1891,7 +1874,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1901,7 +1883,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1910,7 +1891,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1920,7 +1900,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1930,7 +1909,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1939,7 +1917,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1948,7 +1925,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1957,7 +1933,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1966,7 +1941,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1975,7 +1949,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1984,7 +1957,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1993,7 +1965,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2002,7 +1973,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2012,7 +1982,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -2022,7 +1991,6 @@ Simulation { index: StatePartIndex(68), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2180,6 +2148,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_true.txt b/crates/fayalite/tests/sim/expected/queue_2_false_true.txt index 2fe8866..a057fa7 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_false_true.txt @@ -1079,7 +1079,6 @@ Simulation { }, pc: 133, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1199,7 +1198,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1721,7 +1719,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1730,7 +1727,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1743,7 +1739,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1753,7 +1748,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1762,7 +1756,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1775,7 +1768,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1785,7 +1777,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1794,7 +1785,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1804,7 +1794,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1814,7 +1803,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1823,7 +1811,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1832,7 +1819,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1842,7 +1828,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1852,7 +1837,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1861,7 +1845,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1870,7 +1853,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1880,7 +1862,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1889,7 +1870,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1899,7 +1879,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1909,7 +1888,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1918,7 +1896,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1927,7 +1904,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1936,7 +1912,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1945,7 +1920,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1954,7 +1928,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1963,7 +1936,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1972,7 +1944,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1981,7 +1952,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1991,7 +1961,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -2001,7 +1970,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2159,6 +2127,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_false.txt b/crates/fayalite/tests/sim/expected/queue_2_true_false.txt index cc340b8..1f6d8ec 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_true_false.txt @@ -1108,7 +1108,6 @@ Simulation { }, pc: 137, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1230,7 +1229,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1752,7 +1750,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1761,7 +1758,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1774,7 +1770,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1784,7 +1779,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1793,7 +1787,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1806,7 +1799,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1816,7 +1808,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1825,7 +1816,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1835,7 +1825,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1845,7 +1834,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1854,7 +1842,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1863,7 +1850,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1873,7 +1859,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1883,7 +1868,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1892,7 +1876,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1901,7 +1884,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1911,7 +1893,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1920,7 +1901,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1930,7 +1910,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1940,7 +1919,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1949,7 +1927,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1958,7 +1935,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1967,7 +1943,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1976,7 +1951,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1985,7 +1959,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1994,7 +1967,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2003,7 +1975,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2012,7 +1983,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2022,7 +1992,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -2032,7 +2001,6 @@ Simulation { index: StatePartIndex(68), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2190,6 +2158,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_true.txt b/crates/fayalite/tests/sim/expected/queue_2_true_true.txt index 9cc2206..25b08a1 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_true_true.txt @@ -1089,7 +1089,6 @@ Simulation { }, pc: 135, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1209,7 +1208,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1731,7 +1729,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1740,7 +1737,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1753,7 +1749,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1763,7 +1758,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1772,7 +1766,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1785,7 +1778,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1795,7 +1787,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1804,7 +1795,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1814,7 +1804,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1824,7 +1813,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1833,7 +1821,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1842,7 +1829,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1852,7 +1838,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1862,7 +1847,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1871,7 +1855,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1880,7 +1863,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1890,7 +1872,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1899,7 +1880,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1909,7 +1889,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1919,7 +1898,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1928,7 +1906,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1937,7 +1914,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1946,7 +1922,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1955,7 +1930,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1964,7 +1938,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1973,7 +1946,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1982,7 +1954,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1991,7 +1962,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2001,7 +1971,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -2011,7 +1980,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<1>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2169,6 +2137,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_false.txt b/crates/fayalite/tests/sim/expected/queue_3_false_false.txt index 1086ca0..6f65006 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_false_false.txt @@ -1125,7 +1125,6 @@ Simulation { }, pc: 139, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1249,7 +1248,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1761,7 +1759,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1770,7 +1767,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1783,7 +1779,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1793,7 +1788,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x28, last_state: 0x28, }, @@ -1802,7 +1796,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1815,7 +1808,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1825,7 +1817,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1834,7 +1825,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1844,7 +1834,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1854,7 +1843,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1863,7 +1851,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1872,7 +1859,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1882,7 +1868,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1892,7 +1877,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1901,7 +1885,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1910,7 +1893,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1920,7 +1902,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x28, last_state: 0x28, }, @@ -1929,7 +1910,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1939,7 +1919,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1949,7 +1928,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1958,7 +1936,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1967,7 +1944,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1976,7 +1952,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1985,7 +1960,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1994,7 +1968,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2003,7 +1976,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2012,7 +1984,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2021,7 +1992,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2031,7 +2001,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x28, last_state: 0x28, }, @@ -2189,6 +2158,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_true.txt b/crates/fayalite/tests/sim/expected/queue_3_false_true.txt index 1e95f7b..4cffcd6 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_false_true.txt @@ -1106,7 +1106,6 @@ Simulation { }, pc: 137, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1228,7 +1227,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1740,7 +1738,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1749,7 +1746,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1762,7 +1758,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1772,7 +1767,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1781,7 +1775,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1794,7 +1787,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1804,7 +1796,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1813,7 +1804,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1823,7 +1813,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1833,7 +1822,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1842,7 +1830,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1851,7 +1838,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1861,7 +1847,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1871,7 +1856,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1880,7 +1864,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1889,7 +1872,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1899,7 +1881,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1908,7 +1889,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1918,7 +1898,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1928,7 +1907,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1937,7 +1915,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1946,7 +1923,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1955,7 +1931,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1964,7 +1939,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1973,7 +1947,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1982,7 +1955,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1991,7 +1963,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2000,7 +1971,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2010,7 +1980,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -2168,6 +2137,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_false.txt b/crates/fayalite/tests/sim/expected/queue_3_true_false.txt index be9e7ef..03d3aba 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_true_false.txt @@ -1135,7 +1135,6 @@ Simulation { }, pc: 141, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1259,7 +1258,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1771,7 +1769,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1780,7 +1777,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1793,7 +1789,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1803,7 +1798,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1812,7 +1806,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1825,7 +1818,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1835,7 +1827,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1844,7 +1835,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1854,7 +1844,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1864,7 +1853,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1873,7 +1861,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1882,7 +1869,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1892,7 +1878,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1902,7 +1887,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1911,7 +1895,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1920,7 +1903,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1930,7 +1912,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1939,7 +1920,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1949,7 +1929,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1959,7 +1938,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1968,7 +1946,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1977,7 +1954,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1986,7 +1962,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1995,7 +1970,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2004,7 +1978,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2013,7 +1986,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2022,7 +1994,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2031,7 +2002,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2041,7 +2011,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -2199,6 +2168,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_true.txt b/crates/fayalite/tests/sim/expected/queue_3_true_true.txt index 3e691c1..a663e23 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_true_true.txt @@ -1116,7 +1116,6 @@ Simulation { }, pc: 139, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1238,7 +1237,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1750,7 +1748,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1759,7 +1756,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1772,7 +1768,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1782,7 +1777,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1791,7 +1785,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1804,7 +1797,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1814,7 +1806,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1823,7 +1814,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1833,7 +1823,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1843,7 +1832,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1852,7 +1840,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1861,7 +1848,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1871,7 +1857,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1881,7 +1866,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1890,7 +1874,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1899,7 +1882,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1909,7 +1891,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1918,7 +1899,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1928,7 +1908,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1938,7 +1917,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1947,7 +1925,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1956,7 +1933,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1965,7 +1941,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1974,7 +1949,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1983,7 +1957,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1992,7 +1965,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2001,7 +1973,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2010,7 +1981,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2020,7 +1990,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -2178,6 +2147,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_false.txt b/crates/fayalite/tests/sim/expected/queue_4_false_false.txt index c220ba9..445d9d0 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_false_false.txt @@ -1104,7 +1104,6 @@ Simulation { }, pc: 135, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1228,7 +1227,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1750,7 +1748,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1759,7 +1756,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1772,7 +1768,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1782,7 +1777,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1791,7 +1785,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1804,7 +1797,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1814,7 +1806,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1823,7 +1814,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1833,7 +1823,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1843,7 +1832,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1852,7 +1840,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1861,7 +1848,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1871,7 +1857,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1881,7 +1866,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1890,7 +1874,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1899,7 +1882,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1909,7 +1891,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1918,7 +1899,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1928,7 +1908,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1938,7 +1917,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1947,7 +1925,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1956,7 +1933,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1965,7 +1941,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1974,7 +1949,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1983,7 +1957,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1992,7 +1965,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2001,7 +1973,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2010,7 +1981,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2020,7 +1990,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -2030,7 +1999,6 @@ Simulation { index: StatePartIndex(68), ty: UInt<2>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -2188,6 +2156,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_true.txt b/crates/fayalite/tests/sim/expected/queue_4_false_true.txt index 896783b..5e7ada2 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_false_true.txt @@ -1085,7 +1085,6 @@ Simulation { }, pc: 133, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1207,7 +1206,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1729,7 +1727,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1738,7 +1735,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1751,7 +1747,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1761,7 +1756,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1770,7 +1764,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1783,7 +1776,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1793,7 +1785,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1802,7 +1793,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1812,7 +1802,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1822,7 +1811,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1831,7 +1819,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1840,7 +1827,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1850,7 +1836,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1860,7 +1845,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1869,7 +1853,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1878,7 +1861,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1888,7 +1870,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1897,7 +1878,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1907,7 +1887,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1917,7 +1896,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1926,7 +1904,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1935,7 +1912,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1944,7 +1920,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1953,7 +1928,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1962,7 +1936,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1971,7 +1944,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1980,7 +1952,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1989,7 +1960,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1999,7 +1969,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -2009,7 +1978,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<2>, }, - maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -2167,6 +2135,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_false.txt b/crates/fayalite/tests/sim/expected/queue_4_true_false.txt index 4f500fa..2701c1d 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_true_false.txt @@ -1114,7 +1114,6 @@ Simulation { }, pc: 137, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1238,7 +1237,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1760,7 +1758,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1769,7 +1766,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1782,7 +1778,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1792,7 +1787,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1801,7 +1795,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1814,7 +1807,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1824,7 +1816,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1833,7 +1824,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1843,7 +1833,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, - maybe_changed: true, state: 0x4, last_state: 0x4, }, @@ -1853,7 +1842,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1862,7 +1850,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1871,7 +1858,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1881,7 +1867,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1891,7 +1876,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1900,7 +1884,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1909,7 +1892,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1919,7 +1901,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1928,7 +1909,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1938,7 +1918,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1948,7 +1927,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1957,7 +1935,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1966,7 +1943,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1975,7 +1951,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1984,7 +1959,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1993,7 +1967,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2002,7 +1975,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2011,7 +1983,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2020,7 +1991,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2030,7 +2000,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -2040,7 +2009,6 @@ Simulation { index: StatePartIndex(68), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2198,6 +2166,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_true.txt b/crates/fayalite/tests/sim/expected/queue_4_true_true.txt index bf97cd2..a52069d 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_true_true.txt @@ -1095,7 +1095,6 @@ Simulation { }, pc: 135, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [ MemoryData { @@ -1217,7 +1216,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1739,7 +1737,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1748,7 +1745,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1761,7 +1757,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1771,7 +1766,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1780,7 +1774,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1793,7 +1786,6 @@ Simulation { HdlSome(UInt<8>), }, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1803,7 +1795,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1812,7 +1803,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1822,7 +1812,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, - maybe_changed: true, state: 0x4, last_state: 0x4, }, @@ -1832,7 +1821,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1841,7 +1829,6 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1850,7 +1837,6 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1860,7 +1846,6 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, - maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1870,7 +1855,6 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1879,7 +1863,6 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1888,7 +1871,6 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1898,7 +1880,6 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, - maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1907,7 +1888,6 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1917,7 +1897,6 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1927,7 +1906,6 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1936,7 +1914,6 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1945,7 +1922,6 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1954,7 +1930,6 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1963,7 +1938,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1972,7 +1946,6 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1981,7 +1954,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1990,7 +1962,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1999,7 +1970,6 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2009,7 +1979,6 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, - maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -2019,7 +1988,6 @@ Simulation { index: StatePartIndex(66), ty: UInt<2>, }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2177,6 +2145,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 9641ed5..1fb5fee 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -636,7 +636,6 @@ Simulation { }, pc: 69, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -688,7 +687,7 @@ Simulation { 1, 0, 0, - 0 (modified), + 0, 0, 0, 0, @@ -699,7 +698,7 @@ Simulation { 1, 0, 0, - 0 (modified), + 0, 0, 0, 0, @@ -710,7 +709,7 @@ Simulation { 1, 0, 0, - 0 (modified), + 0, 0, 0, ], @@ -726,7 +725,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1286,7 +1284,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -1296,7 +1293,6 @@ Simulation { index: StatePartIndex(1), ty: UInt<6>, }, - maybe_changed: false, state: 0x00, last_state: 0x00, }, @@ -1305,7 +1301,6 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1314,7 +1309,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1323,7 +1317,6 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1332,7 +1325,6 @@ Simulation { kind: BigBool { index: StatePartIndex(5), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1341,7 +1333,6 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1350,7 +1341,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1359,7 +1349,6 @@ Simulation { kind: BigBool { index: StatePartIndex(24), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1368,7 +1357,6 @@ Simulation { kind: BigClock { index: StatePartIndex(33), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1377,7 +1365,6 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1386,7 +1373,6 @@ Simulation { kind: BigClock { index: StatePartIndex(31), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1395,7 +1381,6 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1404,7 +1389,6 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1413,7 +1397,6 @@ Simulation { kind: BigClock { index: StatePartIndex(44), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1422,7 +1405,6 @@ Simulation { kind: BigBool { index: StatePartIndex(45), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1431,7 +1413,6 @@ Simulation { kind: BigClock { index: StatePartIndex(42), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1440,7 +1421,6 @@ Simulation { kind: BigBool { index: StatePartIndex(43), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1449,7 +1429,6 @@ Simulation { kind: BigBool { index: StatePartIndex(47), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1458,7 +1437,6 @@ Simulation { kind: BigClock { index: StatePartIndex(55), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1467,7 +1445,6 @@ Simulation { kind: BigBool { index: StatePartIndex(56), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1476,7 +1453,6 @@ Simulation { kind: BigClock { index: StatePartIndex(53), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1485,7 +1461,6 @@ Simulation { kind: BigBool { index: StatePartIndex(54), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1792,6 +1767,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 70ebccd..2e1b176 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -254,7 +254,6 @@ Simulation { }, pc: 34, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -294,7 +293,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -460,7 +458,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -469,7 +466,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -478,7 +474,6 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -487,7 +482,6 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -496,7 +490,6 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -505,7 +498,6 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -514,7 +506,6 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -523,7 +514,6 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -547,6 +537,5 @@ Simulation { }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt index b291af7..df9c092 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.txt @@ -60,7 +60,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -69,12 +68,12 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), 0, 0, - 49 (modified), - 50 (modified), - 50 (modified), + 0, + 49, + 50, + 50, ], }, sim_only_slots: StatePart { @@ -88,7 +87,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -358,7 +356,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -367,7 +364,6 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -376,7 +372,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -386,7 +381,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, - maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -396,7 +390,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -406,7 +399,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -523,6 +515,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt index 1b0efd5..917dd5d 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt @@ -60,7 +60,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -69,12 +68,12 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), 0, 0, - 49 (modified), - 50 (modified), - 50 (modified), + 0, + 49, + 50, + 50, ], }, sim_only_slots: StatePart { @@ -88,7 +87,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -358,7 +356,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -367,7 +364,6 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -376,7 +372,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -386,7 +381,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, - maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -396,7 +390,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -406,7 +399,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -523,6 +515,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index 241ef46..827f3cc 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -375,7 +375,6 @@ Simulation { }, pc: 41, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -393,7 +392,7 @@ Simulation { 0, 1, 0, - 1 (modified), + 1, 0, 0, 0, @@ -401,7 +400,7 @@ Simulation { 0, 1, 0, - 1 (modified), + 1, 0, ], }, @@ -476,7 +475,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -1254,7 +1252,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1263,7 +1260,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1273,7 +1269,6 @@ Simulation { index: StatePartIndex(0), ty: SimOnly>>, }, - maybe_changed: true, state: { "extra": "value", }, @@ -1287,7 +1282,6 @@ Simulation { index: StatePartIndex(1), ty: SimOnly>>, }, - maybe_changed: true, state: { "extra": "value", }, @@ -1301,7 +1295,6 @@ Simulation { index: StatePartIndex(2), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1319,7 +1312,6 @@ Simulation { index: StatePartIndex(3), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1336,7 +1328,6 @@ Simulation { kind: BigClock { index: StatePartIndex(4), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1345,7 +1336,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(5), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1355,7 +1345,6 @@ Simulation { index: StatePartIndex(6), ty: SimOnly>>, }, - maybe_changed: true, state: { "extra": "value", }, @@ -1369,7 +1358,6 @@ Simulation { index: StatePartIndex(7), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1386,7 +1374,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1395,7 +1382,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(3), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1405,7 +1391,6 @@ Simulation { index: StatePartIndex(4), ty: SimOnly>>, }, - maybe_changed: true, state: { "extra": "value", }, @@ -1419,7 +1404,6 @@ Simulation { index: StatePartIndex(5), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1437,7 +1421,6 @@ Simulation { index: StatePartIndex(8), ty: SimOnly>>, }, - maybe_changed: true, state: { "extra": "value", }, @@ -1450,7 +1433,6 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1459,7 +1441,6 @@ Simulation { kind: BigClock { index: StatePartIndex(12), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1468,7 +1449,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(13), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1478,7 +1458,6 @@ Simulation { index: StatePartIndex(13), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1496,7 +1475,6 @@ Simulation { index: StatePartIndex(14), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1513,7 +1491,6 @@ Simulation { kind: BigClock { index: StatePartIndex(10), }, - maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1522,7 +1499,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(11), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1532,7 +1508,6 @@ Simulation { index: StatePartIndex(11), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1550,7 +1525,6 @@ Simulation { index: StatePartIndex(12), ty: SimOnly>>, }, - maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1770,6 +1744,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt index 3866eb9..6df4571 100644 --- a/crates/fayalite/tests/sim/expected/sim_read_past.txt +++ b/crates/fayalite/tests/sim/expected/sim_read_past.txt @@ -512,7 +512,6 @@ Simulation { }, pc: 57, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -531,18 +530,18 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), 0, 0, - 49 (modified), - 50 (modified), - 50 (modified), - 0 (modified), - 1 (modified), - 0 (modified), - 49 (modified), - 49 (modified), - 50 (modified), + 0, + 49, + 50, + 50, + 0, + 1, + 0, + 49, + 49, + 50, 1, 0, 0, @@ -592,7 +591,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -9502,7 +9500,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -9511,7 +9508,6 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9520,7 +9516,6 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, - maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -9530,7 +9525,6 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, - maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9540,7 +9534,6 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9550,7 +9543,6 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9559,7 +9551,6 @@ Simulation { kind: BigClock { index: StatePartIndex(6), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9568,7 +9559,6 @@ Simulation { kind: BigClock { index: StatePartIndex(7), }, - maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -9577,7 +9567,6 @@ Simulation { kind: BigClock { index: StatePartIndex(8), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9587,7 +9576,6 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, - maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9597,7 +9585,6 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, - maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9607,7 +9594,6 @@ Simulation { index: StatePartIndex(11), ty: UInt<8>, }, - maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9728,6 +9714,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt index b55fd8c..3fea928 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt @@ -48,7 +48,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -57,8 +56,8 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), - 0 (modified), + 0, + 0, 3, ], }, @@ -73,7 +72,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -312,7 +310,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -321,7 +318,6 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -331,7 +327,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: false, state: 0x03, last_state: 0x03, }, @@ -541,6 +536,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt index 29870da..2283ce5 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt @@ -48,7 +48,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -57,8 +56,8 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), - 0 (modified), + 0, + 0, 3, ], }, @@ -73,7 +72,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -312,7 +310,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -321,7 +318,6 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -331,7 +327,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: false, state: 0x03, last_state: 0x03, }, @@ -541,6 +536,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt index 0885cc9..c77046f 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt @@ -48,7 +48,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -57,7 +56,7 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), + 0, 0, 3, ], @@ -73,7 +72,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -312,7 +310,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -321,7 +318,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -331,7 +327,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: false, state: 0x03, last_state: 0x03, }, @@ -499,6 +494,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt index 068edb2..e1c565a 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt @@ -48,7 +48,6 @@ Simulation { }, pc: 0, memory_write_log: [], - assert_failed_log: [], memories: StatePart { value: [], }, @@ -57,7 +56,7 @@ Simulation { }, big_slots: StatePart { value: [ - 0 (modified), + 0, 0, 3, ], @@ -73,7 +72,6 @@ Simulation { .. }, }, - global_io: {}, main_module: SimulationModuleState { base_targets: [ Instance { @@ -312,7 +310,6 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, - maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -321,7 +318,6 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, - maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -331,7 +327,6 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, - maybe_changed: false, state: 0x03, last_state: 0x03, }, @@ -499,6 +494,5 @@ Simulation { }, ), }, - asserts: [], .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_trace_as_string.txt b/crates/fayalite/tests/sim/expected/sim_trace_as_string.txt deleted file mode 100644 index 4befbfc..0000000 --- a/crates/fayalite/tests/sim/expected/sim_trace_as_string.txt +++ /dev/null @@ -1,2257 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 12, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 31, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.addr", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.addr", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[0]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[1]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", - ty: UInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", - ty: UInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", - ty: Bool, - }, - SlotDebugData { - name: "[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "[0]", - ty: Bool, - }, - SlotDebugData { - name: "[1]", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 1, - debug_data: [ - (), - ], - layout_data: [ - MemoryData { - array_type: Array), FmtError}, .. }, 2>, 4>, - data: [ - // len = 0x4 - [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, - ], - }, - ], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:16:1 - 0: Copy { - dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", ty: Bool }, - src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[0]", ty: Bool }, - }, - 1: Copy { - dest: StatePartIndex(24), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", ty: Bool }, - src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.mask[1]", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:15:1 - 2: Copy { - dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", ty: Bool }, - src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.en", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:14:1 - 3: Copy { - dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - src: StatePartIndex(9), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - }, - 4: Copy { - dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - src: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 5: CastToUInt { - dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(6), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.addr", ty: UInt<8> }, - dest_width: 2, - }, - // at: module-XXXXXXXXXX.rs:13:1 - 6: Copy { - dest: StatePartIndex(18), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", ty: UInt<2> }, - src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 7: Copy { - dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", ty: Clock }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 8: Copy { - dest: StatePartIndex(14), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", ty: Bool }, - src: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.en", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 9: CastToUInt { - dest: StatePartIndex(29), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.addr", ty: UInt<8> }, - dest_width: 2, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 10: Copy { - dest: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", ty: UInt<2> }, - src: StatePartIndex(29), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 11: Copy { - dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", ty: Clock }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::clk", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 12: CastBigToArrayIndex { - dest: StatePartIndex(9), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(18), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.addr", ty: UInt<2> }, - }, - 13: IsNonZeroDestIsSmall { - dest: StatePartIndex(8), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.en", ty: Bool }, - }, - 14: IsNonZeroDestIsSmall { - dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.clk", ty: Clock }, - }, - 15: AndSmall { - dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 16: CastBigToArrayIndex { - dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.addr", ty: UInt<2> }, - }, - 17: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(14), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.en", ty: Bool }, - }, - 18: BranchIfSmallZero { - target: 22, - value: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 19: MemoryReadUInt { - dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - memory: StatePartIndex(0), // (MemoryData { - // array_type: Array), FmtError}, .. }, 2>, 4>, - // data: [ - // // len = 0x4 - // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, - // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, - // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, - // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, - // ], - // }) (), - addr: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - stride: 1026, - start: 0, - width: 513, - }, - 20: MemoryReadUInt { - dest: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - memory: StatePartIndex(0), // (MemoryData { - // array_type: Array), FmtError}, .. }, 2>, 4>, - // data: [ - // // len = 0x4 - // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, - // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, - // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, - // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, - // ], - // }) (), - addr: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - stride: 1026, - start: 513, - width: 513, - }, - 21: Branch { - target: 24, - }, - 22: Const { - dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - value: 0x0, - }, - 23: Const { - dest: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:10:1 - 24: Copy { - dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - }, - 25: Copy { - dest: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - src: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 26: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.clk", ty: Clock }, - }, - 27: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 28: BranchIfSmallZero { - target: 29, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 29: BranchIfSmallZero { - target: 41, - value: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 30: CopySmall { - dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(9), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - }, - 31: CopySmall { - dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(8), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 32: Copy { - dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "[0]", ty: Enum {Text(UInt<512>), FmtError} }, - src: StatePartIndex(21), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", ty: Enum {Text(UInt<512>), FmtError} }, - }, - 33: Copy { - dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "[1]", ty: Enum {Text(UInt<512>), FmtError} }, - src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", ty: Enum {Text(UInt<512>), FmtError} }, - }, - 34: Copy { - dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, - src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[0]", ty: Bool }, - }, - 35: Copy { - dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, - src: StatePartIndex(24), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.mask[1]", ty: Bool }, - }, - 36: BranchIfSmallZero { - target: 41, - value: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 37: BranchIfZero { - target: 39, - value: StatePartIndex(27), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, - }, - 38: MemoryWriteUInt { - value: StatePartIndex(25), // (0x1) SlotDebugData { name: "[0]", ty: Enum {Text(UInt<512>), FmtError} }, - memory: StatePartIndex(0), // (MemoryData { - // array_type: Array), FmtError}, .. }, 2>, 4>, - // data: [ - // // len = 0x4 - // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, - // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, - // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, - // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, - // ], - // }) (), - addr: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - stride: 1026, - start: 0, - width: 513, - }, - 39: BranchIfZero { - target: 41, - value: StatePartIndex(28), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, - }, - 40: MemoryWriteUInt { - value: StatePartIndex(26), // (0x1) SlotDebugData { name: "[1]", ty: Enum {Text(UInt<512>), FmtError} }, - memory: StatePartIndex(0), // (MemoryData { - // array_type: Array), FmtError}, .. }, 2>, 4>, - // data: [ - // // len = 0x4 - // [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, - // [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, - // [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, - // [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, - // ], - // }) (), - addr: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, - stride: 1026, - start: 513, - width: 513, - }, - 41: XorSmallImmediate { - dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 42: XorSmallImmediate { - dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 43: Return, - ], - .. - }, - pc: 43, - memory_write_log: [], - assert_failed_log: [], - memories: StatePart { - value: [ - MemoryData { - array_type: Array), FmtError}, .. }, 2>, 4>, - data: [ - // len = 0x4 - [0x0]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c16db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba60b6dacada, - [0x1]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001, - [0x2]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74c96db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba64b6dacada, - [0x3]: 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000174c56d74cd6db595b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba60b6ba66b6dacada, - ], - }, - ], - }, - small_slots: StatePart { - value: [ - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 1, - 1, - 1, - 1, - 1, - ], - }, - big_slots: StatePart { - value: [ - 1, - 1, - 1, - 0, - 1 (modified), - 1 (modified), - 1, - 1, - 0, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }, - global_io: {}, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.clk, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.clk, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.addr, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.clk, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.data, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.data., - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.data.[0], - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.data.[1], - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.read.en, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.addr, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.clk, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.data, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.data[0], - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.data[0]., - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.data[1], - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.data[1]., - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.en, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.mask, - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.mask[0], - Instance { - name: ::sim_trace_as_string, - instantiated: Module { - name: sim_trace_as_string, - .. - }, - }.write.mask[1], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [], - trace_decls: TraceModule { - name: "sim_trace_as_string", - children: [ - TraceModuleIO { - name: "clk", - child: TraceClock { - location: TraceScalarId(0), - name: "clk", - flow: Source, - }, - ty: Clock, - flow: Source, - }, - TraceModuleIO { - name: "read", - child: TraceBundle { - name: "read", - fields: [ - TraceUInt { - location: TraceScalarId(1), - name: "addr", - ty: UInt<8>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(2), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(3), - name: "clk", - flow: Source, - }, - TraceTraceAsString { - location: TraceScalarId(4), - name: "data", - ty: TraceAsString { - inner_ty: Array), FmtError}, 2>, - .. - }, - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<8>, - /* offset = 8 */ - en: Bool, - /* offset = 9 */ - clk: Clock, - #[hdl(flip)] /* offset = 10 */ - data: TraceAsString { - inner_ty: Array), FmtError}, 2>, - .. - }, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<8>, - /* offset = 8 */ - en: Bool, - /* offset = 9 */ - clk: Clock, - #[hdl(flip)] /* offset = 10 */ - data: TraceAsString { - inner_ty: Array), FmtError}, 2>, - .. - }, - }, - flow: Source, - }, - TraceModuleIO { - name: "write", - child: TraceBundle { - name: "write", - fields: [ - TraceUInt { - location: TraceScalarId(5), - name: "addr", - ty: UInt<8>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(6), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(7), - name: "clk", - flow: Source, - }, - TraceArray { - name: "data", - elements: [ - TraceTraceAsString { - location: TraceScalarId(8), - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Source, - }, - TraceTraceAsString { - location: TraceScalarId(9), - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Source, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Source, - }, - TraceArray { - name: "mask", - elements: [ - TraceBool { - location: TraceScalarId(10), - name: "[0]", - flow: Source, - }, - TraceBool { - location: TraceScalarId(11), - name: "[1]", - flow: Source, - }, - ], - ty: Array, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<8>, - /* offset = 8 */ - en: Bool, - /* offset = 9 */ - clk: Clock, - /* offset = 10 */ - data: Array), FmtError}, .. }, 2>, - /* offset = 1036 */ - mask: Array, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<8>, - /* offset = 8 */ - en: Bool, - /* offset = 9 */ - clk: Clock, - /* offset = 10 */ - data: Array), FmtError}, .. }, 2>, - /* offset = 1036 */ - mask: Array, - }, - flow: Source, - }, - TraceMem { - id: TraceMemoryId(0), - name: "mem", - stride: 1026, - element_type: TraceArray { - name: "mem", - elements: [ - TraceTraceAsString { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 4, - stride: 1026, - start: 0, - len: 513, - }, - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Duplex, - }, - TraceTraceAsString { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 4, - stride: 1026, - start: 513, - len: 513, - }, - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Duplex, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(12), - name: "addr", - ty: UInt<2>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(13), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(14), - name: "clk", - flow: Sink, - }, - TraceArray { - name: "data", - elements: [ - TraceTraceAsString { - location: TraceScalarId(15), - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Source, - }, - TraceTraceAsString { - location: TraceScalarId(16), - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Source, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - #[hdl(flip)] /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - #[hdl(flip)] /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(17), - name: "addr", - ty: UInt<2>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(18), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(19), - name: "clk", - flow: Sink, - }, - TraceArray { - name: "data", - elements: [ - TraceTraceAsString { - location: TraceScalarId(20), - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Sink, - }, - TraceTraceAsString { - location: TraceScalarId(21), - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Sink, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Sink, - }, - TraceArray { - name: "mask", - elements: [ - TraceBool { - location: TraceScalarId(22), - name: "[0]", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(23), - name: "[1]", - flow: Sink, - }, - ], - ty: Array, - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - /* offset = 1030 */ - mask: Array, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - /* offset = 1030 */ - mask: Array, - }, - }, - ], - array_type: Array), FmtError}, .. }, 2>, 4>, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigUInt { - index: StatePartIndex(1), - ty: UInt<8>, - }, - maybe_changed: false, - state: 0x01, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigBool { - index: StatePartIndex(2), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigClock { - index: StatePartIndex(3), - }, - maybe_changed: false, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(4), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Array), FmtError}, 2>, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Array), FmtError}, 2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Array { - elements_non_empty: [ - CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::read.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - ], - }, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 2 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001_u1026, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0x174C56D74C56DB595B400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000BA60B6BA62B6DACADA_u1026, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigUInt { - index: StatePartIndex(6), - ty: UInt<8>, - }, - maybe_changed: false, - state: 0x01, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigBool { - index: StatePartIndex(7), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigClock { - index: StatePartIndex(8), - }, - maybe_changed: false, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(8), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 9, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(9), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::write.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(10), - kind: BigBool { - index: StatePartIndex(11), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(11), - kind: BigBool { - index: StatePartIndex(12), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(12), - kind: BigUInt { - index: StatePartIndex(13), - ty: UInt<2>, - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(13), - kind: BigBool { - index: StatePartIndex(14), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(14), - kind: BigClock { - index: StatePartIndex(15), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(15), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 16, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0xBA60B6BA62B6DACADA_u513, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(16), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::r0.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 17, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0xBA62B6BA62B6DACADA_u513, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(17), - kind: BigUInt { - index: StatePartIndex(18), - ty: UInt<2>, - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(18), - kind: BigBool { - index: StatePartIndex(19), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(19), - kind: BigClock { - index: StatePartIndex(20), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(20), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[0]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 5, len: 0 }, - big_slots: StatePartIndexRange { start: 21, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(21), - kind: TraceAsString { - layout: CompiledTypeLayout { - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Transparent { - inner: CompiledTypeLayout { - ty: Enum { - Text(UInt<512>), - FmtError, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_trace_as_string: sim_trace_as_string).sim_trace_as_string::mem::w1.data[1]", - ty: Enum { - Text(UInt<512>), - FmtError, - }, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 5, len: 0 }, - big_slots: StatePartIndexRange { start: 22, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - }, - maybe_changed: true, - state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - last_state: OpaqueSimValue { - bits: 0x1_u513, - sim_only_values: [], - }, - }, - SimTrace { - id: TraceScalarId(22), - kind: BigBool { - index: StatePartIndex(23), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(23), - kind: BigBool { - index: StatePartIndex(24), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x1, - }, - ], - trace_memories: { - StatePartIndex(0): TraceMem { - id: TraceMemoryId(0), - name: "mem", - stride: 1026, - element_type: TraceArray { - name: "mem", - elements: [ - TraceTraceAsString { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 4, - stride: 1026, - start: 0, - len: 513, - }, - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Duplex, - }, - TraceTraceAsString { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 4, - stride: 1026, - start: 513, - len: 513, - }, - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Duplex, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(12), - name: "addr", - ty: UInt<2>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(13), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(14), - name: "clk", - flow: Sink, - }, - TraceArray { - name: "data", - elements: [ - TraceTraceAsString { - location: TraceScalarId(15), - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Source, - }, - TraceTraceAsString { - location: TraceScalarId(16), - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Source, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - #[hdl(flip)] /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - #[hdl(flip)] /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(17), - name: "addr", - ty: UInt<2>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(18), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(19), - name: "clk", - flow: Sink, - }, - TraceArray { - name: "data", - elements: [ - TraceTraceAsString { - location: TraceScalarId(20), - name: "[0]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Sink, - }, - TraceTraceAsString { - location: TraceScalarId(21), - name: "[1]", - ty: TraceAsString { - inner_ty: Enum { - Text(UInt<512>), - FmtError, - }, - .. - }, - flow: Sink, - }, - ], - ty: Array), FmtError}, .. }, 2>, - flow: Sink, - }, - TraceArray { - name: "mask", - elements: [ - TraceBool { - location: TraceScalarId(22), - name: "[0]", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(23), - name: "[1]", - flow: Sink, - }, - ], - ty: Array, - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - /* offset = 1030 */ - mask: Array, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<2>, - /* offset = 2 */ - en: Bool, - /* offset = 3 */ - clk: Clock, - /* offset = 4 */ - data: Array), FmtError}, .. }, 2>, - /* offset = 1030 */ - mask: Array, - }, - }, - ], - array_type: Array), FmtError}, .. }, 2>, 4>, - }, - }, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [ - StatePartIndex(1), - StatePartIndex(6), - ], - event_queue: EventQueue(EventQueueData { - instant: 7 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [], - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd b/crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd deleted file mode 100644 index 3338905..0000000 --- a/crates/fayalite/tests/sim/expected/sim_trace_as_string.vcd +++ /dev/null @@ -1,221 +0,0 @@ -$timescale 1 ps $end -$scope module sim_trace_as_string $end -$var wire 1 J(7*b clk $end -$scope struct read $end -$var wire 8 @t0}\ addr $end -$var wire 1 78"T5 en $end -$var wire 1 G7v@m clk $end -$var string 1 F&^FN data $end -$upscope $end -$scope struct write $end -$var wire 8 "fUdW addr $end -$var wire 1 r1OK) en $end -$var wire 1 ,ADvU clk $end -$scope struct data $end -$var string 1 pD.mP \[0] $end -$var string 1 !V!em \[1] $end -$upscope $end -$scope struct mask $end -$var wire 1 l8dgD \[0] $end -$var wire 1 1/sDs \[1] $end -$upscope $end -$upscope $end -$scope struct mem $end -$scope struct contents $end -$scope struct \[0] $end -$scope struct mem $end -$var string 1 sz>#| \[0] $end -$var string 1 G._83 \[1] $end -$upscope $end -$upscope $end -$scope struct \[1] $end -$scope struct mem $end -$var string 1 2r3#W \[0] $end -$var string 1 AbGF% \[1] $end -$upscope $end -$upscope $end -$scope struct \[2] $end -$scope struct mem $end -$var string 1 .^<$p \[0] $end -$var string 1 ?s@Dc \[1] $end -$upscope $end -$upscope $end -$scope struct \[3] $end -$scope struct mem $end -$var string 1 {*||o \[0] $end -$var string 1 Bg,vB \[1] $end -$upscope $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 2 .0()- addr $end -$var wire 1 GEbRA en $end -$var wire 1 ;`9BK clk $end -$scope struct data $end -$var string 1 _Xe"P \[0] $end -$var string 1 jXrsx \[1] $end -$upscope $end -$upscope $end -$scope struct w1 $end -$var wire 2 '8u?z addr $end -$var wire 1 ~o=`& en $end -$var wire 1 *q>M1 clk $end -$scope struct data $end -$var string 1 N\zBe \[0] $end -$var string 1 c3h8{ \[1] $end -$upscope $end -$scope struct mask $end -$var wire 1 .SYGD \[0] $end -$var wire 1 />wYd \[1] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -s sz>#| -s G._83 -s 2r3#W -s AbGF% -s .^<$p -s ?s@Dc -s {*||o -s Bg,vB -0J(7*b -b0 @t0}\ -078"T5 -0G7v@m -s[,\x20] F&^FN -b0 "fUdW -0r1OK) -0,ADvU -s pD.mP -s !V!em -0l8dgD -01/sDs -b0 .0()- -0GEbRA -0;`9BK -s _Xe"P -s jXrsx -b0 '8u?z -0~o=`& -0*q>M1 -s N\zBe -s c3h8{ -0.SYGD -0/>wYd -$end -#500000 -1J(7*b -1;`9BK -1*q>M1 -#1000000 -0J(7*b -1r1OK) -smem[0][0] pD.mP -smem[0][1] !V!em -1l8dgD -11/sDs -0;`9BK -1~o=`& -0*q>M1 -smem[0][0] N\zBe -smem[0][1] c3h8{ -1.SYGD -1/>wYd -#1500000 -smem[0][0] sz>#| -smem[0][1] G._83 -1J(7*b -1;`9BK -1*q>M1 -#2000000 -0J(7*b -b1 "fUdW -smem[1][0] pD.mP -smem[1][1] !V!em -0;`9BK -b1 '8u?z -0*q>M1 -smem[1][0] N\zBe -smem[1][1] c3h8{ -#2500000 -smem[1][0] 2r3#W -smem[1][1] AbGF% -1J(7*b -1;`9BK -1*q>M1 -#3000000 -0J(7*b -b10 "fUdW -smem[2][0] pD.mP -smem[2][1] !V!em -0;`9BK -b10 '8u?z -0*q>M1 -smem[2][0] N\zBe -smem[2][1] c3h8{ -#3500000 -smem[2][0] .^<$p -smem[2][1] ?s@Dc -1J(7*b -1;`9BK -1*q>M1 -#4000000 -0J(7*b -b11 "fUdW -smem[3][0] pD.mP -smem[3][1] !V!em -0;`9BK -b11 '8u?z -0*q>M1 -smem[3][0] N\zBe -smem[3][1] c3h8{ -#4500000 -smem[3][0] {*||o -smem[3][1] Bg,vB -1J(7*b -1;`9BK -1*q>M1 -#5000000 -0J(7*b -b1 @t0}\ -178"T5 -s[mem[1][0],\x20mem[1][1]] F&^FN -b0 "fUdW -0r1OK) -s pD.mP -s !V!em -b1 .0()- -1GEbRA -0;`9BK -smem[1][0] _Xe"P -smem[1][1] jXrsx -b0 '8u?z -0~o=`& -0*q>M1 -s N\zBe -s c3h8{ -#5500000 -1J(7*b -1;`9BK -1*q>M1 -#6000000 -0J(7*b -b1 "fUdW -1r1OK) -0;`9BK -b1 '8u?z -1~o=`& -0*q>M1 -#6500000 -s 2r3#W -s AbGF% -1J(7*b -s F&^FN -1;`9BK -s _Xe"P -s jXrsx -1*q>M1 -#7000000 diff --git a/crates/fayalite/tests/sim/expected/test_formal_counter.txt b/crates/fayalite/tests/sim/expected/test_formal_counter.txt deleted file mode 100644 index fc90a1a..0000000 --- a/crates/fayalite/tests/sim/expected/test_formal_counter.txt +++ /dev/null @@ -1,855 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 5, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 26, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::enable_assert", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::any_seq_out", - ty: UInt<16>, - }, - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.rst", - ty: SyncReset, - }, - SlotDebugData { - name: ".clk", - ty: Clock, - }, - SlotDebugData { - name: ".rst", - ty: SyncReset, - }, - SlotDebugData { - name: "<>::formal_global_clock", - ty: Clock, - }, - SlotDebugData { - name: "<>::formal_reset", - ty: SyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<9>, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "<>::any_seq", - ty: UInt<16>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:15:1 - 0: Copy { - dest: StatePartIndex(2), // (0x4d2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::any_seq_out", ty: UInt<16> }, - src: StatePartIndex(25), // (0x4d2) SlotDebugData { name: "<>::any_seq", ty: UInt<16> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 1: Copy { - dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(8), // (0x0) SlotDebugData { name: "<>::formal_reset", ty: SyncReset }, - }, - 2: NotU { - dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Bool }, - width: 1, - }, - 3: Const { - dest: StatePartIndex(18), // (0x1) SlotDebugData { name: "", ty: Bool }, - value: 0x1, - }, - 4: And { - dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(18), // (0x1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(20), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 5: NotU { - dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, - width: 1, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 6: Copy { - dest: StatePartIndex(24), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(18), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 7: Copy { - dest: StatePartIndex(0), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count", ty: UInt<8> }, - src: StatePartIndex(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { - dest: StatePartIndex(14), // (0xa) SlotDebugData { name: "", ty: UInt<8> }, - value: 0xa, - }, - 9: CmpLe { - dest: StatePartIndex(17), // (0x1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> }, - rhs: StatePartIndex(14), // (0xa) SlotDebugData { name: "", ty: UInt<8> }, - }, - 10: Or { - dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(17), // (0x1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:11:1 - 11: BranchIfZero { - target: 13, - value: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::enable_assert", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 12: Copy { - dest: StatePartIndex(24), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 13: IsNonZeroDestIsSmall { - dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(24), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 14: Const { - dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - value: 0x1, - }, - 15: Add { - dest: StatePartIndex(13), // (0x3) SlotDebugData { name: "", ty: UInt<9> }, - lhs: StatePartIndex(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> }, - rhs: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, - }, - 16: CmpLt { - dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(13), // (0x3) SlotDebugData { name: "", ty: UInt<9> }, - rhs: StatePartIndex(14), // (0xa) SlotDebugData { name: "", ty: UInt<8> }, - }, - 17: CastToUInt { - dest: StatePartIndex(16), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - src: StatePartIndex(13), // (0x3) SlotDebugData { name: "", ty: UInt<9> }, - dest_width: 8, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 18: Copy { - dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> }, - src: StatePartIndex(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 19: BranchIfZero { - target: 21, - value: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 20: Copy { - dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> }, - src: StatePartIndex(16), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 21: Const { - dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 22: BranchIfNonZero { - target: 24, - value: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 23: Copy { - dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> }, - src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 24: Copy { - dest: StatePartIndex(5), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, - src: StatePartIndex(7), // (0x1) SlotDebugData { name: "<>::formal_global_clock", ty: Clock }, - }, - 25: Copy { - dest: StatePartIndex(6), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, - src: StatePartIndex(8), // (0x0) SlotDebugData { name: "<>::formal_reset", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 26: Copy { - dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.clk", ty: Clock }, - src: StatePartIndex(5), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, - }, - 27: Copy { - dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.rst", ty: SyncReset }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 28: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.clk", ty: Clock }, - }, - 29: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 30: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::cd.rst", ty: SyncReset }, - }, - 31: BranchIfSmallZero { - target: 36, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 32: BranchIfSmallNonZero { - target: 35, - value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 33: Copy { - dest: StatePartIndex(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> }, - src: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg$next", ty: UInt<8> }, - }, - 34: Branch { - target: 36, - }, - 35: Copy { - dest: StatePartIndex(9), // (0x2) SlotDebugData { name: "InstantiatedModule(formal_counter: formal_counter).formal_counter::count_reg", ty: UInt<8> }, - src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:12:1 - 36: Assert { - clk_triggered: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - pred: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - assert_index: 0, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 37: XorSmallImmediate { - dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 38: Return, - ], - .. - }, - pc: 38, - memory_write_log: [], - assert_failed_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [ - 0, - 0, - 1, - 0, - 1, - ], - }, - big_slots: StatePart { - value: [ - 2, - 1, - 1234, - 1, - 0, - 1, - 0, - 1, - 0, - 2, - 3, - 0, - 1, - 3, - 10, - 1, - 3, - 1, - 1, - 0, - 1, - 1, - 0, - 1, - 1, - 1234, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }, - global_io: { - SimIoForGlobal( - formal_global_clock, - ): CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "<>::formal_global_clock", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 7, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - SimIoForGlobal( - formal_reset, - ): CompiledValue { - layout: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "<>::formal_reset", - ty: SyncReset, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 8, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - SimIoForGlobal( - any_seq( - UInt<16>, - ), - ): CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<16>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "<>::any_seq", - ty: UInt<16>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 5, len: 0 }, - big_slots: StatePartIndexRange { start: 25, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - }, - main_module: SimulationModuleState { - base_targets: [ - SimIoForGlobal( - formal_global_clock, - ), - SimIoForGlobal( - formal_reset, - ), - SimIoForGlobal( - any_seq( - UInt<16>, - ), - ), - Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }.count, - Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }.enable_assert, - Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }.any_seq_out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }.any_seq_out, - Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }.count, - Instance { - name: ::formal_counter, - instantiated: Module { - name: formal_counter, - .. - }, - }.enable_assert, - SimIoForGlobal( - any_seq( - UInt<16>, - ), - ), - SimIoForGlobal( - formal_global_clock, - ), - SimIoForGlobal( - formal_reset, - ), - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [], - trace_decls: TraceModule { - name: "formal_counter", - children: [ - TraceFormalInput { - name: "formal_global_clock", - child: TraceClock { - location: TraceScalarId(5), - name: "formal_global_clock", - flow: Source, - }, - formal_input: formal_global_clock, - }, - TraceFormalInput { - name: "formal_reset", - child: TraceSyncReset { - location: TraceScalarId(6), - name: "formal_reset", - flow: Source, - }, - formal_input: formal_reset, - }, - TraceFormalInput { - name: "any_seq", - child: TraceUInt { - location: TraceScalarId(8), - name: "any_seq", - ty: UInt<16>, - flow: Source, - }, - formal_input: any_seq( - UInt<16>, - ), - }, - TraceModuleIO { - name: "count", - child: TraceUInt { - location: TraceScalarId(0), - name: "count", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - TraceModuleIO { - name: "enable_assert", - child: TraceBool { - location: TraceScalarId(1), - name: "enable_assert", - flow: Source, - }, - ty: Bool, - flow: Source, - }, - TraceModuleIO { - name: "any_seq_out", - child: TraceUInt { - location: TraceScalarId(2), - name: "any_seq_out", - ty: UInt<16>, - flow: Sink, - }, - ty: UInt<16>, - flow: Sink, - }, - TraceWire { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - location: TraceScalarId(3), - name: "clk", - flow: Duplex, - }, - TraceSyncReset { - location: TraceScalarId(4), - name: "rst", - flow: Duplex, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Duplex, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - }, - TraceReg { - name: "count_reg", - child: TraceUInt { - location: TraceScalarId(7), - name: "count_reg", - ty: UInt<8>, - flow: Duplex, - }, - ty: UInt<8>, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigUInt { - index: StatePartIndex(0), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0x02, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigBool { - index: StatePartIndex(1), - }, - maybe_changed: false, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<16>, - }, - maybe_changed: true, - state: 0x04d2, - last_state: 0x04d2, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigClock { - index: StatePartIndex(3), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigSyncReset { - index: StatePartIndex(4), - }, - maybe_changed: true, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigClock { - index: StatePartIndex(7), - }, - maybe_changed: true, - state: 0x1, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigSyncReset { - index: StatePartIndex(8), - }, - maybe_changed: true, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigUInt { - index: StatePartIndex(9), - ty: UInt<8>, - }, - maybe_changed: true, - state: 0x02, - last_state: 0x01, - }, - SimTrace { - id: TraceScalarId(8), - kind: BigUInt { - index: StatePartIndex(25), - ty: UInt<16>, - }, - maybe_changed: true, - state: 0x04d2, - last_state: 0x04d2, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [ - StatePartIndex(1), - ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, - asserts: [ - CompiledAssert { - instantiated_module: InstantiatedModule(formal_counter: formal_counter), - stmt_formal: assert { - clk: Wire(formal_counter::cd: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }).clk, - pred: CmpLeU { - lhs: Reg { - name: formal_counter::count_reg, - ty: UInt<8>, - clock_domain: Wire(formal_counter::cd: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }), - init: Some( - 0x0_u8, - ), - .. - }, - rhs: 0xA_u8, - literal_bits: Err( - NotALiteralExpr, - ), - }, - en: BitAndB { - lhs: true, - rhs: NotB { - arg: CastSyncResetToBool { - arg: formal_reset, - literal_bits: Err( - NotALiteralExpr, - ), - }, - literal_bits: Err( - NotALiteralExpr, - ), - }, - literal_bits: Err( - NotALiteralExpr, - ), - }, - text: "", - .. - }, - }, - ], - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/test_formal_counter.vcd b/crates/fayalite/tests/sim/expected/test_formal_counter.vcd deleted file mode 100644 index 1ba1b18..0000000 --- a/crates/fayalite/tests/sim/expected/test_formal_counter.vcd +++ /dev/null @@ -1,290 +0,0 @@ -$timescale 1 ps $end -$scope module formal_counter $end -$var wire 1 ekAK2 formal_global_clock $end -$var wire 1 qTY9h formal_reset $end -$var wire 16 /roOY any_seq $end -$var wire 8 }eN0d count $end -$var wire 1 2f=;S enable_assert $end -$var wire 16 L-uG? any_seq_out $end -$scope struct cd $end -$var wire 1 -e"5` clk $end -$var wire 1 IC0;$ rst $end -$upscope $end -$var reg 8 ^:T_4 count_reg $end -$upscope $end -$enddefinitions $end -$dumpvars -b0 }eN0d -12f=;S -b0 L-uG? -0-e"5` -1IC0;$ -0ekAK2 -1qTY9h -b0 ^:T_4 -b0 /roOY -$end -#1000000 -b10011010010 L-uG? -1-e"5` -1ekAK2 -b10011010010 /roOY -0IC0;$ -0qTY9h -#2000000 -0-e"5` -0ekAK2 -#3000000 -b1 }eN0d -1-e"5` -1ekAK2 -b1 ^:T_4 -#4000000 -0-e"5` -0ekAK2 -#5000000 -b10 }eN0d -1-e"5` -1ekAK2 -b10 ^:T_4 -#6000000 -0-e"5` -0ekAK2 -#7000000 -b11 }eN0d -1-e"5` -1ekAK2 -b11 ^:T_4 -#8000000 -0-e"5` -0ekAK2 -#9000000 -b100 }eN0d -1-e"5` -1ekAK2 -b100 ^:T_4 -#10000000 -0-e"5` -0ekAK2 -#11000000 -b101 }eN0d -1-e"5` -1ekAK2 -b101 ^:T_4 -#12000000 -0-e"5` -0ekAK2 -#13000000 -b110 }eN0d -1-e"5` -1ekAK2 -b110 ^:T_4 -#14000000 -0-e"5` -0ekAK2 -#15000000 -b111 }eN0d -1-e"5` -1ekAK2 -b111 ^:T_4 -#16000000 -0-e"5` -0ekAK2 -#17000000 -b1000 }eN0d -1-e"5` -1ekAK2 -b1000 ^:T_4 -#18000000 -0-e"5` -0ekAK2 -#19000000 -b1001 }eN0d -1-e"5` -1ekAK2 -b1001 ^:T_4 -#20000000 -0-e"5` -0ekAK2 -#21000000 -b0 }eN0d -1-e"5` -1ekAK2 -b0 ^:T_4 -#22000000 -0-e"5` -0ekAK2 -#23000000 -b1 }eN0d -1-e"5` -1ekAK2 -b1 ^:T_4 -#24000000 -0-e"5` -0ekAK2 -#25000000 -b10 }eN0d -1-e"5` -1ekAK2 -b10 ^:T_4 -#26000000 -0-e"5` -0ekAK2 -#27000000 -b11 }eN0d -1-e"5` -1ekAK2 -b11 ^:T_4 -#28000000 -0-e"5` -0ekAK2 -#29000000 -b100 }eN0d -1-e"5` -1ekAK2 -b100 ^:T_4 -#30000000 -0-e"5` -0ekAK2 -#31000000 -b101 }eN0d -1-e"5` -1ekAK2 -b101 ^:T_4 -#32000000 -0-e"5` -0ekAK2 -#33000000 -b110 }eN0d -1-e"5` -1ekAK2 -b110 ^:T_4 -#34000000 -0-e"5` -0ekAK2 -#35000000 -b111 }eN0d -1-e"5` -1ekAK2 -b111 ^:T_4 -#36000000 -0-e"5` -0ekAK2 -#37000000 -b1000 }eN0d -1-e"5` -1ekAK2 -b1000 ^:T_4 -#38000000 -0-e"5` -0ekAK2 -#39000000 -b1001 }eN0d -1-e"5` -1ekAK2 -b1001 ^:T_4 -#40000000 -0-e"5` -0ekAK2 -#41000000 -b0 }eN0d -1-e"5` -1ekAK2 -b0 ^:T_4 -#42000000 -0-e"5` -0ekAK2 -#43000000 -b1 }eN0d -1-e"5` -1ekAK2 -b1 ^:T_4 -#44000000 -0-e"5` -0ekAK2 -#45000000 -b10 }eN0d -1-e"5` -1ekAK2 -b10 ^:T_4 -#46000000 -0-e"5` -0ekAK2 -#47000000 -b11 }eN0d -1-e"5` -1ekAK2 -b11 ^:T_4 -#48000000 -0-e"5` -0ekAK2 -#49000000 -b100 }eN0d -1-e"5` -1ekAK2 -b100 ^:T_4 -#50000000 -0-e"5` -0ekAK2 -#51000000 -b101 }eN0d -1-e"5` -1ekAK2 -b101 ^:T_4 -#52000000 -0-e"5` -0ekAK2 -#53000000 -b110 }eN0d -1-e"5` -1ekAK2 -b110 ^:T_4 -#54000000 -0-e"5` -0ekAK2 -#55000000 -b111 }eN0d -1-e"5` -1ekAK2 -b111 ^:T_4 -#56000000 -0-e"5` -0ekAK2 -#57000000 -b1000 }eN0d -1-e"5` -1ekAK2 -b1000 ^:T_4 -#58000000 -0-e"5` -0ekAK2 -#59000000 -b1001 }eN0d -1-e"5` -1ekAK2 -b1001 ^:T_4 -#60000000 -0-e"5` -0ekAK2 -#61000000 -b0 }eN0d -1-e"5` -1ekAK2 -b0 ^:T_4 -#62000000 -0-e"5` -0ekAK2 -#63000000 -b1 }eN0d -1-e"5` -1ekAK2 -b1 ^:T_4 -#64000000 -0-e"5` -0ekAK2 -#65000000 -b10 }eN0d -1-e"5` -1ekAK2 -b10 ^:T_4 -#66000000 diff --git a/crates/fayalite/tests/sim/expected/test_formal_counter_assert.vcd b/crates/fayalite/tests/sim/expected/test_formal_counter_assert.vcd deleted file mode 100644 index c9b1655..0000000 --- a/crates/fayalite/tests/sim/expected/test_formal_counter_assert.vcd +++ /dev/null @@ -1,194 +0,0 @@ -$timescale 1 ps $end -$scope module formal_counter $end -$var wire 1 ekAK2 formal_global_clock $end -$var wire 1 qTY9h formal_reset $end -$var wire 16 /roOY any_seq $end -$var wire 8 }eN0d count $end -$var wire 1 2f=;S enable_assert $end -$var wire 16 L-uG? any_seq_out $end -$scope struct cd $end -$var wire 1 -e"5` clk $end -$var wire 1 IC0;$ rst $end -$upscope $end -$var reg 8 ^:T_4 count_reg $end -$upscope $end -$enddefinitions $end -$dumpvars -b0 }eN0d -02f=;S -b0 L-uG? -0-e"5` -1IC0;$ -0ekAK2 -1qTY9h -b0 ^:T_4 -b0 /roOY -$end -#500000 -b10011010010 L-uG? -1-e"5` -1ekAK2 -b10011010010 /roOY -0IC0;$ -0qTY9h -#1000000 -0-e"5` -0ekAK2 -#1500000 -b1 }eN0d -1-e"5` -1ekAK2 -b1 ^:T_4 -#2000000 -0-e"5` -0ekAK2 -#2500000 -b10 }eN0d -1-e"5` -1ekAK2 -b10 ^:T_4 -#3000000 -0-e"5` -0ekAK2 -#3500000 -b11 }eN0d -1-e"5` -1ekAK2 -b11 ^:T_4 -#4000000 -0-e"5` -0ekAK2 -#4500000 -b100 }eN0d -1-e"5` -1ekAK2 -b100 ^:T_4 -#5000000 -0-e"5` -0ekAK2 -#5500000 -b101 }eN0d -1-e"5` -1ekAK2 -b101 ^:T_4 -#6000000 -0-e"5` -0ekAK2 -#6500000 -b110 }eN0d -1-e"5` -1ekAK2 -b110 ^:T_4 -#7000000 -0-e"5` -0ekAK2 -#7500000 -b111 }eN0d -1-e"5` -1ekAK2 -b111 ^:T_4 -#8000000 -0-e"5` -0ekAK2 -#8500000 -b1000 }eN0d -1-e"5` -1ekAK2 -b1000 ^:T_4 -#9000000 -0-e"5` -0ekAK2 -#9500000 -b1001 }eN0d -1-e"5` -1ekAK2 -b1001 ^:T_4 -#10000000 -0-e"5` -0ekAK2 -#10500000 -b0 }eN0d -1-e"5` -1ekAK2 -b0 ^:T_4 -#11000000 -0-e"5` -0ekAK2 -#11500000 -b1 }eN0d -1-e"5` -1ekAK2 -b1 ^:T_4 -#12000000 -0-e"5` -0ekAK2 -#12500000 -b10 }eN0d -1-e"5` -1ekAK2 -b10 ^:T_4 -#13000000 -0-e"5` -0ekAK2 -#13500000 -b11 }eN0d -1-e"5` -1ekAK2 -b11 ^:T_4 -#14000000 -0-e"5` -0ekAK2 -#14500000 -b100 }eN0d -1-e"5` -1ekAK2 -b100 ^:T_4 -#15000000 -0-e"5` -0ekAK2 -#15500000 -b101 }eN0d -1-e"5` -1ekAK2 -b101 ^:T_4 -#16000000 -0-e"5` -0ekAK2 -#16500000 -b110 }eN0d -1-e"5` -1ekAK2 -b110 ^:T_4 -#17000000 -12f=;S -0-e"5` -0ekAK2 -#17500000 -b111 }eN0d -1-e"5` -1ekAK2 -b111 ^:T_4 -#18000000 -0-e"5` -0ekAK2 -#18500000 -b1000 }eN0d -1-e"5` -1ekAK2 -b1000 ^:T_4 -#19000000 -0-e"5` -0ekAK2 -#19500000 -b1001 }eN0d -1-e"5` -1ekAK2 -b1001 ^:T_4 -#20000000 -0-e"5` -0ekAK2 -#20500000 -b0 }eN0d -1-e"5` -1ekAK2 -b0 ^:T_4 diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr index 8eff725..6c78637 100644 --- a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr +++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr @@ -55,7 +55,7 @@ error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'sta note: required because it appears within the type `DynSimOnlyValue` --> src/sim/value/sim_only_value_unsafe.rs | - 281 | pub struct DynSimOnlyValue(Rc); + 271 | pub struct DynSimOnlyValue(Rc); | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` --> $RUST/core/src/marker.rs @@ -75,7 +75,7 @@ note: required because it appears within the type `Vec` note: required because it appears within the type `OpaqueSimValue` --> src/ty.rs | - 896 | pub struct OpaqueSimValue { + 734 | pub struct OpaqueSimValue { | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` --> src/sim/value.rs @@ -194,7 +194,7 @@ error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'sta note: required because it appears within the type `DynSimOnlyValue` --> src/sim/value/sim_only_value_unsafe.rs | - 281 | pub struct DynSimOnlyValue(Rc); + 271 | pub struct DynSimOnlyValue(Rc); | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` --> $RUST/core/src/marker.rs @@ -214,7 +214,7 @@ note: required because it appears within the type `Vec` note: required because it appears within the type `OpaqueSimValue` --> src/ty.rs | - 896 | pub struct OpaqueSimValue { + 734 | pub struct OpaqueSimValue { | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` --> src/sim/value.rs @@ -306,7 +306,7 @@ error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'sta note: required because it appears within the type `DynSimOnlyValue` --> src/sim/value/sim_only_value_unsafe.rs | - 281 | pub struct DynSimOnlyValue(Rc); + 271 | pub struct DynSimOnlyValue(Rc); | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` --> $RUST/core/src/marker.rs @@ -326,7 +326,7 @@ note: required because it appears within the type `Vec` note: required because it appears within the type `OpaqueSimValue` --> src/ty.rs | - 896 | pub struct OpaqueSimValue { + 734 | pub struct OpaqueSimValue { | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` --> src/sim/value.rs diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json index 1267aa7..a74cef9 100644 --- a/crates/fayalite/visit_types.json +++ b/crates/fayalite/visit_types.json @@ -51,8 +51,7 @@ "Reset": "Visible", "Clock": "Visible", "PhantomConst": "Visible", - "DynSimOnly": "Visible", - "TraceAsString": "Visible" + "DynSimOnly": "Visible" } }, "Bundle": { @@ -151,11 +150,6 @@ "$kind": "Opaque" } }, - "NameIdOrGlobal": { - "data": { - "$kind": "ManualImpl" - } - }, "ScopedNameId": { "data": { "$kind": "Struct", @@ -1027,34 +1021,6 @@ "fold_where": "T: Fold", "visit_where": "T: Visit" }, - "ops::ToTraceAsString": { - "data": { - "$kind": "Struct", - "$constructor": "ops::ToTraceAsString::new", - "inner()": "Visible", - "ty()": "Visible" - }, - "generics": "", - "fold_where": "T: Fold", - "visit_where": "T: Visit" - }, - "ops::TraceAsStringAsInner": { - "data": { - "$kind": "Struct", - "$constructor": "ops::TraceAsStringAsInner::new", - "arg_typed()": "Visible" - }, - "generics": "", - "fold_where": "T: Fold", - "visit_where": "T: Visit" - }, - "ops::SimIoForGlobal": { - "data": { - "$kind": "Struct", - "$constructor": "ops::SimIoForGlobal::new", - "global()": "Visible" - } - }, "BlockId": { "data": { "$kind": "Opaque" @@ -1289,9 +1255,7 @@ "RegSync": "Visible", "RegAsync": "Visible", "Wire": "Visible", - "Instance": "Visible", - "FormalInput": "Visible", - "SimIoForGlobal": "Visible" + "Instance": "Visible" } }, "TargetChild": { @@ -1319,25 +1283,12 @@ "$kind": "Struct" } }, - "TargetPathTraceAsStringInner": { - "data": { - "$kind": "Struct" - } - }, - "TargetPathToTraceAsString": { - "data": { - "$kind": "Struct", - "ty": "Visible" - } - }, "TargetPathElement": { "data": { "$kind": "Enum", "BundleField": "Visible", "ArrayElement": "Visible", - "DynArrayElement": "Visible", - "TraceAsStringInner": "Visible", - "ToTraceAsString": "Visible" + "DynArrayElement": "Visible" } }, "PhantomConst": { @@ -1355,29 +1306,6 @@ "data": { "$kind": "ManualImpl" } - }, - "TraceAsString": { - "data": { - "$kind": "ManualImpl" - }, - "generics": "", - "fold_where": "T: Fold", - "visit_where": "T: Visit" - }, - "FormalInput": { - "data": { - "$kind": "Struct", - "$constructor": "FormalInput::new", - "kind()": "Visible", - "name_id()": "Visible", - "ty()": "Visible", - "source_location()": "Visible" - } - }, - "FormalInputKind": { - "data": { - "$kind": "Opaque" - } } } } \ No newline at end of file diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh index 779bcbf..99205bb 100755 --- a/scripts/check-copyright.sh +++ b/scripts/check-copyright.sh @@ -47,7 +47,7 @@ function main() */LICENSE.md|*/Notices.txt) # copyright file ;; - /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt) + /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt) # file that can't contain copyright header ;; /.forgejo/workflows/*.yml|*/.gitignore|*.toml|*/Makefile|*/_CoqProject)