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5d68885eaf
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fayalite::testing: add checked_vcd_output!()
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2026-06-05 00:35:19 -07:00 |
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8cff3687f7
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Run Rocq tests.
/ test (pull_request) Successful in 8m7s
/ test (push) Successful in 4m58s
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2026-03-30 19:36:24 -03:00 |
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e4210a672f
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Check copyright header in Rocq files.
/ test (pull_request) Successful in 4m4s
/ test (push) Successful in 4m39s
If we ever add Verilog files, we can "or" both results, I guess.
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2025-12-09 07:45:35 -03:00 |
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259bee39c2
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tests/sim: split expected output text into separate files
/ deps (push) Successful in 18s
/ test (push) Successful in 5m16s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m22s
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2024-12-05 18:17:13 -08:00 |
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053391b010
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add script for checking copyright headers
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2024-09-22 15:29:28 -07:00 |
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