sim: WIP working on memory
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3ed7827485
commit
9654167ca3
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@ -1215,10 +1215,16 @@ struct Register {
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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enum MemoryPort {
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ReadOnly {},
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struct MemoryPort {
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WriteOnly {},
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clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
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ReadWrite {},
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addr_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
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en_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
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data: CompiledValue<CanonicalType>,
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read_data_delayed: Vec<TypeIndex>,
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write_data_delayed: Vec<TypeIndex>,
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write_mask_delayed: Vec<TypeIndex>,
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write_mode_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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@ -3350,11 +3356,37 @@ impl Compiler {
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};
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};
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self.decl_conditions.insert(target, conditions);
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self.decl_conditions.insert(target, conditions);
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trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
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trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
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todo!("handle read/write");
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match port.port_kind() {
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match port.port_kind() {
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PortKind::ReadOnly => MemoryPort::ReadOnly {},
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PortKind::ReadOnly => MemoryPort {
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PortKind::WriteOnly => MemoryPort::WriteOnly {},
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clk_triggered: todo!(),
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PortKind::ReadWrite => MemoryPort::ReadWrite {},
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addr_delayed: todo!(),
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en_delayed: todo!(),
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data: todo!(),
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read_data_delayed: todo!(),
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write_data_delayed: todo!(),
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write_mask_delayed: todo!(),
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write_mode_delayed: todo!(),
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},
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PortKind::WriteOnly => MemoryPort {
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clk_triggered: todo!(),
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addr_delayed: todo!(),
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en_delayed: todo!(),
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data: todo!(),
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read_data_delayed: todo!(),
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write_data_delayed: todo!(),
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write_mask_delayed: todo!(),
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write_mode_delayed: todo!(),
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},
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PortKind::ReadWrite => MemoryPort {
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clk_triggered: todo!(),
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addr_delayed: todo!(),
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en_delayed: todo!(),
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data: todo!(),
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read_data_delayed: todo!(),
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write_data_delayed: todo!(),
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write_mask_delayed: todo!(),
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write_mode_delayed: todo!(),
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},
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}
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}
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})
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})
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.collect();
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.collect();
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