From 9654167ca3644dd8ff143923bd9eddc38951af09 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 6 Dec 2024 15:53:34 -0800 Subject: [PATCH] sim: WIP working on memory --- crates/fayalite/src/sim.rs | 48 +++++++++++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 8 deletions(-) diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 3802ae4..321ab49 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -1215,10 +1215,16 @@ struct Register { } #[derive(Debug)] -enum MemoryPort { - ReadOnly {}, - WriteOnly {}, - ReadWrite {}, + +struct MemoryPort { + clk_triggered: StatePartIndex, + addr_delayed: Vec>, + en_delayed: Vec>, + data: CompiledValue, + read_data_delayed: Vec, + write_data_delayed: Vec, + write_mask_delayed: Vec, + write_mode_delayed: Vec>, } #[derive(Debug)] @@ -3350,11 +3356,37 @@ impl Compiler { }; self.decl_conditions.insert(target, conditions); trace_decls.push(self.make_trace_decl(instantiated_module, target_base)); - todo!("handle read/write"); match port.port_kind() { - PortKind::ReadOnly => MemoryPort::ReadOnly {}, - PortKind::WriteOnly => MemoryPort::WriteOnly {}, - PortKind::ReadWrite => MemoryPort::ReadWrite {}, + PortKind::ReadOnly => MemoryPort { + clk_triggered: todo!(), + addr_delayed: todo!(), + en_delayed: todo!(), + data: todo!(), + read_data_delayed: todo!(), + write_data_delayed: todo!(), + write_mask_delayed: todo!(), + write_mode_delayed: todo!(), + }, + PortKind::WriteOnly => MemoryPort { + clk_triggered: todo!(), + addr_delayed: todo!(), + en_delayed: todo!(), + data: todo!(), + read_data_delayed: todo!(), + write_data_delayed: todo!(), + write_mask_delayed: todo!(), + write_mode_delayed: todo!(), + }, + PortKind::ReadWrite => MemoryPort { + clk_triggered: todo!(), + addr_delayed: todo!(), + en_delayed: todo!(), + data: todo!(), + read_data_delayed: todo!(), + write_data_delayed: todo!(), + write_mask_delayed: todo!(), + write_mode_delayed: todo!(), + }, } }) .collect();