libre-chip/fayalite
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add some missing #[track_caller]

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Jacob Lifshay 2025-03-19 17:10:51 -07:00
parent d453755bb2
commit 920d8d875f
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 4 additions and 0 deletions
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4
crates/fayalite/src/module.rs
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@ -2174,6 +2174,7 @@ impl ModuleBuilder {
.builder_extern_body()
.verilog_name = name.intern();
}
#[track_caller]
pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) {
let name = name.as_ref();
self.impl_
@ -2186,6 +2187,7 @@ impl ModuleBuilder {
value,
});
}
#[track_caller]
pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) {
let name = name.as_ref();
let value = value.into();
@ -2199,6 +2201,7 @@ impl ModuleBuilder {
value: ExternModuleParameterValue::Integer(value),
});
}
#[track_caller]
pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) {
let name = name.as_ref();
let value = value.as_ref();
@ -2212,6 +2215,7 @@ impl ModuleBuilder {
value: ExternModuleParameterValue::String(value.intern()),
});
}
#[track_caller]
pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) {
let name = name.as_ref();
let raw_verilog = raw_verilog.as_ref();