From 920d8d875f80b970a996b4d45f06b145a07fba84 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 19 Mar 2025 17:10:51 -0700
Subject: [PATCH] add some missing #[track_caller]

---
 crates/fayalite/src/module.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 446746a..d26dc7b 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -2174,6 +2174,7 @@ impl ModuleBuilder {
             .builder_extern_body()
             .verilog_name = name.intern();
     }
+    #[track_caller]
     pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) {
         let name = name.as_ref();
         self.impl_
@@ -2186,6 +2187,7 @@ impl ModuleBuilder {
                 value,
             });
     }
+    #[track_caller]
     pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) {
         let name = name.as_ref();
         let value = value.into();
@@ -2199,6 +2201,7 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::Integer(value),
             });
     }
+    #[track_caller]
     pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) {
         let name = name.as_ref();
         let value = value.as_ref();
@@ -2212,6 +2215,7 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::String(value.intern()),
             });
     }
+    #[track_caller]
     pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) {
         let name = name.as_ref();
         let raw_verilog = raw_verilog.as_ref();