From 903ca1bf30827903608938f6993e586e13cf54ca Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 12 Dec 2024 19:47:57 -0800 Subject: [PATCH] sim: simple memory test works! --- crates/fayalite/src/memory.rs | 65 +- crates/fayalite/src/sim.rs | 168 +- crates/fayalite/src/sim/interpreter.rs | 387 ++- crates/fayalite/tests/sim.rs | 111 +- .../tests/sim/expected/connect_const.txt | 9 +- .../sim/expected/connect_const_reset.txt | 21 +- .../tests/sim/expected/counter_async.txt | 72 +- .../tests/sim/expected/counter_sync.txt | 62 +- crates/fayalite/tests/sim/expected/enums.txt | 412 +-- .../fayalite/tests/sim/expected/memories.txt | 2776 +++++++++++++++++ .../fayalite/tests/sim/expected/memories.vcd | 408 +++ crates/fayalite/tests/sim/expected/mod1.txt | 69 +- .../tests/sim/expected/shift_register.txt | 96 +- 13 files changed, 4146 insertions(+), 510 deletions(-) create mode 100644 crates/fayalite/tests/sim/expected/memories.txt create mode 100644 crates/fayalite/tests/sim/expected/memories.vcd diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs index 4992cd6..2f0ec47 100644 --- a/crates/fayalite/src/memory.rs +++ b/crates/fayalite/src/memory.rs @@ -519,7 +519,12 @@ impl fmt::Debug for Mem { f.debug_struct("Mem") .field("name", scoped_name) .field("array_type", array_type) - .field("initial_value", initial_value) + .field( + "initial_value", + &initial_value.as_ref().map(|initial_value| { + DebugMemoryData::from_bit_slice(*array_type, initial_value) + }), + ) .field("read_latency", read_latency) .field("write_latency", write_latency) .field("read_under_write", read_under_write) @@ -1079,3 +1084,61 @@ pub fn splat_mask(ty: T, value: Expr) -> Expr> { )), } } + +pub trait DebugMemoryDataGetElement { + fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice; +} + +impl<'a, F: ?Sized + Fn(usize, Array) -> &'a BitSlice> DebugMemoryDataGetElement for &'a F { + fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice { + self(element_index, array_type) + } +} + +#[derive(Clone)] +pub struct DebugMemoryData { + pub array_type: Array, + pub get_element: GetElement, +} + +impl DebugMemoryDataGetElement for &'_ BitSlice { + fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice { + assert!(element_index < array_type.len()); + let stride = array_type.element().bit_width(); + let start = element_index + .checked_mul(stride) + .expect("memory is too big"); + let end = start.checked_add(stride).expect("memory is too big"); + &self[start..end] + } +} + +impl<'a> DebugMemoryData<&'a BitSlice> { + pub fn from_bit_slice( + array_type: ArrayType, + bit_slice: &'a BitSlice, + ) -> Self { + let array_type = array_type.as_dyn_array(); + assert_eq!(bit_slice.len(), array_type.type_properties().bit_width); + Self { + array_type, + get_element: bit_slice, + } + } +} + +impl fmt::Debug for DebugMemoryData { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + if self.array_type.len() == 0 { + return f.write_str("[]"); + } + writeln!(f, "[\n // len = {:#x}", self.array_type.len())?; + for element_index in 0..self.array_type.len() { + let element = crate::util::BitSliceWriteWithBase( + self.get_element.get_element(element_index, self.array_type), + ); + writeln!(f, " [{element_index:#x}]: {element:#x},")?; + } + f.write_str("]") + } +} diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 731f469..a2b9648 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -26,12 +26,13 @@ use crate::{ reset::{ResetType, ResetTypeDispatch}, sim::{ interpreter::{ - Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, - InsnsBuildingDone, InsnsBuildingKind, Label, SlotDebugData, SmallUInt, State, - StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex, StatePartIndexRange, - StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots, - StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes, - TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts, + BreakAction, BreakpointsSet, Insn, InsnField, InsnFieldKind, InsnFieldType, + InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label, + MemoryData, RunResult, SlotDebugData, SmallUInt, State, StatePartArrayIndex, + StatePartArrayIndexed, StatePartIndex, StatePartIndexRange, StatePartKind, + StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout, + StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex, + TypeIndexRange, TypeLayout, TypeLen, TypeParts, }, time::{SimDuration, SimInstant}, }, @@ -4274,12 +4275,15 @@ impl Compiler { .memories .allocate(&StatePartLayout::scalar( (), - mem.initial_value().unwrap_or_else(|| { - Intern::intern_owned(BitVec::repeat( - false, - mem.array_type().type_properties().bit_width, - )) - }), + MemoryData { + array_type: mem.array_type(), + data: mem.initial_value().unwrap_or_else(|| { + Intern::intern_owned(BitVec::repeat( + false, + mem.array_type().type_properties().bit_width, + )) + }), + }, )) .start; let (ports, trace_ports) = mem @@ -4765,9 +4769,10 @@ impl Compiler { source_location, }| { self.insns.push( - Insn::NotSmall { + Insn::XorSmallImmediate { dest: last_clk_was_low, - src: clk, + lhs: clk, + rhs: 1, }, source_location, ); @@ -4857,14 +4862,6 @@ impl Compiler { } in mem::take(ports) { let port_end = self.insns.new_label(); - self.insns.push( - Insn::BranchIfSmallZero { - target: port_end.0, - value: clk_triggered, - }, - mem.source_location(), - ); - self.insns.extend(write_insns, mem.source_location()); let small_shift_reg = |this: &mut Self, values: &[StatePartIndex]| { for pair in values.windows(2).rev() { @@ -4883,12 +4880,20 @@ impl Compiler { .extend(pair[0].insns_for_copy_to(pair[1]), mem.source_location()); } }; + self.insns.push( + Insn::BranchIfSmallZero { + target: port_end.0, + value: clk_triggered, + }, + mem.source_location(), + ); small_shift_reg(self, &addr_delayed); small_shift_reg(self, &en_delayed); - shift_reg(self, &read_data_delayed); shift_reg(self, &write_data_delayed); shift_reg(self, &write_mask_delayed); small_shift_reg(self, &write_mode_delayed); + shift_reg(self, &read_data_delayed); + self.insns.extend(write_insns, mem.source_location()); self.insns.define_label_at_next_insn(port_end); } } @@ -5814,9 +5819,50 @@ struct SimulationImpl { trace_writers: Vec>, instant: SimInstant, clocks_triggered: Interned<[StatePartIndex]>, + breakpoints: Option, +} + +impl fmt::Debug for SimulationImpl { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.debug_fmt(None, f) + } } impl SimulationImpl { + fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + state, + io: self_io, + uninitialized_inputs, + io_targets, + made_initial_step, + needs_settle, + trace_decls, + traces, + trace_memories, + trace_writers, + instant, + clocks_triggered, + breakpoints: _, + } = self; + f.debug_struct("Simulation") + .field("state", state) + .field("io", io.unwrap_or(self_io)) + .field( + "uninitialized_inputs", + &SortedSetDebug(uninitialized_inputs), + ) + .field("io_targets", &SortedMapDebug(io_targets)) + .field("made_initial_step", made_initial_step) + .field("needs_settle", needs_settle) + .field("trace_decls", trace_decls) + .field("traces", traces) + .field("trace_memories", trace_memories) + .field("trace_writers", trace_writers) + .field("instant", instant) + .field("clocks_triggered", clocks_triggered) + .finish_non_exhaustive() + } fn parse_io(&mut self, target: Target, value: CompiledValue) { self.io_targets.insert(target, value); match value.layout.body { @@ -5876,6 +5922,7 @@ impl SimulationImpl { trace_writers: vec![], instant: SimInstant::START, clocks_triggered: compiled.clocks_triggered, + breakpoints: None, }; let io_target = Target::from(compiled.io); for (BundleField { name, .. }, value) in compiled @@ -5905,7 +5952,7 @@ impl SimulationImpl { trace_writer.set_memory_element( self.trace_memories[&memory].id, element_index, - &self.state.memories[memory][start..end], + &self.state.memories[memory].data[start..end], ) }; if ONLY_IF_CHANGED { @@ -6054,7 +6101,30 @@ impl SimulationImpl { return; } self.state.setup_call(0); - self.state.run(); + if self.breakpoints.is_some() { + loop { + match self + .state + .run(self.breakpoints.as_mut().expect("just checked")) + { + RunResult::Break(break_action) => { + println!( + "hit breakpoint at:\n{:?}", + self.state.debug_insn_at(self.state.pc), + ); + match break_action { + BreakAction::DumpStateAndContinue => { + println!("{self:#?}"); + } + BreakAction::Continue => {} + } + } + RunResult::Return(()) => break, + } + } + } else { + let RunResult::Return(()) = self.state.run(()); + } if self.made_initial_step { self.read_traces::(); } else { @@ -6097,7 +6167,7 @@ impl SimulationImpl { if Some(&target) == self.io.target().as_deref() || Some(target.base()) != self.io.target().map(|v| v.base()) { - panic!("simulator read/write expression must be an array element/field of `Simulator::io()`"); + panic!("simulator read/write expression must be an array element/field of `Simulation::io()`"); }; panic!("simulator read/write expression must not have dynamic array indexes"); } @@ -6361,41 +6431,8 @@ impl fmt::Debug for SortedMapDebug<'_, K, V> { impl fmt::Debug for Simulation { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - sim_impl: - SimulationImpl { - state, - io: _, - uninitialized_inputs, - io_targets, - made_initial_step, - needs_settle, - trace_decls, - traces, - trace_memories, - trace_writers, - instant, - clocks_triggered, - }, - io, - } = self; - f.debug_struct("Simulation") - .field("state", state) - .field("io", io) - .field( - "uninitialized_inputs", - &SortedSetDebug(uninitialized_inputs), - ) - .field("io_targets", &SortedMapDebug(io_targets)) - .field("made_initial_step", made_initial_step) - .field("needs_settle", needs_settle) - .field("trace_decls", trace_decls) - .field("traces", traces) - .field("trace_memories", trace_memories) - .field("trace_writers", trace_writers) - .field("instant", instant) - .field("clocks_triggered", clocks_triggered) - .finish() + let Self { sim_impl, io } = self; + sim_impl.debug_fmt(Some(io), f) } } @@ -6488,4 +6525,13 @@ impl Simulation { pub fn read_reset(&mut self, io: Expr) -> bool { self.sim_impl.read_bit(Expr::canonical(io)) } + #[doc(hidden)] + /// This is explicitly unstable and may be changed/removed at any time + pub fn set_breakpoints_unstable(&mut self, pcs: HashSet, trace: bool) { + self.sim_impl.breakpoints = Some(BreakpointsSet { + last_was_break: false, + set: pcs, + trace, + }); + } } diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index 54645eb..22f6f5f 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -2,6 +2,7 @@ // See Notices.txt for copyright information use crate::{ + array::Array, int::{BoolOrIntType, SInt, UInt}, intern::{Intern, Interned, Memoize}, source_location::SourceLocation, @@ -9,17 +10,17 @@ use crate::{ util::get_many_mut, }; use bitvec::{boxed::BitBox, slice::BitSlice}; -use hashbrown::HashMap; +use hashbrown::{HashMap, HashSet}; use num_bigint::BigInt; use num_traits::{One, Signed, ToPrimitive, Zero}; use std::{ any::TypeId, borrow::BorrowMut, convert::Infallible, - fmt, + fmt::{self, Write}, hash::{Hash, Hasher}, marker::PhantomData, - ops::{Deref, DerefMut, Index, IndexMut}, + ops::{ControlFlow, Deref, DerefMut, Index, IndexMut}, }; use vec_map::VecMap; @@ -174,7 +175,37 @@ fn make_array_into_iter( impl fmt::Debug for Insn { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.debug_fmt::(f, None, None) + self.debug_fmt::(f, None, None, None) + } +} + +struct PrefixLinesWrapper<'a, W> { + writer: W, + at_beginning_of_line: bool, + blank_line_prefix: &'a str, + line_prefix: &'a str, +} + +impl fmt::Write for PrefixLinesWrapper<'_, T> { + fn write_str(&mut self, input: &str) -> fmt::Result { + for part in input.split_inclusive('\n') { + if part.is_empty() { + continue; + } + if self.at_beginning_of_line { + let prefix = match part { + "\n" => self.blank_line_prefix, + _ => self.line_prefix, + }; + if !prefix.is_empty() { + self.writer.write_str(prefix)?; + } + self.at_beginning_of_line = false; + } + self.writer.write_str(part)?; + self.at_beginning_of_line = part.ends_with('\n'); + } + Ok(()) } } @@ -184,15 +215,22 @@ impl Insn { f: &mut fmt::Formatter<'_>, labels: Option<&Labels>, state_layout: Option<&StateLayout>, + state: Option<&State>, ) -> fmt::Result { let (insn_name, fields) = self.fields_with_names(); write!(f, "{insn_name}")?; if fields.len() == 0 { return Ok(()); } + let mut f = PrefixLinesWrapper { + writer: f, + at_beginning_of_line: false, + blank_line_prefix: "", + line_prefix: " ", + }; writeln!(f, " {{")?; for (field_name, field) in fields { - write!(f, " {field_name}: ")?; + write!(f, "{field_name}: ")?; match field.kind { InsnFieldKind::BranchTarget => match field.ty { InsnFieldType::USize(&label_index) => { @@ -227,35 +265,100 @@ impl Insn { | InsnFieldKind::Output | InsnFieldKind::Immediate => {} } + macro_rules! debug_fmt_state_part { + ($v:expr) => { + $v.debug_fmt(&mut f, ",", " // ", " // ", "", state_layout, state) + }; + } match field.ty { InsnFieldType::Memory(v) => { - v.debug_fmt(f, ",", " // ", "", state_layout)?; + debug_fmt_state_part!(v)?; } InsnFieldType::SmallSlot(v) => { - v.debug_fmt(f, ",", " // ", "", state_layout)?; + debug_fmt_state_part!(v)?; } InsnFieldType::BigSlot(v) => { - v.debug_fmt(f, ",", " // ", "", state_layout)?; + debug_fmt_state_part!(v)?; } InsnFieldType::SmallSlotArrayIndexed(v) => { - v.debug_fmt(f, ",", " // ", "", state_layout)?; + debug_fmt_state_part!(v)?; } InsnFieldType::BigSlotArrayIndexed(v) => { - v.debug_fmt(f, ",", " // ", "", state_layout)?; + debug_fmt_state_part!(v)?; } - InsnFieldType::SmallUInt(v) => fmt::Debug::fmt(v, f)?, - InsnFieldType::SmallSInt(v) => fmt::Debug::fmt(v, f)?, - InsnFieldType::InternedBigInt(v) => fmt::Debug::fmt(v, f)?, - InsnFieldType::U8(v) => fmt::Debug::fmt(v, f)?, - InsnFieldType::USize(v) => fmt::Debug::fmt(v, f)?, - InsnFieldType::Empty(v) => fmt::Debug::fmt(v, f)?, + InsnFieldType::SmallUInt(v) => write!(f, "{v:#x}")?, + InsnFieldType::SmallSInt(v) => write!(f, "{v:#x}")?, + InsnFieldType::InternedBigInt(v) => write!(f, "{v:#x}")?, + InsnFieldType::U8(v) => write!(f, "{v:#x}")?, + InsnFieldType::USize(v) => write!(f, "{v}")?, + InsnFieldType::Empty(v) => write!(f, "{v:?}")?, } writeln!(f, ",")?; } - write!(f, "}}") + write!(f.writer, "}}") } } +pub(crate) trait Breakpoints { + type Break; + fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow; +} + +impl Breakpoints for &'_ mut T { + type Break = T::Break; + fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow { + T::check_for_breakpoint(self, pc) + } +} + +impl Breakpoints for Box { + type Break = T::Break; + fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow { + T::check_for_breakpoint(self, pc) + } +} + +impl Breakpoints for () { + type Break = Infallible; + fn check_for_breakpoint(&mut self, _pc: usize) -> ControlFlow { + ControlFlow::Continue(()) + } +} + +pub(crate) struct BreakpointsSet { + pub(crate) last_was_break: bool, + pub(crate) set: HashSet, + pub(crate) trace: bool, +} + +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] +pub(crate) enum BreakAction { + DumpStateAndContinue, + Continue, +} + +impl Breakpoints for BreakpointsSet { + type Break = BreakAction; + fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow { + let retval = if self.last_was_break { + ControlFlow::Continue(()) + } else if self.set.contains(&pc) { + ControlFlow::Break(BreakAction::DumpStateAndContinue) + } else if self.trace { + ControlFlow::Break(BreakAction::Continue) + } else { + ControlFlow::Continue(()) + }; + self.last_was_break = retval.is_break(); + retval + } +} + +pub(crate) enum RunResult { + Break(Break), + Return(Return), +} + macro_rules! impl_insns { ( #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident] @@ -402,11 +505,14 @@ macro_rules! impl_insns { } impl $State { - $vis fn $run(&mut $self) -> $run_ret_ty { + $vis fn $run(&mut $self, mut breakpoints: B) -> RunResult { let mut $state = $state_init; $($setup)* let mut insn = $state.insns[$state.pc]; let retval = 'main_loop: loop { + if let ControlFlow::Break(b) = breakpoints.check_for_breakpoint($state.pc) { + break RunResult::Break(b); + } macro_rules! $next_macro { () => { $state.pc += 1; @@ -542,6 +648,7 @@ struct InsnsDebug<'a, BK: InsnsBuildingKind> { insn_source_locations: &'a [SourceLocation], labels: &'a BK::Labels, state_layout: &'a StateLayout, + state: Option<&'a State>, } struct InsnDebug<'a, BK: InsnsBuildingKind> { @@ -550,6 +657,7 @@ struct InsnDebug<'a, BK: InsnsBuildingKind> { insn: &'a Insn, labels: Option<&'a Labels>, state_layout: &'a StateLayout, + state: Option<&'a State>, } impl fmt::Debug for InsnDebug<'_, BK> { @@ -566,7 +674,8 @@ impl fmt::Debug for InsnDebug<'_, BK> { writeln!(f, "// at: {source_location}")?; } write!(f, "{}: ", self.address)?; - self.insn.debug_fmt(f, self.labels, Some(self.state_layout)) + self.insn + .debug_fmt(f, self.labels, Some(self.state_layout), self.state) } } @@ -591,6 +700,7 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> { insn, labels, state_layout: self.state_layout, + state: self.state, }); last_source_location = Some(source_location); } @@ -598,8 +708,45 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> { } } -impl fmt::Debug for Insns { +impl Insns { + pub(crate) fn debug_insn_at<'a>( + &'a self, + address: usize, + state: Option<&'a State>, + ) -> impl fmt::Debug + 'a { + let Self { + insns, + insn_source_locations, + labels, + state_layout, + } = self; + InsnDebug { + address, + source_location: Some(insn_source_locations[address]), + insn: &insns[address], + labels: BK::labels(labels), + state_layout, + state, + } + } +} + +impl State { + pub(crate) fn debug_insn_at(&self, address: usize) -> impl fmt::Debug + '_ { + self.insns.debug_insn_at(address, Some(self)) + } +} + +struct InsnsOfState<'a>(&'a State); + +impl fmt::Debug for InsnsOfState<'_> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.0.insns.debug_fmt(Some(self.0), f) + } +} + +impl Insns { + fn debug_fmt(&self, state: Option<&State>, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { insns, insn_source_locations, @@ -615,12 +762,19 @@ impl fmt::Debug for Insns { insn_source_locations, labels, state_layout, + state, }, ) .finish_non_exhaustive() } } +impl fmt::Debug for Insns { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.debug_fmt(None, f) + } +} + pub(crate) trait StatePartKind: Send + Sync + Ord + Hash + fmt::Debug + 'static + Copy + Default { @@ -635,6 +789,11 @@ pub(crate) trait StatePartKind: state_layout: &StateLayout, part_index: StatePartIndex, ) -> Option<&Self::DebugData>; + fn debug_fmt_state_value( + state: &State, + index: StatePartIndex, + f: &mut impl fmt::Write, + ) -> fmt::Result; } pub(crate) trait StatePartsValue { @@ -987,7 +1146,6 @@ macro_rules! make_state_part_kinds { } } - #[derive(Debug)] pub(crate) struct State { pub(crate) insns: Interned>, pub(crate) pc: usize, @@ -996,6 +1154,25 @@ macro_rules! make_state_part_kinds { $(pub(crate) $type_field: StatePart<$TypeKind>,)* } + impl fmt::Debug for State { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + insns: _, + pc, + memory_write_log, + $($state_field,)* + $($type_field,)* + } = self; + f.debug_struct("State") + .field("insns", &InsnsOfState(self)) + .field("pc", pc) + .field("memory_write_log", memory_write_log) + $(.field(stringify!($state_field), $state_field))* + $(.field(stringify!($type_field), $type_field))* + .finish() + } + } + impl State { pub(crate) fn new(insns: Interned>) -> Self { Self { @@ -1199,6 +1376,25 @@ macro_rules! make_state_part_kinds { }; } +#[derive(Copy, Clone, Hash, PartialEq, Eq)] +pub(crate) struct MemoryData> { + pub(crate) array_type: Array, + pub(crate) data: T, +} + +impl> fmt::Debug for MemoryData { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { array_type, data } = self; + f.debug_struct("MemoryData") + .field("array_type", array_type) + .field( + "data", + &crate::memory::DebugMemoryData::from_bit_slice(*array_type, data), + ) + .finish() + } +} + make_state_part_kinds! { /*#[state, field = small_stack] impl StatePartKind for StatePartKindSmallStack { @@ -1244,11 +1440,14 @@ make_state_part_kinds! { impl StatePartKind for StatePartKindMemories { const NAME: &'static str = "Memories"; type DebugData = (); - type LayoutData = Interned; - type State = Box<[BitBox]>; - type BorrowedState<'a> = &'a mut [BitBox]; + type LayoutData = MemoryData>; + type State = Box<[MemoryData]>; + type BorrowedState<'a> = &'a mut [MemoryData]; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - layout_data.iter().map(|initial_data| BitBox::from_bitslice(initial_data)).collect() + layout_data.iter().map(|MemoryData { array_type, data }| MemoryData { + array_type: *array_type, + data: BitBox::from_bitslice(data), + }).collect() } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { state @@ -1259,6 +1458,13 @@ make_state_part_kinds! { ) -> Option<&Self::DebugData> { state_layout.memories.debug_data.get(part_index.as_usize()) } + fn debug_fmt_state_value( + state: &State, + index: StatePartIndex, + f: &mut impl fmt::Write, + ) -> fmt::Result { + write!(f, "{:#?}", &state.memories[index]) + } } #[type, field = small_slots] impl StatePartKind for StatePartKindSmallSlots { @@ -1279,6 +1485,15 @@ make_state_part_kinds! { ) -> Option<&Self::DebugData> { state_layout.ty.small_slots.debug_data.get(part_index.as_usize()) } + fn debug_fmt_state_value( + state: &State, + index: StatePartIndex, + f: &mut impl fmt::Write, + ) -> fmt::Result { + let value = state.small_slots[index]; + write!(f, "{value:#x} {}", value as SmallSInt)?; + Ok(()) + } } #[type, field = big_slots] impl StatePartKind for StatePartKindBigSlots { @@ -1299,6 +1514,13 @@ make_state_part_kinds! { ) -> Option<&Self::DebugData> { state_layout.ty.big_slots.debug_data.get(part_index.as_usize()) } + fn debug_fmt_state_value( + state: &State, + index: StatePartIndex, + f: &mut impl fmt::Write, + ) -> fmt::Result { + write!(f, "{:#x}", state.big_slots[index]) + } } } @@ -1474,37 +1696,32 @@ pub(crate) struct StatePartArrayIndexed { impl StatePartArrayIndexed { pub(crate) fn debug_fmt( &self, - f: &mut fmt::Formatter<'_>, + f: &mut impl fmt::Write, before_debug_info_text: &str, comment_start: &str, + comment_line_start: &str, comment_end: &str, state_layout: Option<&StateLayout>, + state: Option<&State>, ) -> fmt::Result { - if let Some(state_layout) = state_layout { - let Self { base, indexes } = *self; - if indexes.is_empty() { - base.debug_fmt( - f, - before_debug_info_text, - comment_start, - comment_end, - Some(state_layout), - ) - } else { - base.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?; - for StatePartArrayIndex { index, len, stride } in indexes { - f.write_str("[")?; - index.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?; - write!(f, ", len={len}, stride={}]", stride.value)?; - } - f.write_str(before_debug_info_text) - } + let Self { base, indexes } = *self; + if indexes.is_empty() { + base.debug_fmt( + f, + before_debug_info_text, + comment_start, + comment_line_start, + comment_end, + state_layout, + state, + ) } else { - let Self { base, indexes } = self; - f.debug_struct("StatePartArrayIndexed") - .field("base", base) - .field("indexes", indexes) - .finish()?; + base.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?; + for StatePartArrayIndex { index, len, stride } in indexes { + f.write_str("[")?; + index.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?; + write!(f, ", len={len}, stride={}]", stride.value)?; + } f.write_str(before_debug_info_text) } } @@ -1512,7 +1729,7 @@ impl StatePartArrayIndexed { impl fmt::Debug for StatePartArrayIndexed { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.debug_fmt::(f, "", "", "", None) + self.debug_fmt::(f, "", "", "", "", None, None) } } @@ -1579,18 +1796,40 @@ impl StatePartIndex { } pub(crate) fn debug_fmt( &self, - f: &mut fmt::Formatter<'_>, + f: &mut impl fmt::Write, before_debug_info_text: &str, comment_start: &str, + comment_line_start: &str, comment_end: &str, state_layout: Option<&StateLayout>, + state: Option<&State>, ) -> fmt::Result { write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)?; f.write_str(before_debug_info_text)?; - if let Some(state_layout) = state_layout { - if let Some(debug_data) = K::part_debug_data(state_layout, *self) { - write!(f, "{comment_start}{debug_data:?}{comment_end}")?; - } + let debug_data = + state_layout.and_then(|state_layout| K::part_debug_data(state_layout, *self)); + if state.is_some() || debug_data.is_some() { + f.write_str(comment_start)?; + } + let mut f = PrefixLinesWrapper { + writer: f, + at_beginning_of_line: false, + blank_line_prefix: comment_line_start.trim_end(), + line_prefix: comment_line_start, + }; + if let Some(state) = state { + f.write_str("(")?; + K::debug_fmt_state_value(state, *self, &mut f)?; + f.write_str(")")?; + } + if state.is_some() && debug_data.is_some() { + f.write_str(" ")?; + } + if let Some(debug_data) = debug_data { + write!(f, "{debug_data:?}")?; + } + if state.is_some() || debug_data.is_some() { + f.writer.write_str(comment_end)?; } Ok(()) } @@ -1598,7 +1837,7 @@ impl StatePartIndex { impl fmt::Debug for StatePartIndex { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.debug_fmt::(f, "", "", "", None) + self.debug_fmt::(f, "", "", "", "", None, None) } } @@ -2182,7 +2421,7 @@ impl BorrowedState<'_> { let Ok(addr) = usize::try_from(addr) else { return; }; - if addr < self.memories.value.len() { + if addr < self.memories[memory].array_type.len() { let log_entry = (memory, addr); if self.memory_write_log.last().copied() == Some(log_entry) { return; @@ -2521,6 +2760,18 @@ impl_insns! { state.big_slots[dest] = value; next!(); } + XorSmallImmediate { + #[kind = Output] + dest: StatePartIndex, + #[kind = Input] + lhs: StatePartIndex, + #[kind = Immediate] + rhs: SmallUInt, + } => { + let value = state.small_slots[lhs] ^ rhs; + state.small_slots[dest] = value; + next!(); + } NotS { #[kind = Output] dest: StatePartIndex, @@ -2543,16 +2794,6 @@ impl_insns! { state.big_slots[dest] = value; next!(); } - NotSmall { - #[kind = Output] - dest: StatePartIndex, - #[kind = Input] - src: StatePartIndex, - } => { - let value = !state.small_slots[src]; - state.small_slots[dest] = value; - next!(); - } Neg { #[kind = Output] dest: StatePartIndex, @@ -2879,7 +3120,7 @@ impl_insns! { width: usize, } => { let addr = state.small_slots[addr]; - state.big_slots[dest] = memory_read_big::(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default(); + state.big_slots[dest] = memory_read_big::(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default(); next!(); } MemoryReadSInt { @@ -2897,7 +3138,7 @@ impl_insns! { width: usize, } => { let addr = state.small_slots[addr]; - state.big_slots[dest] = memory_read_big::(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default(); + state.big_slots[dest] = memory_read_big::(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default(); next!(); } MemoryWriteUInt { @@ -2915,7 +3156,7 @@ impl_insns! { width: usize, } => { let addr = state.small_slots[addr]; - memory_write_big::(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]); + memory_write_big::(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]); state.log_memory_write(memory, addr); next!(); } @@ -2934,11 +3175,11 @@ impl_insns! { width: usize, } => { let addr = state.small_slots[addr]; - memory_write_big::(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]); + memory_write_big::(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]); state.log_memory_write(memory, addr); next!(); } Return => { - break; + break RunResult::Return(()); } } diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 41d966b..2b8f276 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -509,7 +509,6 @@ pub fn memories() { connect_any(mem.new_write_port(), w); } -#[cfg(todo)] // TODO: finish #[hdl] #[test] fn test_memories() { @@ -529,15 +528,107 @@ fn test_memories() { w_data: (u8, i8), w_mask: (bool, bool), } - let io_cycles = [IO { - r_addr: 0, - r_en: false, - r_data: (0, 0), - w_addr: 0, - w_en: false, - w_data: (0, 0), - w_mask: (false, false), - }]; + let io_cycles = [ + IO { + r_addr: 0, + r_en: false, + r_data: (0, 0), + w_addr: 0, + w_en: false, + w_data: (0, 0), + w_mask: (false, false), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x1, 0x23), + w_addr: 0, + w_en: true, + w_data: (0x10, 0x20), + w_mask: (true, true), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x10, 0x20), + w_addr: 0, + w_en: true, + w_data: (0x30, 0x40), + w_mask: (false, true), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x10, 0x40), + w_addr: 0, + w_en: true, + w_data: (0x50, 0x60), + w_mask: (true, false), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x50, 0x40), + w_addr: 0, + w_en: true, + w_data: (0x70, -0x80), + w_mask: (false, false), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x50, 0x40), + w_addr: 0, + w_en: false, + w_data: (0x90, 0xA0u8 as i8), + w_mask: (false, false), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x50, 0x40), + w_addr: 1, + w_en: true, + w_data: (0x90, 0xA0u8 as i8), + w_mask: (true, true), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x50, 0x40), + w_addr: 2, + w_en: true, + w_data: (0xB0, 0xC0u8 as i8), + w_mask: (true, true), + }, + IO { + r_addr: 0, + r_en: true, + r_data: (0x50, 0x40), + w_addr: 2, + w_en: false, + w_data: (0xD0, 0xE0u8 as i8), + w_mask: (true, true), + }, + IO { + r_addr: 1, + r_en: true, + r_data: (0x90, 0xA0u8 as i8), + w_addr: 2, + w_en: false, + w_data: (0xD0, 0xE0u8 as i8), + w_mask: (true, true), + }, + IO { + r_addr: 2, + r_en: true, + r_data: (0xB0, 0xC0u8 as i8), + w_addr: 2, + w_en: false, + w_data: (0xD0, 0xE0u8 as i8), + w_mask: (true, true), + }, + ]; for ( cycle, expected @ IO { diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index e527678..e44c50d 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -33,13 +33,13 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:1:1 0: Const { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: UInt<8> }, - value: 5, + dest: StatePartIndex(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x5, }, // at: module-XXXXXXXXXX.rs:3:1 1: Copy { - dest: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> }, - src: StatePartIndex(1), // SlotDebugData { name: "", ty: UInt<8> }, + dest: StatePartIndex(0), // (0x5) SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> }, + src: StatePartIndex(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> }, }, // at: module-XXXXXXXXXX.rs:1:1 2: Return, @@ -138,4 +138,5 @@ Simulation { trace_writers: [], instant: 0 s, clocks_triggered: [], + .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index f74dbec..d1ab998 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -45,27 +45,27 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:1:1 0: Const { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - value: 1, + dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, }, 1: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: AsyncReset }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset }, + src: StatePartIndex(2), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:4:1 2: Copy { - dest: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, - src: StatePartIndex(3), // SlotDebugData { name: "", ty: AsyncReset }, + dest: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 3: Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, + dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, }, // at: module-XXXXXXXXXX.rs:5:1 4: Copy { - dest: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool }, - src: StatePartIndex(4), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool }, + src: StatePartIndex(4), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 5: Return, @@ -225,4 +225,5 @@ Simulation { ], instant: 1 μs, clocks_triggered: [], + .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index b2bcd56..2e005a0 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -82,85 +82,86 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:1:1 0: Const { - dest: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<1> }, - value: 1, + dest: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, }, 1: Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, // at: module-XXXXXXXXXX.rs:3:1 2: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 3: Const { - dest: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - value: 3, + dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, + value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 4: BranchIfZero { target: 6, - value: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, 5: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:1:1 6: Add { - dest: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - rhs: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 7: CastToUInt { - dest: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<5> }, + dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 8: Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 9: Copy { - dest: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, - src: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 10: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, 11: AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 12: BranchIfSmallNonZero { target: 16, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 13: BranchIfSmallZero { target: 17, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 14: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, 15: Branch { target: 17, }, 16: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 17: NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + 17: XorSmallImmediate { + dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 18: Return, @@ -174,7 +175,7 @@ Simulation { }, small_slots: StatePart { value: [ - 18446744073709551614, + 0, 0, 1, 0, @@ -517,4 +518,5 @@ Simulation { clocks_triggered: [ StatePartIndex(1), ], + .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 1615917..78fc200 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -78,71 +78,72 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:6:1 0: Copy { - dest: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, - src: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:1:1 1: Const { - dest: StatePartIndex(6), // SlotDebugData { name: "", ty: UInt<1> }, - value: 1, + dest: StatePartIndex(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, }, 2: Add { - dest: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - rhs: StatePartIndex(6), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + rhs: StatePartIndex(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 3: CastToUInt { - dest: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<5> }, + dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 4: Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 5: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 6: Const { - dest: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - value: 3, + dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, + value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 7: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, 8: AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 9: BranchIfSmallZero { target: 14, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 10: BranchIfSmallNonZero { target: 13, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 11: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, 12: Branch { target: 14, }, 13: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 14: NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + 14: XorSmallImmediate { + dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 15: Return, @@ -156,7 +157,7 @@ Simulation { }, small_slots: StatePart { value: [ - 18446744073709551614, + 0, 0, 1, 0, @@ -498,4 +499,5 @@ Simulation { clocks_triggered: [ StatePartIndex(1), ], + .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index 5f958ad..ebdcf7e 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -398,476 +398,477 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:1:1 0: Const { - dest: StatePartIndex(72), // SlotDebugData { name: "", ty: UInt<4> }, - value: 0, + dest: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + value: 0x0, }, 1: SliceInt { - dest: StatePartIndex(61), // SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> }, + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> }, start: 2, len: 2, }, 2: CastToSInt { - dest: StatePartIndex(62), // SlotDebugData { name: "", ty: SInt<2> }, - src: StatePartIndex(61), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 2, }, 3: Const { - dest: StatePartIndex(54), // SlotDebugData { name: "", ty: UInt<2> }, - value: 2, + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x2, }, 4: SliceInt { - dest: StatePartIndex(41), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> }, + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> }, start: 1, len: 1, }, 5: Copy { - dest: StatePartIndex(42), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(41), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(42), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 6: Copy { - dest: StatePartIndex(60), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(42), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(42), // (0x1) SlotDebugData { name: "", ty: Bool }, }, 7: SliceInt { - dest: StatePartIndex(38), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> }, + dest: StatePartIndex(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> }, start: 0, len: 1, }, 8: Copy { - dest: StatePartIndex(39), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(38), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 9: Copy { - dest: StatePartIndex(40), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(39), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "", ty: Bool }, }, 10: Copy { - dest: StatePartIndex(36), // SlotDebugData { name: ".0", ty: UInt<1> }, - src: StatePartIndex(40), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 11: Copy { - dest: StatePartIndex(37), // SlotDebugData { name: ".1", ty: Bool }, - src: StatePartIndex(42), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: ".1", ty: Bool }, + src: StatePartIndex(42), // (0x1) SlotDebugData { name: "", ty: Bool }, }, 12: Copy { - dest: StatePartIndex(58), // SlotDebugData { name: "[0]", ty: UInt<1> }, - src: StatePartIndex(40), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 13: Copy { - dest: StatePartIndex(59), // SlotDebugData { name: "[1]", ty: UInt<1> }, - src: StatePartIndex(60), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 14: Copy { - dest: StatePartIndex(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> }, - src: StatePartIndex(58), // SlotDebugData { name: "[0]", ty: UInt<1> }, + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> }, }, 15: Copy { - dest: StatePartIndex(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> }, - src: StatePartIndex(59), // SlotDebugData { name: "[1]", ty: UInt<1> }, + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> }, }, 16: Copy { - dest: StatePartIndex(57), // SlotDebugData { name: ".b", ty: SInt<2> }, - src: StatePartIndex(62), // SlotDebugData { name: "", ty: SInt<2> }, + dest: StatePartIndex(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> }, + src: StatePartIndex(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> }, }, 17: Copy { - dest: StatePartIndex(50), // SlotDebugData { name: ".0", ty: UInt<2> }, - src: StatePartIndex(54), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, }, 18: Copy { - dest: StatePartIndex(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> }, - src: StatePartIndex(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> }, + dest: StatePartIndex(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> }, + src: StatePartIndex(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> }, }, 19: Copy { - dest: StatePartIndex(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> }, - src: StatePartIndex(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> }, + dest: StatePartIndex(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> }, }, 20: Copy { - dest: StatePartIndex(53), // SlotDebugData { name: ".1.b", ty: SInt<2> }, - src: StatePartIndex(57), // SlotDebugData { name: ".b", ty: SInt<2> }, + dest: StatePartIndex(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> }, + src: StatePartIndex(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> }, }, 21: Shl { - dest: StatePartIndex(63), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> }, + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> }, rhs: 1, }, 22: Or { - dest: StatePartIndex(64), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> }, - rhs: StatePartIndex(63), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> }, + rhs: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, }, 23: CastToUInt { - dest: StatePartIndex(65), // SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(53), // SlotDebugData { name: ".1.b", ty: SInt<2> }, + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> }, dest_width: 2, }, 24: Shl { - dest: StatePartIndex(66), // SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(65), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, rhs: 2, }, 25: Or { - dest: StatePartIndex(67), // SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(64), // SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(66), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> }, }, 26: Shl { - dest: StatePartIndex(68), // SlotDebugData { name: "", ty: UInt<6> }, - lhs: StatePartIndex(67), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, rhs: 2, }, 27: Or { - dest: StatePartIndex(69), // SlotDebugData { name: "", ty: UInt<6> }, - lhs: StatePartIndex(50), // SlotDebugData { name: ".0", ty: UInt<2> }, - rhs: StatePartIndex(68), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, + lhs: StatePartIndex(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> }, }, 28: CastToUInt { - dest: StatePartIndex(70), // SlotDebugData { name: "", ty: UInt<6> }, - src: StatePartIndex(69), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, dest_width: 6, }, 29: Copy { - dest: StatePartIndex(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(70), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, }, 30: Const { - dest: StatePartIndex(31), // SlotDebugData { name: "", ty: UInt<2> }, - value: 1, + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x1, }, 31: CmpEq { - dest: StatePartIndex(32), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> }, - rhs: StatePartIndex(31), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> }, + rhs: StatePartIndex(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, 32: Copy { - dest: StatePartIndex(33), // SlotDebugData { name: ".0", ty: UInt<2> }, - src: StatePartIndex(31), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, 33: Copy { - dest: StatePartIndex(34), // SlotDebugData { name: ".1.0", ty: UInt<1> }, - src: StatePartIndex(36), // SlotDebugData { name: ".0", ty: UInt<1> }, + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> }, + src: StatePartIndex(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, }, 34: Copy { - dest: StatePartIndex(35), // SlotDebugData { name: ".1.1", ty: Bool }, - src: StatePartIndex(37), // SlotDebugData { name: ".1", ty: Bool }, + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool }, + src: StatePartIndex(37), // (0x1) SlotDebugData { name: ".1", ty: Bool }, }, 35: Copy { - dest: StatePartIndex(43), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(35), // SlotDebugData { name: ".1.1", ty: Bool }, + dest: StatePartIndex(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool }, }, 36: Shl { - dest: StatePartIndex(44), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(43), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, rhs: 1, }, 37: Or { - dest: StatePartIndex(45), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(34), // SlotDebugData { name: ".1.0", ty: UInt<1> }, - rhs: StatePartIndex(44), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> }, + rhs: StatePartIndex(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, }, 38: Shl { - dest: StatePartIndex(46), // SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(45), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, rhs: 2, }, 39: Or { - dest: StatePartIndex(47), // SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(33), // SlotDebugData { name: ".0", ty: UInt<2> }, - rhs: StatePartIndex(46), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> }, + rhs: StatePartIndex(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> }, }, 40: CastToUInt { - dest: StatePartIndex(48), // SlotDebugData { name: "", ty: UInt<6> }, - src: StatePartIndex(47), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> }, dest_width: 6, }, 41: Copy { - dest: StatePartIndex(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(48), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> }, }, 42: Const { - dest: StatePartIndex(29), // SlotDebugData { name: "", ty: UInt<2> }, - value: 0, + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, }, 43: CmpEq { - dest: StatePartIndex(30), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> }, - rhs: StatePartIndex(29), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> }, + rhs: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, 44: Copy { - dest: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<6> }, - src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + dest: StatePartIndex(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, + src: StatePartIndex(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, 45: SliceInt { - dest: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, start: 2, len: 2, }, 46: SliceInt { - dest: StatePartIndex(15), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, 47: SliceInt { - dest: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, 48: Copy { - dest: StatePartIndex(17), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(17), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 49: Copy { - dest: StatePartIndex(11), // SlotDebugData { name: ".0", ty: UInt<1> }, - src: StatePartIndex(15), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 50: Copy { - dest: StatePartIndex(12), // SlotDebugData { name: ".1", ty: Bool }, - src: StatePartIndex(17), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: ".1", ty: Bool }, + src: StatePartIndex(17), // (0x1) SlotDebugData { name: "", ty: Bool }, }, 51: Copy { - dest: StatePartIndex(73), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(12), // SlotDebugData { name: ".1", ty: Bool }, + dest: StatePartIndex(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: ".1", ty: Bool }, }, 52: Shl { - dest: StatePartIndex(74), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(73), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, rhs: 1, }, 53: Or { - dest: StatePartIndex(75), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(11), // SlotDebugData { name: ".0", ty: UInt<1> }, - rhs: StatePartIndex(74), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, }, 54: CastToUInt { - dest: StatePartIndex(76), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(75), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 4, }, 55: SliceInt { - dest: StatePartIndex(23), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> }, start: 2, len: 4, }, 56: SliceInt { - dest: StatePartIndex(24), // SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(23), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, start: 0, len: 2, }, 57: SliceInt { - dest: StatePartIndex(25), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(24), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, 58: SliceInt { - dest: StatePartIndex(26), // SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(24), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, 59: Copy { - dest: StatePartIndex(21), // SlotDebugData { name: "[0]", ty: UInt<1> }, - src: StatePartIndex(25), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 60: Copy { - dest: StatePartIndex(22), // SlotDebugData { name: "[1]", ty: UInt<1> }, - src: StatePartIndex(26), // SlotDebugData { name: "", ty: UInt<1> }, + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 61: SliceInt { - dest: StatePartIndex(27), // SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(23), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, start: 2, len: 2, }, 62: CastToSInt { - dest: StatePartIndex(28), // SlotDebugData { name: "", ty: SInt<2> }, - src: StatePartIndex(27), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> }, + src: StatePartIndex(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 2, }, 63: Copy { - dest: StatePartIndex(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> }, - src: StatePartIndex(21), // SlotDebugData { name: "[0]", ty: UInt<1> }, + dest: StatePartIndex(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> }, + src: StatePartIndex(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> }, }, 64: Copy { - dest: StatePartIndex(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> }, - src: StatePartIndex(22), // SlotDebugData { name: "[1]", ty: UInt<1> }, + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> }, }, 65: Copy { - dest: StatePartIndex(20), // SlotDebugData { name: ".b", ty: SInt<2> }, - src: StatePartIndex(28), // SlotDebugData { name: "", ty: SInt<2> }, + dest: StatePartIndex(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> }, + src: StatePartIndex(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> }, }, 66: Shl { - dest: StatePartIndex(77), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> }, + dest: StatePartIndex(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> }, rhs: 1, }, 67: Or { - dest: StatePartIndex(78), // SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> }, - rhs: StatePartIndex(77), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> }, + rhs: StatePartIndex(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, }, 68: CastToUInt { - dest: StatePartIndex(79), // SlotDebugData { name: "", ty: UInt<2> }, - src: StatePartIndex(20), // SlotDebugData { name: ".b", ty: SInt<2> }, + dest: StatePartIndex(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> }, dest_width: 2, }, 69: Shl { - dest: StatePartIndex(80), // SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(79), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, rhs: 2, }, 70: Or { - dest: StatePartIndex(81), // SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(78), // SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(80), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + lhs: StatePartIndex(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:8:1 71: AndBigWithSmallImmediate { - dest: StatePartIndex(4), // SlotDebugData { name: "", ty: Enum {A, B, C} }, - lhs: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - rhs: 3, + dest: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + lhs: StatePartIndex(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + rhs: 0x3, }, // at: module-XXXXXXXXXX.rs:15:1 72: BranchIfSmallNeImmediate { target: 75, - lhs: StatePartIndex(4), // SlotDebugData { name: "", ty: Enum {A, B, C} }, - rhs: 0, + lhs: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + rhs: 0x0, }, // at: module-XXXXXXXXXX.rs:16:1 73: Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> }, - src: StatePartIndex(29), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, // at: module-XXXXXXXXXX.rs:17:1 74: Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> }, - src: StatePartIndex(72), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> }, + src: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:15:1 75: BranchIfSmallNeImmediate { target: 78, - lhs: StatePartIndex(4), // SlotDebugData { name: "", ty: Enum {A, B, C} }, - rhs: 1, + lhs: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:18:1 76: Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> }, - src: StatePartIndex(31), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, // at: module-XXXXXXXXXX.rs:19:1 77: Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> }, - src: StatePartIndex(76), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> }, + src: StatePartIndex(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:15:1 78: BranchIfSmallNeImmediate { target: 81, - lhs: StatePartIndex(4), // SlotDebugData { name: "", ty: Enum {A, B, C} }, - rhs: 2, + lhs: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} }, + rhs: 0x2, }, // at: module-XXXXXXXXXX.rs:20:1 79: Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> }, - src: StatePartIndex(54), // SlotDebugData { name: "", ty: UInt<2> }, + dest: StatePartIndex(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> }, + src: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, }, // at: module-XXXXXXXXXX.rs:21:1 80: Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> }, - src: StatePartIndex(81), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> }, + src: StatePartIndex(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:8:1 81: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset }, + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 82: Const { - dest: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<6> }, - value: 0, + dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, + value: 0x0, }, 83: Copy { - dest: StatePartIndex(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<6> }, + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:9:1 84: BranchIfZero { target: 92, - value: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, + value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 85: BranchIfZero { target: 87, - value: StatePartIndex(30), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 86: Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + dest: StatePartIndex(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:10:1 87: BranchIfNonZero { target: 92, - value: StatePartIndex(30), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:12:1 88: BranchIfZero { target: 90, - value: StatePartIndex(32), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 89: Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + dest: StatePartIndex(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:12:1 90: BranchIfNonZero { target: 92, - value: StatePartIndex(32), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 91: Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + dest: StatePartIndex(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:8:1 92: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, }, 93: AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 94: BranchIfSmallZero { target: 99, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 95: BranchIfSmallNonZero { target: 98, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 96: Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + dest: StatePartIndex(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, 97: Branch { target: 99, }, 98: Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, - src: StatePartIndex(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + dest: StatePartIndex(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 99: NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + 99: XorSmallImmediate { + dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 100: Return, @@ -881,7 +882,7 @@ Simulation { }, small_slots: StatePart { value: [ - 18446744073709551614, + 0, 0, 1, 0, @@ -1638,4 +1639,5 @@ Simulation { clocks_triggered: [ StatePartIndex(1), ], + .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt new file mode 100644 index 0000000..afccd8a --- /dev/null +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -0,0 +1,2776 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 12, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 28, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.data.1", + ty: SInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.data.1", + ty: SInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.mask.0", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.mask.1", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", + ty: SInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", + ty: SInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + SlotDebugData { + name: ".0", + ty: Bool, + }, + SlotDebugData { + name: ".1", + ty: Bool, + }, + ], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1: SInt<8>}, 16>, + data: [ + // len = 0x10 + [0x0]: 0x2301, + [0x1]: 0x2301, + [0x2]: 0x2301, + [0x3]: 0x2301, + [0x4]: 0x2301, + [0x5]: 0x2301, + [0x6]: 0x2301, + [0x7]: 0x2301, + [0x8]: 0x2301, + [0x9]: 0x2301, + [0xa]: 0x2301, + [0xb]: 0x2301, + [0xc]: 0x2301, + [0xd]: 0x2301, + [0xe]: 0x2301, + [0xf]: 0x2301, + ], + }, + ], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:8:1 + 0: Copy { + dest: StatePartIndex(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> }, + src: StatePartIndex(5), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.addr", ty: UInt<4> }, + }, + 1: Copy { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.en", ty: Bool }, + }, + 2: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.clk", ty: Clock }, + }, + 3: Copy { + dest: StatePartIndex(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> }, + src: StatePartIndex(8), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.0", ty: UInt<8> }, + }, + 4: Copy { + dest: StatePartIndex(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> }, + src: StatePartIndex(9), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.1", ty: SInt<8> }, + }, + 5: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool }, + src: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.0", ty: Bool }, + }, + 6: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.1", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 7: Copy { + dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.clk", ty: Clock }, + }, + 8: Copy { + dest: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool }, + src: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.en", ty: Bool }, + }, + 9: Copy { + dest: StatePartIndex(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> }, + src: StatePartIndex(0), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 10: CastBigToArrayIndex { + dest: StatePartIndex(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> }, + }, + 11: IsNonZeroDestIsSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool }, + }, + 12: IsNonZeroDestIsSmall { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock }, + }, + 13: AndSmall { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 14: CastBigToArrayIndex { + dest: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> }, + }, + 15: IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool }, + }, + 16: BranchIfSmallZero { + target: 20, + value: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 17: MemoryReadUInt { + dest: StatePartIndex(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1: SInt<8>}, 16>, + // data: [ + // // len = 0x10 + // [0x0]: 0x4050, + // [0x1]: 0xa090, + // [0x2]: 0xc0b0, + // [0x3]: 0x2301, + // [0x4]: 0x2301, + // [0x5]: 0x2301, + // [0x6]: 0x2301, + // [0x7]: 0x2301, + // [0x8]: 0x2301, + // [0x9]: 0x2301, + // [0xa]: 0x2301, + // [0xb]: 0x2301, + // [0xc]: 0x2301, + // [0xd]: 0x2301, + // [0xe]: 0x2301, + // [0xf]: 0x2301, + // ], + // }) (), + addr: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + stride: 16, + start: 0, + width: 8, + }, + 18: MemoryReadSInt { + dest: StatePartIndex(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1: SInt<8>}, 16>, + // data: [ + // // len = 0x10 + // [0x0]: 0x4050, + // [0x1]: 0xa090, + // [0x2]: 0xc0b0, + // [0x3]: 0x2301, + // [0x4]: 0x2301, + // [0x5]: 0x2301, + // [0x6]: 0x2301, + // [0x7]: 0x2301, + // [0x8]: 0x2301, + // [0x9]: 0x2301, + // [0xa]: 0x2301, + // [0xb]: 0x2301, + // [0xc]: 0x2301, + // [0xd]: 0x2301, + // [0xe]: 0x2301, + // [0xf]: 0x2301, + // ], + // }) (), + addr: StatePartIndex(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + stride: 16, + start: 8, + width: 8, + }, + 19: Branch { + target: 22, + }, + 20: Const { + dest: StatePartIndex(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> }, + value: 0x0, + }, + 21: Const { + dest: StatePartIndex(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 22: Copy { + dest: StatePartIndex(3), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.0", ty: UInt<8> }, + src: StatePartIndex(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> }, + }, + 23: Copy { + dest: StatePartIndex(4), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.1", ty: SInt<8> }, + src: StatePartIndex(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 24: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock }, + }, + 25: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 26: BranchIfSmallZero { + target: 27, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 27: BranchIfSmallZero { + target: 39, + value: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 28: CopySmall { + dest: StatePartIndex(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + }, + 29: CopySmall { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 30: Copy { + dest: StatePartIndex(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> }, + src: StatePartIndex(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> }, + }, + 31: Copy { + dest: StatePartIndex(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> }, + src: StatePartIndex(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> }, + }, + 32: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".0", ty: Bool }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool }, + }, + 33: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: ".1", ty: Bool }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool }, + }, + 34: BranchIfSmallZero { + target: 39, + value: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 35: BranchIfZero { + target: 37, + value: StatePartIndex(26), // (0x1) SlotDebugData { name: ".0", ty: Bool }, + }, + 36: MemoryWriteUInt { + value: StatePartIndex(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1: SInt<8>}, 16>, + // data: [ + // // len = 0x10 + // [0x0]: 0x4050, + // [0x1]: 0xa090, + // [0x2]: 0xc0b0, + // [0x3]: 0x2301, + // [0x4]: 0x2301, + // [0x5]: 0x2301, + // [0x6]: 0x2301, + // [0x7]: 0x2301, + // [0x8]: 0x2301, + // [0x9]: 0x2301, + // [0xa]: 0x2301, + // [0xb]: 0x2301, + // [0xc]: 0x2301, + // [0xd]: 0x2301, + // [0xe]: 0x2301, + // [0xf]: 0x2301, + // ], + // }) (), + addr: StatePartIndex(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + stride: 16, + start: 0, + width: 8, + }, + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: ".1", ty: Bool }, + }, + 38: MemoryWriteSInt { + value: StatePartIndex(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1: SInt<8>}, 16>, + // data: [ + // // len = 0x10 + // [0x0]: 0x4050, + // [0x1]: 0xa090, + // [0x2]: 0xc0b0, + // [0x3]: 0x2301, + // [0x4]: 0x2301, + // [0x5]: 0x2301, + // [0x6]: 0x2301, + // [0x7]: 0x2301, + // [0x8]: 0x2301, + // [0x9]: 0x2301, + // [0xa]: 0x2301, + // [0xb]: 0x2301, + // [0xc]: 0x2301, + // [0xd]: 0x2301, + // [0xe]: 0x2301, + // [0xf]: 0x2301, + // ], + // }) (), + addr: StatePartIndex(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> }, + stride: 16, + start: 8, + width: 8, + }, + 39: XorSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 40: XorSmallImmediate { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 41: Return, + ], + .. + }, + pc: 41, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1: SInt<8>}, 16>, + data: [ + // len = 0x10 + [0x0]: 0x4050, + [0x1]: 0xa090, + [0x2]: 0xc0b0, + [0x3]: 0x2301, + [0x4]: 0x2301, + [0x5]: 0x2301, + [0x6]: 0x2301, + [0x7]: 0x2301, + [0x8]: 0x2301, + [0x9]: 0x2301, + [0xa]: 0x2301, + [0xb]: 0x2301, + [0xc]: 0x2301, + [0xd]: 0x2301, + [0xe]: 0x2301, + [0xf]: 0x2301, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 2, + 0, + ], + }, + big_slots: StatePart { + value: [ + 2, + 1, + 0, + 176, + -64, + 2, + 0, + 0, + 208, + -32, + 1, + 1, + 2, + 1, + 0, + 176, + -64, + 2, + 0, + 0, + 208, + -32, + 1, + 1, + 208, + -32, + 1, + 1, + ], + }, + }, + io: Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 5, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.data.1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 5 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 2 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data.0: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data.1: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 7, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.data.1", + ty: SInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.mask.0", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.mask.1", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(5), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: Bool, + }, + SlotDebugData { + name: ".1", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 7 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 2 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data.0: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data.1: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: Bool, + }, + SlotDebugData { + name: ".1", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 2 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask.0: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask.1: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "memories", + children: [ + TraceModuleIO { + name: "r", + child: TraceBundle { + name: "r", + fields: [ + TraceUInt { + location: TraceScalarId(0), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "clk", + flow: Source, + }, + TraceBundle { + name: "data", + fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "0", + ty: UInt<8>, + flow: Sink, + }, + TraceSInt { + location: TraceScalarId(4), + name: "1", + ty: SInt<8>, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + flow: Source, + }, + TraceModuleIO { + name: "w", + child: TraceBundle { + name: "w", + fields: [ + TraceUInt { + location: TraceScalarId(5), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(6), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(7), + name: "clk", + flow: Source, + }, + TraceBundle { + name: "data", + fields: [ + TraceUInt { + location: TraceScalarId(8), + name: "0", + ty: UInt<8>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(9), + name: "1", + ty: SInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Source, + }, + TraceBundle { + name: "mask", + fields: [ + TraceBool { + location: TraceScalarId(10), + name: "0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(11), + name: "1", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + flow: Source, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 16, + element_type: TraceBundle { + name: "mem", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 16, + stride: 16, + start: 0, + len: 8, + }, + name: "0", + ty: UInt<8>, + flow: Duplex, + }, + TraceSInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 16, + stride: 16, + start: 8, + len: 8, + }, + name: "1", + ty: SInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(12), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(13), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(14), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceUInt { + location: TraceScalarId(15), + name: "0", + ty: UInt<8>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(16), + name: "1", + ty: SInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(17), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(18), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(19), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceUInt { + location: TraceScalarId(20), + name: "0", + ty: UInt<8>, + flow: Sink, + }, + TraceSInt { + location: TraceScalarId(21), + name: "1", + ty: SInt<8>, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Sink, + }, + TraceBundle { + name: "mask", + fields: [ + TraceBool { + location: TraceScalarId(22), + name: "0", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(23), + name: "1", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + }, + ], + array_type: Array, 1: SInt<8>}, 16>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<4>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + state: 0xb0, + last_state: 0xb0, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigSInt { + index: StatePartIndex(4), + ty: SInt<8>, + }, + state: 0xc0, + last_state: 0xc0, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<4>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigBool { + index: StatePartIndex(6), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigClock { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(8), + ty: UInt<8>, + }, + state: 0xd0, + last_state: 0xd0, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigSInt { + index: StatePartIndex(9), + ty: SInt<8>, + }, + state: 0xe0, + last_state: 0xe0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(10), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigBool { + index: StatePartIndex(11), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(12), + ty: UInt<4>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigBool { + index: StatePartIndex(13), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigClock { + index: StatePartIndex(14), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<8>, + }, + state: 0xb0, + last_state: 0xb0, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigSInt { + index: StatePartIndex(16), + ty: SInt<8>, + }, + state: 0xc0, + last_state: 0xc0, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigUInt { + index: StatePartIndex(17), + ty: UInt<4>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigBool { + index: StatePartIndex(18), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigClock { + index: StatePartIndex(19), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigUInt { + index: StatePartIndex(20), + ty: UInt<8>, + }, + state: 0xd0, + last_state: 0xd0, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigSInt { + index: StatePartIndex(21), + ty: SInt<8>, + }, + state: 0xe0, + last_state: 0xe0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(22), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(23), + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 16, + element_type: TraceBundle { + name: "mem", + fields: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 16, + stride: 16, + start: 0, + len: 8, + }, + name: "0", + ty: UInt<8>, + flow: Duplex, + }, + TraceSInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 16, + stride: 16, + start: 8, + len: 8, + }, + name: "1", + ty: SInt<8>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(12), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(13), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(14), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceUInt { + location: TraceScalarId(15), + name: "0", + ty: UInt<8>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(16), + name: "1", + ty: SInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(17), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(18), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(19), + name: "clk", + flow: Sink, + }, + TraceBundle { + name: "data", + fields: [ + TraceUInt { + location: TraceScalarId(20), + name: "0", + ty: UInt<8>, + flow: Sink, + }, + TraceSInt { + location: TraceScalarId(21), + name: "1", + ty: SInt<8>, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + flow: Sink, + }, + TraceBundle { + name: "mask", + fields: [ + TraceBool { + location: TraceScalarId(22), + name: "0", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(23), + name: "1", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + }, + ], + array_type: Array, 1: SInt<8>}, 16>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 22 μs, + clocks_triggered: [ + StatePartIndex(1), + StatePartIndex(6), + ], + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd new file mode 100644 index 0000000..72af410 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/memories.vcd @@ -0,0 +1,408 @@ +$timescale 1 ps $end +$scope module memories $end +$scope struct r $end +$var wire 4 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end +$scope struct data $end +$var wire 8 $ \0 $end +$var wire 8 % \1 $end +$upscope $end +$upscope $end +$scope struct w $end +$var wire 4 & addr $end +$var wire 1 ' en $end +$var wire 1 ( clk $end +$scope struct data $end +$var wire 8 ) \0 $end +$var wire 8 * \1 $end +$upscope $end +$scope struct mask $end +$var wire 1 + \0 $end +$var wire 1 , \1 $end +$upscope $end +$upscope $end +$scope struct mem $end +$scope struct contents $end +$scope struct [0] $end +$scope struct mem $end +$var reg 8 9 \0 $end +$var reg 8 I \1 $end +$upscope $end +$upscope $end +$scope struct [1] $end +$scope struct mem $end +$var reg 8 : \0 $end +$var reg 8 J \1 $end +$upscope $end +$upscope $end +$scope struct [2] $end +$scope struct mem $end +$var reg 8 ; \0 $end +$var reg 8 K \1 $end +$upscope $end +$upscope $end +$scope struct [3] $end +$scope struct mem $end +$var reg 8 < \0 $end +$var reg 8 L \1 $end +$upscope $end +$upscope $end +$scope struct [4] $end +$scope struct mem $end +$var reg 8 = \0 $end +$var reg 8 M \1 $end +$upscope $end +$upscope $end +$scope struct [5] $end +$scope struct mem $end +$var reg 8 > \0 $end +$var reg 8 N \1 $end +$upscope $end +$upscope $end +$scope struct [6] $end +$scope struct mem $end +$var reg 8 ? \0 $end +$var reg 8 O \1 $end +$upscope $end +$upscope $end +$scope struct [7] $end +$scope struct mem $end +$var reg 8 @ \0 $end +$var reg 8 P \1 $end +$upscope $end +$upscope $end +$scope struct [8] $end +$scope struct mem $end +$var reg 8 A \0 $end +$var reg 8 Q \1 $end +$upscope $end +$upscope $end +$scope struct [9] $end +$scope struct mem $end +$var reg 8 B \0 $end +$var reg 8 R \1 $end +$upscope $end +$upscope $end +$scope struct [10] $end +$scope struct mem $end +$var reg 8 C \0 $end +$var reg 8 S \1 $end +$upscope $end +$upscope $end +$scope struct [11] $end +$scope struct mem $end +$var reg 8 D \0 $end +$var reg 8 T \1 $end +$upscope $end +$upscope $end +$scope struct [12] $end +$scope struct mem $end +$var reg 8 E \0 $end +$var reg 8 U \1 $end +$upscope $end +$upscope $end +$scope struct [13] $end +$scope struct mem $end +$var reg 8 F \0 $end +$var reg 8 V \1 $end +$upscope $end +$upscope $end +$scope struct [14] $end +$scope struct mem $end +$var reg 8 G \0 $end +$var reg 8 W \1 $end +$upscope $end +$upscope $end +$scope struct [15] $end +$scope struct mem $end +$var reg 8 H \0 $end +$var reg 8 X \1 $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 - addr $end +$var wire 1 . en $end +$var wire 1 / clk $end +$scope struct data $end +$var wire 8 0 \0 $end +$var wire 8 1 \1 $end +$upscope $end +$upscope $end +$scope struct w1 $end +$var wire 4 2 addr $end +$var wire 1 3 en $end +$var wire 1 4 clk $end +$scope struct data $end +$var wire 8 5 \0 $end +$var wire 8 6 \1 $end +$upscope $end +$scope struct mask $end +$var wire 1 7 \0 $end +$var wire 1 8 \1 $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +b1 9 +b100011 I +b1 : +b100011 J +b1 ; +b100011 K +b1 < +b100011 L +b1 = +b100011 M +b1 > +b100011 N +b1 ? +b100011 O +b1 @ +b100011 P +b1 A +b100011 Q +b1 B +b100011 R +b1 C +b100011 S +b1 D +b100011 T +b1 E +b100011 U +b1 F +b100011 V +b1 G +b100011 W +b1 H +b100011 X +b0 ! +0" +0# +b0 $ +b0 % +b0 & +0' +0( +b0 ) +b0 * +0+ +0, +b0 - +0. +0/ +b0 0 +b0 1 +b0 2 +03 +04 +b0 5 +b0 6 +07 +08 +$end +#1000000 +1# +1( +1/ +14 +#2000000 +1" +0# +b1 $ +b100011 % +1' +0( +b10000 ) +b100000 * +1+ +1, +1. +0/ +b1 0 +b100011 1 +13 +04 +b10000 5 +b100000 6 +17 +18 +#3000000 +b10000 9 +b100000 I +1# +1( +1/ +14 +b10000 $ +b100000 % +b10000 0 +b100000 1 +#4000000 +0# +0( +b110000 ) +b1000000 * +0+ +0/ +04 +b110000 5 +b1000000 6 +07 +#5000000 +b10000 9 +b1000000 I +1# +1( +1/ +14 +b1000000 % +b1000000 1 +#6000000 +0# +0( +b1010000 ) +b1100000 * +1+ +0, +0/ +04 +b1010000 5 +b1100000 6 +17 +08 +#7000000 +b1010000 9 +b1000000 I +1# +1( +1/ +14 +b1010000 $ +b1010000 0 +#8000000 +0# +0( +b1110000 ) +b10000000 * +0+ +0/ +04 +b1110000 5 +b10000000 6 +07 +#9000000 +1# +1( +1/ +14 +#10000000 +0# +0' +0( +b10010000 ) +b10100000 * +0/ +03 +04 +b10010000 5 +b10100000 6 +#11000000 +1# +1( +1/ +14 +#12000000 +0# +b1 & +1' +0( +1+ +1, +0/ +b1 2 +13 +04 +17 +18 +#13000000 +b10010000 : +b10100000 J +1# +1( +1/ +14 +#14000000 +0# +b10 & +0( +b10110000 ) +b11000000 * +0/ +b10 2 +04 +b10110000 5 +b11000000 6 +#15000000 +b10110000 ; +b11000000 K +1# +1( +1/ +14 +#16000000 +0# +0' +0( +b11010000 ) +b11100000 * +0/ +03 +04 +b11010000 5 +b11100000 6 +#17000000 +1# +1( +1/ +14 +#18000000 +b1 ! +0# +b10010000 $ +b10100000 % +0( +b1 - +0/ +b10010000 0 +b10100000 1 +04 +#19000000 +1# +1( +1/ +14 +#20000000 +b10 ! +0# +b10110000 $ +b11000000 % +0( +b10 - +0/ +b10110000 0 +b11000000 1 +04 +#21000000 +1# +1( +1/ +14 +#22000000 +0# +0( +0/ +04 diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 8c68108..5c2b7eb 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -93,86 +93,86 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:4:1 0: Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, - src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> }, + dest: StatePartIndex(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, + src: StatePartIndex(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> }, }, 1: Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> }, + dest: StatePartIndex(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, + src: StatePartIndex(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:2:1 2: Copy { - dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, - src: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, + dest: StatePartIndex(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, + src: StatePartIndex(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, }, 3: Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, + dest: StatePartIndex(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, + src: StatePartIndex(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, }, // at: module-XXXXXXXXXX-2.rs:1:1 4: Const { - dest: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<4> }, - value: 15, + dest: StatePartIndex(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + value: 0xf, }, 5: Const { - dest: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<4> }, - value: 5, + dest: StatePartIndex(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> }, + value: 0x5, }, 6: CmpLt { - dest: StatePartIndex(15), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<4> }, - rhs: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, }, 7: CastToUInt { - dest: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, + dest: StatePartIndex(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, dest_width: 4, }, // at: module-XXXXXXXXXX-2.rs:7:1 8: Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, - src: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, + src: StatePartIndex(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX-2.rs:8:1 9: BranchIfZero { target: 11, - value: StatePartIndex(15), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX-2.rs:9:1 10: Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, - src: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<4> }, + dest: StatePartIndex(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, + src: StatePartIndex(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:2:1 11: Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, - src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, + dest: StatePartIndex(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, + src: StatePartIndex(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:4:1 12: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> }, - src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, + dest: StatePartIndex(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> }, + src: StatePartIndex(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, }, // at: module-XXXXXXXXXX-2.rs:1:1 13: CastToSInt { - dest: StatePartIndex(12), // SlotDebugData { name: "", ty: SInt<2> }, - src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, + dest: StatePartIndex(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> }, + src: StatePartIndex(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, dest_width: 2, }, // at: module-XXXXXXXXXX-2.rs:6:1 14: Copy { - dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, - src: StatePartIndex(12), // SlotDebugData { name: "", ty: SInt<2> }, + dest: StatePartIndex(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, + src: StatePartIndex(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> }, }, // at: module-XXXXXXXXXX.rs:2:1 15: Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, - src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, + dest: StatePartIndex(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, + src: StatePartIndex(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, }, // at: module-XXXXXXXXXX.rs:4:1 16: Copy { - dest: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> }, - src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, + dest: StatePartIndex(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> }, + src: StatePartIndex(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, }, // at: module-XXXXXXXXXX.rs:1:1 17: Return, @@ -806,4 +806,5 @@ Simulation { ], instant: 2 μs, clocks_triggered: [], + .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 007c15b..73f6263 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -94,132 +94,133 @@ Simulation { insns: [ // at: module-XXXXXXXXXX.rs:13:1 0: Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, - src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:12:1 1: Copy { - dest: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, - src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 2: Copy { - dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, - src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 3: Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:6:1 4: Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 5: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 6: Const { - dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - value: 0, + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, }, // at: module-XXXXXXXXXX.rs:5:1 7: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, 8: AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 9: BranchIfSmallZero { target: 14, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 10: BranchIfSmallNonZero { target: 13, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 11: Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, - src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, }, 12: Branch { target: 14, }, 13: Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:7:1 14: BranchIfSmallZero { target: 19, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 15: BranchIfSmallNonZero { target: 18, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 16: Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, - src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, }, 17: Branch { target: 19, }, 18: Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 19: BranchIfSmallZero { target: 24, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 20: BranchIfSmallNonZero { target: 23, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 21: Copy { - dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, - src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, }, 22: Branch { target: 24, }, 23: Copy { - dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 24: BranchIfSmallZero { target: 29, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 25: BranchIfSmallNonZero { target: 28, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 26: Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, - src: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, }, 27: Branch { target: 29, }, 28: Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 - 29: NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + 29: XorSmallImmediate { + dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 30: Return, @@ -233,7 +234,7 @@ Simulation { }, small_slots: StatePart { value: [ - 18446744073709551614, + 0, 0, 1, 0, @@ -678,4 +679,5 @@ Simulation { clocks_triggered: [ StatePartIndex(1), ], + .. } \ No newline at end of file