libre-chip/fayalite
2
0
Fork 2
Code Issues Pull requests 1 Actions Packages Projects Releases Wiki Activity

formal: add workaround for wires disappearing because yosys optimizes them out
All checks were successful
/ test (push) Successful in 39m13s
Details

Browse source
This commit is contained in:
Jacob Lifshay 2024-10-15 01:48:48 -07:00
parent 3939ce2360
commit 3d0f95cfe5
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
1 changed files with 5 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
crates/fayalite/src/cli.rs
View file

@ -687,7 +687,11 @@ impl FormalArgs {
} }
writeln!(retval, "read_verilog -sv -formal \"{verilog_file}\"").unwrap(); writeln!(retval, "read_verilog -sv -formal \"{verilog_file}\"").unwrap();
} }
writeln!(retval, "prep -top {top_module}").unwrap(); // workaround for wires disappearing -- set `keep` on all wires
writeln!(retval, "hierarchy -top {top_module}").unwrap();
writeln!(retval, "proc").unwrap();
writeln!(retval, "setattr -set keep 1 w:\\*").unwrap();
writeln!(retval, "prep").unwrap();
Ok(retval) Ok(retval)
} }
fn run_impl( fn run_impl(