From 3d0f95cfe5a910f79177babf8fe12483f83e96f9 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 15 Oct 2024 01:48:48 -0700
Subject: [PATCH] formal: add workaround for wires disappearing because yosys
 optimizes them out

---
 crates/fayalite/src/cli.rs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index a3649cc..1dace37 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -687,7 +687,11 @@ impl FormalArgs {
             }
             writeln!(retval, "read_verilog -sv -formal \"{verilog_file}\"").unwrap();
         }
-        writeln!(retval, "prep -top {top_module}").unwrap();
+        // workaround for wires disappearing -- set `keep` on all wires
+        writeln!(retval, "hierarchy -top {top_module}").unwrap();
+        writeln!(retval, "proc").unwrap();
+        writeln!(retval, "setattr -set keep 1 w:\\*").unwrap();
+        writeln!(retval, "prep").unwrap();
         Ok(retval)
     }
     fn run_impl(