simulating circuits with deduced resets works
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 272 additions and 7 deletions
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@ -16,9 +16,9 @@ use crate::{
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int::BoolOrIntType,
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intern::{Intern, Interned, Memoize},
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module::{
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AnnotatedModuleIO, Block, Id, InstantiatedModule, ModuleBody, NameId, NormalModuleBody,
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ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance,
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StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
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transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, Id, InstantiatedModule,
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ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration,
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StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
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},
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prelude::*,
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sim::{
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@ -1183,6 +1183,7 @@ impl Assignment {
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#[derive(Debug)]
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pub struct Compiler {
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insns: Insns<InsnsBuilding>,
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original_base_module: Interned<Module<Bundle>>,
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base_module: Interned<Module<Bundle>>,
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modules: HashMap<InstantiatedModule, CompiledModule>,
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compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
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@ -1197,8 +1198,12 @@ pub struct Compiler {
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impl Compiler {
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pub fn new(base_module: Interned<Module<Bundle>>) -> Self {
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let original_base_module = base_module;
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let base_module = deduce_resets(base_module, true)
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.unwrap_or_else(|e| panic!("failed to deduce reset types: {e}"));
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Self {
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insns: Insns::new(),
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original_base_module,
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base_module,
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modules: HashMap::new(),
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compiled_values: HashMap::new(),
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@ -1295,7 +1300,7 @@ impl Compiler {
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flow,
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}
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.into(),
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CanonicalType::Reset(ty) => todo!(),
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CanonicalType::Reset(_) => unreachable!(),
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CanonicalType::Clock(ty) => TraceClock {
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id: self.make_trace_scalar_helper(
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target,
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@ -2945,10 +2950,10 @@ impl Compiler {
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io: Instance::new_unchecked(
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ScopedNameId(
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NameId("<simulator>".intern(), Id::new()),
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self.base_module.name_id(),
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self.original_base_module.name_id(),
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),
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self.base_module,
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self.base_module.source_location(),
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self.original_base_module,
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self.original_base_module.source_location(),
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),
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traces: Intern::intern_owned(self.traces),
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}
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@ -156,6 +156,266 @@ fn test_connect_const() {
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assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
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}
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#[hdl_module(outline_generated)]
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pub fn connect_const_reset() {
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#[hdl]
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let reset_out: Reset = m.output();
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#[hdl]
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let bit_out: Bool = m.output();
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connect(reset_out, true.to_async_reset().to_reset());
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connect(bit_out, reset_out.cast_to_static());
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}
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#[test]
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fn test_connect_const_reset() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(connect_const_reset());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.settle_step();
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sim.advance_time(SimDuration::from_micros(1));
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd
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!= r#"$timescale 1 ps $end
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$scope module connect_const_reset $end
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$var wire 1 ! reset_out $end
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$var wire 1 " bit_out $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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1 !
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1 "
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$end
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#1000000
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"# {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug
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!= r#"Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 5,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
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value: 1,
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},
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
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src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
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src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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Copy {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
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src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 5,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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1,
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1,
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1,
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1,
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1,
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],
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},
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},
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io: Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.bit_out: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bool,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
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ty: Bool,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.reset_out: CompiledValue {
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layout: CompiledTypeLayout {
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ty: AsyncReset,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
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ty: AsyncReset,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "connect_const_reset",
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children: [
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TraceModuleIO {
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name: "reset_out",
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child: TraceAsyncReset {
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id: TraceScalarId(0),
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name: "reset_out",
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flow: Sink,
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},
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ty: AsyncReset,
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flow: Sink,
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},
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TraceModuleIO {
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name: "bit_out",
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child: TraceBool {
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id: TraceScalarId(1),
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name: "bit_out",
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flow: Sink,
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},
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ty: Bool,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigAsyncReset {
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index: StatePartIndex<BigSlots>(0),
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},
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state: 0x1,
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last_state: 0x1,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x1,
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last_state: 0x1,
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},
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],
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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instant: 1 μs,
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}"# {
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panic!();
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}
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assert_eq!(sim.read_bool_or_int(sim.io().bit_out), true);
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}
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#[hdl_module(outline_generated)]
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pub fn mod1_child() {
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#[hdl]
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