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fix wire example to actually be about wires, not registers
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This commit is contained in:
Jacob Lifshay 2024-07-26 14:09:52 -07:00
parent b33566841d
commit 305805d237
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
1 changed files with 5 additions and 5 deletions
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10
crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
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@ -15,13 +15,13 @@
//! # #[hdl]
//! # let v: UInt<1> = m.input();
//! #[hdl]
//! let cd: ClockDomain = m.input();
//! #[hdl]
//! let my_register: UInt<8> = m.reg_builder().clock_domain(cd).reset(8_hdl_u8);
//! let my_wire: UInt<8> = m.wire();
//! #[hdl]
//! if v {
//! // my_register is only changed when both `v` is set and `cd`'s clock edge occurs.
//! m.connect(my_register, 0x45_hdl_u8);
//! m.connect(my_wire, 0x45_hdl_u8);
//! } else {
//! // wires must be connected to under all conditions
//! m.connect(my_wire, 0x23_hdl_u8);
//! }
//! # }
//! ```