diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
index 882c342..532ea21 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
@@ -15,13 +15,13 @@
 //! # #[hdl]
 //! # let v: UInt<1> = m.input();
 //! #[hdl]
-//! let cd: ClockDomain = m.input();
-//! #[hdl]
-//! let my_register: UInt<8> = m.reg_builder().clock_domain(cd).reset(8_hdl_u8);
+//! let my_wire: UInt<8> = m.wire();
 //! #[hdl]
 //! if v {
-//!     // my_register is only changed when both `v` is set and `cd`'s clock edge occurs.
-//!     m.connect(my_register, 0x45_hdl_u8);
+//!     m.connect(my_wire, 0x45_hdl_u8);
+//! } else {
+//!     // wires must be connected to under all conditions
+//!     m.connect(my_wire, 0x23_hdl_u8);
 //! }
 //! # }
 //! ```