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fetch.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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main_memory_and_io.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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memory_interface_adapter_no_split.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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next_pc.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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receiver_and_uart_clock_gen.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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receiver_no_queue_and_uart_clock_gen.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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reg_alloc.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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rename_execute_retire_fibonacci_combinatorial.vcd
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add GlobalState to ExecuteToUnitInterface
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2026-05-24 19:56:14 -07:00 |
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rename_execute_retire_fibonacci_non_combinatorial.vcd
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add GlobalState to ExecuteToUnitInterface
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2026-05-24 19:56:14 -07:00 |
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rename_execute_retire_fibonacci_real.vcd
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unit::alu_branch::add_sub: bug fix: actually add in carry_in
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2026-06-17 20:32:30 -07:00 |
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rename_execute_retire_head_n1.vcd
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redo ShiftRotateMOp and write actual operation definition in doc comment
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2026-05-28 01:41:31 -07:00 |
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rename_execute_retire_head_n1_real.vcd
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unit::alu_branch::add_sub: bug fix: actually add in carry_in
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2026-06-17 20:32:30 -07:00 |
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rename_execute_retire_save_restore_gprs.vcd
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add GlobalState to ExecuteToUnitInterface
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2026-05-24 19:56:14 -07:00 |
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rename_execute_retire_save_restore_gprs_real.vcd
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unit::alu_branch::add_sub: bug fix: actually add in carry_in
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2026-06-17 20:32:30 -07:00 |
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rename_execute_retire_slow_loop.vcd
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add GlobalState to ExecuteToUnitInterface
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2026-05-24 19:56:14 -07:00 |
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rename_execute_retire_slow_loop_real.vcd
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unit::alu_branch::add_sub: bug fix: actually add in carry_in
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2026-06-17 20:32:30 -07:00 |
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simple_uart.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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transmitter_and_uart_clock_gen.vcd
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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
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2026-03-26 19:21:52 -07:00 |
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units_formal_power_isa_add_sim.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_add_sub_sim_0.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_add_sub_sim_1.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_add_sub_sim_2.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_add_sub_sim_3.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_add_sub_sim_4.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_add_sub_sim_5.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
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units_formal_power_isa_paddi_sim.vcd
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tests/units_formal: implement tests for rest of AddSub[I] instructions
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2026-06-18 20:09:55 -07:00 |
