| .. |
|
fetch.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
main_memory_and_io.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
memory_interface_adapter_no_split.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
next_pc.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
receiver_and_uart_clock_gen.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
receiver_no_queue_and_uart_clock_gen.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
reg_alloc.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
rename_execute_retire_fibonacci_combinatorial.vcd
|
add GlobalState to ExecuteToUnitInterface
|
2026-05-24 19:56:14 -07:00 |
|
rename_execute_retire_fibonacci_non_combinatorial.vcd
|
add GlobalState to ExecuteToUnitInterface
|
2026-05-24 19:56:14 -07:00 |
|
rename_execute_retire_fibonacci_real.vcd
|
unit::alu_branch::compare: implement CmpRBOne/CmpRBTwo/CmpEqB
|
2026-05-28 19:12:41 -07:00 |
|
rename_execute_retire_head_n1.vcd
|
redo ShiftRotateMOp and write actual operation definition in doc comment
|
2026-05-28 01:41:31 -07:00 |
|
rename_execute_retire_head_n1_real.vcd
|
unit::alu_branch::compare: implement CmpRBOne/CmpRBTwo/CmpEqB
|
2026-05-28 19:12:41 -07:00 |
|
rename_execute_retire_save_restore_gprs.vcd
|
add GlobalState to ExecuteToUnitInterface
|
2026-05-24 19:56:14 -07:00 |
|
rename_execute_retire_save_restore_gprs_real.vcd
|
unit::alu_branch::compare: implement CmpRBOne/CmpRBTwo/CmpEqB
|
2026-05-28 19:12:41 -07:00 |
|
rename_execute_retire_slow_loop.vcd
|
add GlobalState to ExecuteToUnitInterface
|
2026-05-24 19:56:14 -07:00 |
|
rename_execute_retire_slow_loop_real.vcd
|
unit::alu_branch::compare: implement CmpRBOne/CmpRBTwo/CmpEqB
|
2026-05-28 19:12:41 -07:00 |
|
simple_uart.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
|
transmitter_and_uart_clock_gen.vcd
|
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
|
2026-03-26 19:21:52 -07:00 |
