implement "Create the next-instruction logic" and "Create a model of the instruction fetch/decode control system" #5
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This adds all the logic for running the fetch/decode and branch prediction stuff, except that the actual memory fetches and instruction decoding pipe isn't part of this set of tasks.
This uses 3 different predictors:
It has interfaces to the input and output of the fetch/decode pipe and also has an interface to the rename/dispatch/execute/retire logic to feed instructions in and get retired instructions out, handling any cancels generated.
It supports superscalar instruction fetch, though it is currently limited to one branch per cycle.
the test uses a fetch block size of 8 bytes and a maximum throughput of 2 instructions per cycle.
It also has the logic needed to clear the state on reset, not depending on FPGAs being able to initialize SRAM on startup.
I have it running a simple recursive-descent expression parser as a non-trivial demo program that has calls and branches and conditional branches.
It can very much use more optimization, but implementing this has taken much longer than planned, so now that the tests pass and everything works I think this is good enough for now and more optimization can be done at some later point.
Fixes: libre-chip/grant-tracking#13
Fixes: libre-chip/grant-tracking#10
WIP: implement "Create the next-instruction logic" and "Create a model of the instruction fetch/decode control system"to implement "Create the next-instruction logic" and "Create a model of the instruction fetch/decode control system"