libre-chip/cpu
3
0
Fork 2
Code Issues 1 Pull requests Projects Releases Packages Wiki Activity Actions

add link to other NLnet task and note lack of optimization
Some checks failed
/ test (pull_request) Has been cancelled
Details

Browse source
This commit is contained in:
Jacob Lifshay 2025-12-16 23:10:07 -08:00
parent d5a7d9dd9e
commit 2de4a67360
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 5 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

6
crates/cpu/src/next_pc.rs
View file

@ -1,7 +1,11 @@
// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
//! [Next-Instruction Logic](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10)
//! Next-Instruction Logic and Instruction Fetch/Decode Control System
//! [#10](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10)
//! and [#13](https://git.libre-chip.org/libre-chip/grant-tracking/issues/13).
//!
//! This could use a lot more optimization, but it works AFAIK.
//!
//! The basic idea here is that there's a `next_pc` stage that sends predicted fetch PCs to the `fetch` stage,
//! the `fetch` stage's outputs eventually end up in the `decode` stage,