|
|
151683fbda
|
rename_execute_retire: add reference counting for L1 registers
/ test (pull_request) Successful in 6m28s
/ test (push) Successful in 7m18s
|
2026-05-21 23:41:11 -07:00 |
|
|
|
e0dc5d486b
|
rename_execute_retire: add reference counting for L2 registers
/ test (pull_request) Successful in 6m2s
|
2026-05-21 21:06:40 -07:00 |
|
|
|
fdf1e97e10
|
move RenameTable and ReorderBuffer into their own mods
|
2026-05-21 20:46:19 -07:00 |
|
|
|
bf2cb688c7
|
implement register fences and use for L2 reg file writes and when running out of L2 reg file output regs
/ test (pull_request) Successful in 6m25s
fixes deadlock when running rename_execute_retire_save_restore_gprs
|
2026-05-21 17:23:57 -07:00 |
|
|
|
3e08a282ec
|
add test_rename_execute_retire_save_restore_gprs
currently it fails due to the L2 reg file running out of output registers
|
2026-05-20 19:44:20 -07:00 |
|
|
|
6026df8d7a
|
rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput
/ test (pull_request) Successful in 5m45s
|
2026-05-20 17:02:34 -07:00 |
|
|
|
e502dfe574
|
rename_execute_retire: don't include completed instructions in space used by a unit
|
2026-05-20 16:56:58 -07:00 |
|
|
|
0d69666b00
|
tests/rename_execute_retire: add and use mock_combinational_unit
/ test (pull_request) Successful in 6m18s
|
2026-05-19 19:33:09 -07:00 |
|
|
|
2363e65564
|
tests/rename_execute_retire: make loads/stores take more than one cycle to execute
/ test (pull_request) Successful in 6m19s
|
2026-05-19 18:08:07 -07:00 |
|
|
|
79ac190093
|
rename_execute_retire: add a head -n1 test
/ test (pull_request) Successful in 9m24s
|
2026-05-18 22:22:31 -07:00 |
|
|
|
0d3c41fa14
|
add TraceAsString around instructions and stuff to make the .vcd files much smaller and easier to read
/ test (pull_request) Successful in 5m44s
|
2026-05-14 22:38:50 -07:00 |
|
|
|
8bee576a2a
|
update fayalite to get TraceAsString
|
2026-05-14 22:28:25 -07:00 |
|
|
|
3fbdab0862
|
rename_execute_retire: implement generating L2 reg file writes
/ test (pull_request) Successful in 12m13s
|
2026-05-10 23:39:02 -07:00 |
|
|
|
33b5d59507
|
improve debug formatting of PRegValue and PRegFlags
|
2026-05-07 21:40:23 -07:00 |
|
|
|
559e2967a2
|
improve debug formatting of MOpRegNum/MOpDestReg
|
2026-05-07 21:25:27 -07:00 |
|
|
|
5e6041a97c
|
change MOp to use SrcReg: Type instead of UIntType<SrcRegWidth>
|
2026-05-07 19:56:56 -07:00 |
|
|
|
409ca7bf97
|
update decode_one_insn.vcd for modified instruction data structures
/ test (pull_request) Successful in 5m13s
|
2026-05-05 21:52:02 -07:00 |
|
|
|
9308e5d195
|
update fayalite to fix bug in VCD generation
/ test (pull_request) Failing after 5m12s
|
2026-05-05 21:28:46 -07:00 |
|
|
|
09c8c194e0
|
group micro ops by the instruction they come from when retiring
/ test (pull_request) Failing after 3m56s
|
2026-05-05 19:33:25 -07:00 |
|
|
|
83b3f7bac9
|
use custom debug
/ test (pull_request) Failing after 3m57s
|
2026-05-03 23:35:19 -07:00 |
|
|
|
ba9ec3bd29
|
adapt code for new fayalite features
|
2026-05-03 23:35:19 -07:00 |
|
|
|
1229d9c758
|
update fayalite for optimizations and new features
|
2026-05-03 23:35:19 -07:00 |
|
|
|
283117d8df
|
add support for speculative loads
/ test (pull_request) Failing after 9m18s
|
2026-04-30 17:51:33 -07:00 |
|
|
|
4d21ca622b
|
add initial impl of rename_execute_retire; running a recursive fibonacci gives the correct output
/ test (pull_request) Failing after 12m14s
|
2026-04-24 18:13:27 -07:00 |
|
