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0433e4f8f1
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mark .vcd files as generated
/ test (pull_request) Successful in 27m0s
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2026-01-20 16:20:40 -08:00 |
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a93dca25ac
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extract lut out into separate Lut4 type and add test
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2026-01-20 16:03:28 -08:00 |
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85ada6e55a
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add tests for and fix decoding branch instructions
/ test (pull_request) Successful in 27m1s
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2026-01-19 22:38:48 -08:00 |
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2e05329c36
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add branch instructions, no tests yet
/ test (pull_request) Successful in 27m31s
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2026-01-19 20:09:21 -08:00 |
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1fc56e02f9
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decode exts[bhw][.] and pnop
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2026-01-19 15:41:56 -08:00 |
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aa85ecab01
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simplify tests/simple_power_isa_decoder::test_cases somewhat
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2026-01-19 14:16:00 -08:00 |
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62a330ed4d
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update reg_alloc.vcd
/ test (pull_request) Successful in 27m28s
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2026-01-18 23:23:54 -08:00 |
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c9a3de19b7
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add test that UnitMOp has all the register fields aligned across the different variants
/ test (pull_request) Failing after 27m1s
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2026-01-18 22:50:38 -08:00 |
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7ebcd5de1e
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decode bitwise logic instructions; also nop and mr special cases
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2026-01-18 19:12:48 -08:00 |
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3a35a698e2
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decode fixed-point compare instructions
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2026-01-18 16:37:00 -08:00 |
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a4b052f5f3
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decode all fixed-point add/sub instructions other than addex
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2026-01-18 15:02:15 -08:00 |
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62512960c3
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decode some more add instructions
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2026-01-15 16:10:03 -08:00 |
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b7b6a02777
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decodes an addi instruction
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2026-01-14 21:41:25 -08:00 |
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6d40eaadb3
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WIP adding simple power isa decoder
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2026-01-12 07:10:58 -08:00 |
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305d7b0ae6
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rename src/powerisa.rs -> src/powerisa_instructions_xml.rs
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2026-01-12 03:31:06 -08:00 |
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781dbc6bcb
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add copyright header to build.rs
/ test (pull_request) Successful in 26m24s
/ test (push) Successful in 27m21s
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2026-01-09 02:05:08 -08:00 |
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5faf0899a8
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fully parse powerisa-instructions.xml
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2026-01-09 02:03:59 -08:00 |
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8c02483b65
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wip parsing the xml
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2026-01-08 00:09:20 -08:00 |
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e4a7d9f59c
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add build script that parses the PowerISA v3.1C pdf and produces an xml file
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2026-01-07 14:19:46 -08:00 |
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3b5104c8fa
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fix vcd to match test output
/ test (pull_request) Successful in 27m4s
/ test (push) Successful in 26m56s
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2025-12-16 23:25:54 -08:00 |
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2de4a67360
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add link to other NLnet task and note lack of optimization
/ test (pull_request) Has been cancelled
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2025-12-16 23:10:07 -08:00 |
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d5a7d9dd9e
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next_pc works afaict
/ test (pull_request) Has been cancelled
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2025-12-16 23:06:32 -08:00 |
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59da0aec06
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WIP fixing bugs
/ test (pull_request) Failing after 18m46s
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2025-12-16 02:32:19 -08:00 |
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5e1238b5c7
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replace tests/next_pc's demo program with a simple expression parser as a better demo
/ test (pull_request) Failing after 18m22s
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2025-12-15 21:40:11 -08:00 |
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bc9a3a5ce7
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add missing copyright header and check-copyright.sh support for .mermaid
/ test (pull_request) Failing after 18m42s
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2025-12-15 03:00:37 -08:00 |
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d42f010cda
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WIP fixing bugs
/ test (pull_request) Failing after 14s
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2025-12-15 02:48:40 -08:00 |
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84e4fde512
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fix queueing errors
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2025-12-15 00:47:53 -08:00 |
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8ab63f3c6a
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update fayalite
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2025-12-14 21:05:59 -08:00 |
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f39f40ce1f
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fix next_pc::Queue and add test
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2025-12-14 20:39:15 -08:00 |
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cbd52c60a8
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WIP: next_pc test fails
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2025-12-14 01:26:18 -08:00 |
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c87a1b8e1e
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wrote out all of next_pc and tests/next_pc
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2025-12-13 22:42:34 -08:00 |
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cfd04469ce
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WIP linking next_pc stages together
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2025-12-10 20:31:04 -08:00 |
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231f5e72ec
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WIP: completed stages of next-pc logic, still need to combine them into a pipeline
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2025-12-10 20:31:04 -08:00 |
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033d5d4f34
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WIP adding next_pc: add call stack
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2025-12-10 20:31:04 -08:00 |
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7a77c02cda
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WIP adding next_pc: added mock_fetch_decode_pipe
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2025-12-10 20:31:04 -08:00 |
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61d52bd028
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add Serialize/Deserialize impls for CpuConfig
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2025-12-10 20:31:04 -08:00 |
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554238c544
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update for new fayalite
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2025-12-10 20:31:04 -08:00 |
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24d6537ffe
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update Fayalite to get new features and bug fixes
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2025-12-10 20:31:04 -08:00 |
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c30bd0737f
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add readme
/ test (pull_request) Successful in 18m8s
/ test (push) Successful in 18m21s
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2025-10-24 16:36:31 -07:00 |
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291ad59b02
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update CI to use new fayalite-deps container
/ test (pull_request) Successful in 19m18s
/ test (push) Successful in 18m58s
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2025-10-24 02:54:03 -07:00 |
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5e8bc3e580
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upgrade to Fayalite edcc5927a5f9ebca6
as part of this I switched to using Fayalite's UIntInRangeInclusive instead of using a custom Length struct
|
2025-10-24 02:53:35 -07:00 |
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0e7a518bd0
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switch to use server's new actions org
/ deps (pull_request) Successful in 11m46s
/ test (pull_request) Successful in 27m48s
/ deps (push) Successful in 12s
/ test (push) Successful in 27m13s
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2025-10-10 00:03:53 -07:00 |
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00ddd602c5
|
format code
/ deps (push) Successful in 14s
/ test (push) Successful in 26m32s
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2025-08-24 19:08:58 -07:00 |
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b969249f5f
|
switch to edition 2024
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2025-08-24 19:07:53 -07:00 |
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aa50ae543e
|
upgrade to rust 1.89.0
|
2025-08-24 19:06:01 -07:00 |
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7de7d5435a
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make forgejo actions actually run
/ deps (push) Successful in 11m48s
/ test (push) Has been cancelled
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2025-08-24 18:50:33 -07:00 |
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60341e22af
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WIP: add ArrayVec
/ deps (push) Successful in 11m46s
/ test (push) Successful in 29m15s
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2025-03-04 00:20:33 -08:00 |
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2cfd54ba88
|
update fayalite to latest git
/ deps (push) Successful in 15s
/ test (push) Successful in 27m12s
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2025-03-03 22:00:11 -08:00 |
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ca3bcd7df2
|
switch CI to use mirrors
/ deps (push) Successful in 11m34s
/ test (push) Successful in 27m44s
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2025-03-02 18:04:09 -08:00 |
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518284685f
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UnitMOp now has L2RegisterFileMOp after renaming and instead has MoveRegMOp before renaming
/ deps (push) Successful in 16s
/ test (push) Successful in 25m54s
|
2025-02-28 17:45:46 -08:00 |
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