|  | 11ddbc43c7 | writing VCD for combinatorial circuits works! | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | c4b5d00419 | WIP adding VCD output | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 09aa9fbc78 | wire up simulator trace writing interface | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 288a6b71b9 | WIP adding VCD output | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 0095570f19 | simple combinatorial simulation works! | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | f54e55a143 | Simulation::settle_step() works for simple modules | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | a6e40839ac | simulator WIP: use petgraph for topological sort over assignments | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 3106a6fff6 | working on simulator... | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | f338f37d3e | working on simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 277d3e0d4d | working on simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | b288d6f8f2 | add missing copyright headers | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 479d59b287 | WIP implementing simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 6f904148c4 | WIP adding simulator | 2024-11-20 22:53:54 -08:00 |  | 
				
					
						|  | 3ea0d98924 | always write formal cache json | 2024-11-20 22:51:40 -08:00 |  | 
				
					
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									 Cesar Strauss | c1f1a8b749 | Add test module exercising formal verification. | 2024-11-20 18:29:39 -03:00 |  | 
				
					
						|  | ee15fd2b94 | support #[hdl] type aliases | 2024-10-30 20:47:10 -07:00 |  | 
				
					
						|  | 20cf0abbcc | fix using #[hdl] types like S<{ 1 + 2 }> | 2024-10-30 20:46:11 -07:00 |  | 
				
					
						|  | cb17913004 | limit sby to one thread each since it seems not to respect job count in parallel mode | 2024-10-15 21:32:38 -07:00 |  | 
				
					
						|  | 42effd1132 | switch to using a make job server for managing test parallelism | 2024-10-15 20:32:33 -07:00 |  | 
				
					
						|  | 3d0f95cfe5 | formal: add workaround for wires disappearing because yosys optimizes them out | 2024-10-15 01:48:48 -07:00 |  | 
				
					
						|  | 3939ce2360 | add Bundle and Enum to prelude | 2024-10-14 17:47:58 -07:00 |  | 
				
					
						|  | d0229fbcfb | get #[hdl] struct S<A: KnownSize, B: KnownSize> to work | 2024-10-11 17:30:49 -07:00 |  | 
				
					
						|  | 4909724995 | add more thorough checks that bounds are properly handled on #[hdl] structs | 2024-10-10 23:34:46 -07:00 |  | 
				
					
						|  | d0694cbd52 | add disabled test for #[hdl] struct S4<W: KnownSize, W2: KnownSize> which type errors | 2024-10-10 22:58:15 -07:00 |  | 
				
					
						|  | 1a2149b040 | silence warnings for field names that start with _ | 2024-10-10 20:53:29 -07:00 |  | 
				
					
						|  | 59cef3f398 | add PhantomData as a hdl bundle | 2024-10-10 20:48:09 -07:00 |  | 
				
					
						|  | bf907c3872 | cache results of formal proofs | 2024-10-07 23:31:24 -07:00 |  | 
				
					
						|  | 99180eb3b4 | fix clippy lints in generated code | 2024-10-07 22:06:59 -07:00 |  | 
				
					
						|  | 017c14a2f1 | don't use #[allow(..., reason = "...")] since that's not stable yet on rust 1.80.1 | 2024-10-07 22:06:59 -07:00 |  | 
				
					
						|  | ed1aea41f3 | clean up some clippy warnings | 2024-10-07 21:49:18 -07:00 |  | 
				
					
						|  | f12322aa2a | remove interning contexts | 2024-10-07 21:33:56 -07:00 |  | 
				
					
						|  | 44ca1a607a | remove unused AGCContext | 2024-10-07 21:23:13 -07:00 |  | 
				
					
						|  | 30b9a5e48d | change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created | 2024-10-07 19:06:01 -07:00 |  | 
				
					
						|  | eed0afc6ab | add some utility From<Interned<T>> impls | 2024-10-07 19:05:20 -07:00 |  | 
				
					
						|  | 2e8b73d2fc | rename fire/fire_data to firing/firing_data | 2024-10-06 19:04:48 -07:00 |  | 
				
					
						|  | e05c368688 | change register names to end in _regby convention | 2024-10-06 18:50:09 -07:00 |  | 
				
					
						|  | b7f1101164 | reduce parallelism to fit within the number of available cpus even when running sby in prove mode (which likes to run 2 smt solvers in parallel) | 2024-10-04 17:03:51 -07:00 |  | 
				
					
						|  | 0d54b9a2a9 | queue formal proof passes! | 2024-10-03 23:07:14 -07:00 |  | 
				
					
						|  | 343805f80b | fix #[hdl] to work with unusual identifier hygiene from macros | 2024-10-03 23:04:14 -07:00 |  | 
				
					
						|  | 4084a70485 | switch default solver to z3 | 2024-10-03 01:43:46 -07:00 |  | 
				
					
						|  | 3e2fb9b94f | WIP getting queue formal to pass -- passes for capacity <= 2 | 2024-10-03 01:08:01 -07:00 |  | 
				
					
						|  | 0cf01600b3 | add mod formal and move assert/assume/cover stuff to it | 2024-10-01 19:56:17 -07:00 |  | 
				
					
						|  | f3d6528f5b | make annotations easier to use | 2024-10-01 19:54:17 -07:00 |  | 
				
					
						|  | f35d88d2bb | remove unused valueless.rs | 2024-10-01 18:41:41 -07:00 |  | 
				
					
						|  | e8c393f3bb | sort pub mod items | 2024-10-01 18:40:52 -07:00 |  | 
				
					
						|  | d0b406d288 | add more annotation kinds | 2024-10-01 18:33:32 -07:00 |  | 
				
					
						|  | 2a25dd9d7b | fix annotations getting lost | 2024-10-01 18:31:44 -07:00 |  | 
				
					
						|  | 6e0b6c000d | remove stray debugging prints | 2024-10-01 18:30:46 -07:00 |  | 
				
					
						|  | d089095667 | change default to --simplify-enums=replace-with-bundle-of-uints | 2024-10-01 00:07:48 -07:00 |  | 
				
					
						|  | 9d66fcc548 | improve ExportOptions support in assert_export_firrtl! | 2024-10-01 00:05:39 -07:00 |  |