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formal: add workaround for wires disappearing because yosys optimizes them out

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This commit is contained in:
Jacob Lifshay 2024-10-15 01:48:48 -07:00
parent 3939ce2360
commit 3d0f95cfe5
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
1 changed files with 5 additions and 1 deletions
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6
crates/fayalite/src/cli.rs
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@ -687,7 +687,11 @@ impl FormalArgs {
}
writeln!(retval, "read_verilog -sv -formal \"{verilog_file}\"").unwrap();
}
writeln!(retval, "prep -top {top_module}").unwrap();
// workaround for wires disappearing -- set `keep` on all wires
writeln!(retval, "hierarchy -top {top_module}").unwrap();
writeln!(retval, "proc").unwrap();
writeln!(retval, "setattr -set keep 1 w:\\*").unwrap();
writeln!(retval, "prep").unwrap();
Ok(retval)
}
fn run_impl(