forked from libre-chip/fayalite
queue formal proof passes!
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SSH key fingerprint:
SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
6 changed files with 183 additions and 86 deletions
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@ -516,7 +516,7 @@ impl FormalArgs {
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std::fs::write(&sby_file, self.sby_contents(&output)?)?;
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let mut cmd = process::Command::new(&self.sby);
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cmd.arg("-f");
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cmd.arg(sby_file);
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cmd.arg(sby_file.file_name().unwrap());
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cmd.args(&self.sby_extra_args);
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cmd.current_dir(&output.verilog.firrtl.output_dir);
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let status = self.verilog.firrtl.base.run_external_command(cmd)?;
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@ -1,7 +1,8 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use crate::{
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intern::{Intern, Interned},
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int::BoolOrIntType,
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intern::{Intern, Interned, Memoize},
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prelude::*,
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};
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use std::sync::OnceLock;
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@ -172,12 +173,7 @@ pub fn formal_reset() -> Expr<SyncReset> {
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m.annotate_module(BlackBoxInlineAnnotation {
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path: "fayalite_formal_reset.v".intern(),
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text: r"module __fayalite_formal_reset(output rst);
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reg rst;
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(* gclk *)
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reg gclk;
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initial rst = 1;
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always @(posedge gclk)
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rst <= 0;
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assign rst = $initstate;
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endmodule
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"
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.intern(),
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@ -189,3 +185,63 @@ endmodule
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let formal_reset = instance(*MOD.get_or_init(formal_reset));
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formal_reset.rst
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}
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macro_rules! make_any_const_fn {
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($ident:ident, $verilog_attribute:literal) => {
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#[hdl]
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pub fn $ident<T: BoolOrIntType>(ty: T) -> Expr<T> {
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#[hdl_module(extern)]
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pub(super) fn $ident<T: BoolOrIntType>(ty: T) {
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#[hdl]
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let out: T = m.output(ty);
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let width = ty.width();
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let verilog_bitslice = if width == 1 {
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String::new()
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} else {
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format!(" [{}:0]", width - 1)
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};
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m.annotate_module(BlackBoxInlineAnnotation {
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path: Intern::intern_owned(format!(
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"fayalite_{}_{width}.v",
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stringify!($ident),
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)),
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text: Intern::intern_owned(format!(
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r"module __fayalite_{}_{width}(output{verilog_bitslice} out);
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(* {} *)
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reg{verilog_bitslice} out;
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endmodule
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",
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stringify!($ident),
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$verilog_attribute,
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)),
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});
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m.verilog_name(format!("__fayalite_{}_{width}", stringify!($ident)));
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}
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#[derive(Copy, Clone, PartialEq, Eq, Hash)]
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struct TheMemoize<T>(T);
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impl<T: BoolOrIntType> Memoize for TheMemoize<T> {
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type Input = ();
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type InputOwned = ();
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type Output = Option<Interned<Module<$ident<T>>>>;
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fn inner(self, _input: &Self::Input) -> Self::Output {
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if self.0.width() == 0 {
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None
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} else {
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Some($ident(self.0))
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}
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}
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}
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let Some(module) = TheMemoize(ty).get_owned(()) else {
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return 0_hdl_u0.cast_bits_to(ty);
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};
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#[hdl]
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let $ident = instance(module);
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$ident.out
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}
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};
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}
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make_any_const_fn!(any_const, "anyconst");
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make_any_const_fn!(any_seq, "anyseq");
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make_any_const_fn!(all_const, "allconst");
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make_any_const_fn!(all_seq, "allseq");
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@ -14,8 +14,9 @@ pub use crate::{
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ReduceBits, ToExpr,
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},
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formal::{
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formal_global_clock, formal_reset, hdl_assert, hdl_assert_with_enable, hdl_assume,
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hdl_assume_with_enable, hdl_cover, hdl_cover_with_enable, MakeFormalExpr,
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all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, hdl_assert,
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hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover,
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hdl_cover_with_enable, MakeFormalExpr,
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},
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hdl, hdl_module,
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int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
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@ -68,7 +68,6 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
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},
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);
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let mut dir = String::with_capacity(64);
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write!(dir, "{simple_hash:08x}-").unwrap();
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for ch in Path::new(file)
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.file_stem()
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.unwrap_or_default()
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@ -84,6 +83,7 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
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_ => '_',
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});
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}
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write!(dir, "-{simple_hash:08x}").unwrap();
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let index = *DIRS
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.lock()
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.unwrap()
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@ -91,7 +91,7 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
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.entry_ref(&dir)
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.and_modify(|v| *v += 1)
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.or_insert(0);
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write!(dir, ".{index}").unwrap();
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write!(dir, "-{index}").unwrap();
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get_cargo_target_dir()
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.join("fayalite_assert_formal")
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.join(dir)
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@ -49,7 +49,6 @@ impl<T: Type> ReadyValid<T> {
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}
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}
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// TODO: needs testing
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#[hdl_module]
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pub fn queue<T: Type>(
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ty: T,
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@ -134,7 +133,7 @@ pub fn queue<T: Type>(
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#[hdl]
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if inp_fire {
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#[hdl]
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if inp_index.cmp_eq(capacity) {
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if inp_index.cmp_eq(capacity.get() - 1) {
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connect_any(inp_index, 0_hdl_u0);
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} else {
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connect_any(inp_index, inp_index + 1_hdl_u1);
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@ -144,7 +143,7 @@ pub fn queue<T: Type>(
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#[hdl]
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if out_fire {
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#[hdl]
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if out_index.cmp_eq(capacity) {
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if out_index.cmp_eq(capacity.get() - 1) {
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connect_any(out_index, 0_hdl_u0);
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} else {
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connect_any(out_index, out_index + 1_hdl_u1);
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@ -153,10 +152,12 @@ pub fn queue<T: Type>(
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#[hdl]
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if indexes_equal {
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connect(
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count,
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maybe_full.cast_to_static::<UInt<1>>() << (count_ty.width() - 1),
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);
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#[hdl]
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if maybe_full {
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connect_any(count, capacity);
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} else {
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connect_any(count, 0_hdl_u0);
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}
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} else {
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if capacity.is_power_of_two() {
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debug_assert_eq!(count_ty.width(), index_ty.width() + 1);
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@ -182,6 +183,7 @@ mod tests {
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use crate::{
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cli::FormalMode, firrtl::ExportOptions,
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module::transform::simplify_enums::SimplifyEnumsKind, testing::assert_formal,
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ty::StaticType,
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};
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use std::num::NonZero;
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@ -190,8 +192,8 @@ mod tests {
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assert_formal(
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format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
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queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
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FormalMode::BMC,
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20,
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FormalMode::Prove,
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14,
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None,
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ExportOptions {
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simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
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@ -200,12 +202,6 @@ mod tests {
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);
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#[hdl_module]
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fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
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#[hdl]
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let inp_data: HdlOption<UInt<8>> = m.input();
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#[hdl]
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let out_ready: Bool = m.input();
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#[hdl]
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let start_check: Bool = m.input();
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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@ -219,6 +215,24 @@ mod tests {
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},
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);
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#[hdl]
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let inp_data: HdlOption<UInt<8>> = wire();
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#[hdl]
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if any_seq(Bool) {
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connect(inp_data, HdlSome(any_seq(UInt::<8>::TYPE)));
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} else {
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connect(inp_data, HdlNone());
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}
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#[hdl]
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let out_ready: Bool = wire();
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connect(out_ready, any_seq(Bool));
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let index_ty: UInt<32> = UInt::TYPE;
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#[hdl]
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let index_to_check = wire();
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connect(index_to_check, any_const(index_ty));
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let index_max = !index_ty.zero();
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// we saturate at index_max, so only check indexes where we properly maintain position
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hdl_assume(clk, index_to_check.cmp_ne(index_max), "");
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#[hdl]
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let dut = instance(queue(
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UInt[ConstUsize::<8>],
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capacity,
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@ -228,63 +242,97 @@ mod tests {
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connect(dut.cd, cd);
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connect(dut.inp.data, inp_data);
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connect(dut.out.ready, out_ready);
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hdl_assume(
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clk,
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index_to_check.cmp_ne(!Expr::ty(index_to_check).zero()),
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"",
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);
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#[hdl]
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let count = reg_builder().clock_domain(cd).reset(0u32);
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let expected_count = reg_builder().clock_domain(cd).reset(0u32);
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#[hdl]
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let next_count = wire();
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connect(next_count, count);
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connect(count, next_count);
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let next_expected_count = wire();
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connect(next_expected_count, expected_count);
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connect(expected_count, next_expected_count);
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#[hdl]
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if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
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connect_any(next_count, count + 1u8);
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connect_any(next_expected_count, expected_count + 1u8);
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} else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
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connect_any(next_count, count - 1u8);
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connect_any(next_expected_count, expected_count - 1u8);
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}
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hdl_assert(cd.clk, count.cmp_eq(dut.count), "");
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hdl_assert(cd.clk, expected_count.cmp_eq(dut.count), "");
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#[hdl]
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let started_check = reg_builder().clock_domain(cd).reset(false);
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let prev_out_ready = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
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connect_any(
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prev_out_ready,
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(prev_out_ready << 1) | out_ready.cast_to(UInt[1]),
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);
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#[hdl]
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let steps_till_output = reg_builder().clock_domain(cd).reset(0u32);
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let prev_inp_valid = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
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connect_any(
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prev_inp_valid,
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(prev_inp_valid << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
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);
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hdl_assume(clk, (prev_out_ready & prev_inp_valid).cmp_ne(0u8), "");
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#[hdl]
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let expected_output = reg_builder().clock_domain(cd).reset(HdlNone());
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let inp_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
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#[hdl]
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if start_check & !started_check {
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let stored_inp_data = reg_builder().clock_domain(cd).reset(0u8);
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#[hdl]
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if let HdlSome(data) = ReadyValid::fire_data(dut.inp) {
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#[hdl]
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if let HdlSome(inp) = ReadyValid::fire_data(dut.inp) {
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connect(started_check, true);
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connect_any(
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steps_till_output,
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count + (!ReadyValid::fire(dut.out)).cast_to(UInt[1]),
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);
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connect(expected_output, HdlSome(inp));
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}
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} else if started_check & steps_till_output.cmp_ne(0u32) & ReadyValid::fire(dut.out) {
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connect_any(steps_till_output, steps_till_output - 1u32);
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}
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#[hdl]
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let stored_output = reg_builder().clock_domain(cd).reset(HdlNone());
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#[hdl]
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if let HdlSome(out) = ReadyValid::fire_data(dut.out) {
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#[hdl]
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if (start_check & !started_check) | (started_check & steps_till_output.cmp_ne(0u32))
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{
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connect(stored_output, HdlSome(out));
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}
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}
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#[hdl]
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if started_check & steps_till_output.cmp_eq(0u32) {
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#[hdl]
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if let HdlSome(expected_output) = expected_output {
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if inp_index.cmp_lt(index_max) {
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connect_any(inp_index, inp_index + 1u8);
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#[hdl]
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if let HdlSome(stored_output) = stored_output {
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hdl_assert(cd.clk, stored_output.cmp_eq(expected_output), "");
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} else {
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hdl_assert(cd.clk, false.to_expr(), "");
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if inp_index.cmp_eq(index_to_check) {
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connect(stored_inp_data, data);
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}
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} else {
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hdl_assert(cd.clk, false.to_expr(), "");
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}
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}
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#[hdl]
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if inp_index.cmp_lt(index_to_check) {
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hdl_assert(clk, stored_inp_data.cmp_eq(0u8), "");
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}
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#[hdl]
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let out_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
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#[hdl]
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let stored_out_data = reg_builder().clock_domain(cd).reset(0u8);
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#[hdl]
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if let HdlSome(data) = ReadyValid::fire_data(dut.out) {
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#[hdl]
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if out_index.cmp_lt(index_max) {
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connect_any(out_index, out_index + 1u8);
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#[hdl]
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if out_index.cmp_eq(index_to_check) {
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connect(stored_out_data, data);
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}
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}
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}
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#[hdl]
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if out_index.cmp_lt(index_to_check) {
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hdl_assert(clk, stored_out_data.cmp_eq(0u8), "");
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}
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hdl_assert(clk, inp_index.cmp_ge(out_index), "");
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#[hdl]
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if inp_index.cmp_lt(index_max) & out_index.cmp_lt(index_max) {
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hdl_assert(clk, expected_count.cmp_eq(inp_index - out_index), "");
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} else {
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hdl_assert(clk, expected_count.cmp_ge(inp_index - out_index), "");
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}
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#[hdl]
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if inp_index.cmp_gt(index_to_check) & out_index.cmp_gt(index_to_check) {
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hdl_assert(clk, stored_inp_data.cmp_eq(stored_out_data), "");
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}
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}
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}
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@ -328,49 +376,41 @@ mod tests {
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test_queue(NonZero::new(2).unwrap(), true, true);
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}
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#[cfg(todo)]
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#[test]
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fn test_3_false_false() {
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test_queue(NonZero::new(3).unwrap(), false, false);
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}
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#[cfg(todo)]
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#[test]
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fn test_3_false_true() {
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test_queue(NonZero::new(3).unwrap(), false, true);
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}
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#[cfg(todo)]
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#[test]
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fn test_3_true_false() {
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test_queue(NonZero::new(3).unwrap(), true, false);
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}
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#[cfg(todo)]
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#[test]
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fn test_3_true_true() {
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test_queue(NonZero::new(3).unwrap(), true, true);
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}
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#[cfg(todo)]
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#[test]
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fn test_4_false_false() {
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test_queue(NonZero::new(4).unwrap(), false, false);
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}
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#[cfg(todo)]
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#[test]
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fn test_4_false_true() {
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test_queue(NonZero::new(4).unwrap(), false, true);
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}
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#[cfg(todo)]
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#[test]
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fn test_4_true_false() {
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test_queue(NonZero::new(4).unwrap(), true, false);
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}
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#[cfg(todo)]
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#[test]
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fn test_4_true_true() {
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test_queue(NonZero::new(4).unwrap(), true, true);
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|
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@ -3394,7 +3394,7 @@ circuit check_formal: %[[
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{
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"class": "firrtl.transforms.BlackBoxInlineAnno",
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"name": "fayalite_formal_reset.v",
|
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"text": "module __fayalite_formal_reset(output rst);\n reg rst;\n (* gclk *)\n reg gclk;\n initial rst = 1;\n always @(posedge gclk)\n rst <= 0;\nendmodule\n",
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"text": "module __fayalite_formal_reset(output rst);\n assign rst = $initstate;\nendmodule\n",
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"target": "~check_formal|formal_reset"
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}
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]]
|
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|
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@ -3407,20 +3407,20 @@ circuit check_formal: %[[
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input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
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input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
|
||||
input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
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inst formal_reset of formal_reset @[formal.rs 189:24]
|
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inst formal_reset of formal_reset @[formal.rs 185:24]
|
||||
assert(clk, pred1, and(en1, not(formal_reset.rst)), "en check 1") @[module-XXXXXXXXXX.rs 9:1]
|
||||
inst formal_reset_1 of formal_reset @[formal.rs 189:24]
|
||||
inst formal_reset_1 of formal_reset @[formal.rs 185:24]
|
||||
assume(clk, pred2, and(en2, not(formal_reset_1.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1]
|
||||
inst formal_reset_2 of formal_reset @[formal.rs 189:24]
|
||||
inst formal_reset_2 of formal_reset @[formal.rs 185:24]
|
||||
cover(clk, pred3, and(en3, not(formal_reset_2.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1]
|
||||
inst formal_reset_3 of formal_reset @[formal.rs 189:24]
|
||||
inst formal_reset_3 of formal_reset @[formal.rs 185:24]
|
||||
assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset_3.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1]
|
||||
inst formal_reset_4 of formal_reset @[formal.rs 189:24]
|
||||
inst formal_reset_4 of formal_reset @[formal.rs 185:24]
|
||||
assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset_4.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1]
|
||||
inst formal_reset_5 of formal_reset @[formal.rs 189:24]
|
||||
inst formal_reset_5 of formal_reset @[formal.rs 185:24]
|
||||
cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset_5.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1]
|
||||
extmodule formal_reset: @[formal.rs 168:5]
|
||||
output rst: UInt<1> @[formal.rs 171:32]
|
||||
extmodule formal_reset: @[formal.rs 169:5]
|
||||
output rst: UInt<1> @[formal.rs 172:32]
|
||||
defname = __fayalite_formal_reset
|
||||
"#,
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue