HaeckseAlex
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  • Joined on 2025-09-24
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HaeckseAlex created branch orangecrab2 in HaeckseAlex/fayalite 2026-05-24 19:08:24 +00:00
HaeckseAlex pushed to orangecrab2 at HaeckseAlex/fayalite 2026-05-24 19:08:24 +00:00
e0623c9b0f copy vendor/xilinx to vendor/lattice
cf3e6cfc6b Add .to_trace_as_string() and clean up code
ea183eac87 add TraceAsString<T> -- sim traces it as a string rather than all its internal fields
26224abe1c sim: properly update all VCD wires when they share simulation state
2266315944 redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue
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HaeckseAlex created branch tp/rebase2 in libre-chip/fayalite 2026-05-24 18:55:49 +00:00
HaeckseAlex pushed to tp/rebase2 at libre-chip/fayalite 2026-05-24 18:55:49 +00:00
fd2c635343 non-working build on TLII (using QEMU for x86 binaries)
34b4a57507 copy vendor/xilinx to vendor/lattice
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HaeckseAlex created branch tp/base in HaeckseAlex/fayalite 2026-04-21 16:22:42 +00:00
HaeckseAlex pushed to tp/base at HaeckseAlex/fayalite 2026-04-21 16:22:42 +00:00
HaeckseAlex created branch tp/backup in HaeckseAlex/fayalite 2026-04-21 16:22:37 +00:00
HaeckseAlex pushed to tp/backup at HaeckseAlex/fayalite 2026-04-21 16:22:37 +00:00
34b4a57507 copy vendor/xilinx to vendor/lattice
HaeckseAlex commented on issue libre-chip/grant-tracking#15 2026-03-02 21:21:42 +00:00
NLnet 2024-12-324 memory system: main memory and IO devices

I am currently working on the OranngeCrab task

HaeckseAlex pushed to orangecrab at HaeckseAlex/fayalite 2026-01-21 19:13:24 +00:00
9da113b53e remove XdcCreateClockAnnotation, XdcIOStandardAnnotation and XdcLocationAnnotation
HaeckseAlex pushed to orangecrab at HaeckseAlex/fayalite 2026-01-21 19:01:33 +00:00
ad5e7e29e9 copy vendor/xilinx to vendor/lattice
HaeckseAlex created branch orangecrab in HaeckseAlex/fayalite 2026-01-18 14:35:33 +00:00
HaeckseAlex pushed to orangecrab at HaeckseAlex/fayalite 2026-01-18 14:35:33 +00:00
HaeckseAlex pushed to master at HaeckseAlex/fayalite 2026-01-18 14:29:09 +00:00
3dd7b9b107 add lattice files
HaeckseAlex created repository HaeckseAlex/fayalite 2026-01-18 14:28:43 +00:00
259afa1fa9 add my paragraph
HaeckseAlex created repository HaeckseAlex/website 2025-11-30 10:17:55 +00:00
HaeckseAlex commented on pull request libre-chip/website#1 2025-11-30 09:31:42 +00:00
add grant proposal: Libre-Chip's CPU with a Programmable Decoder to Run Multiple ISAs at Full Speed

@programmerjake wrote in libre-chip/website#1 (comment):

@HaeckseAlex please do let us know if you're interested in participating in this next grant.

Yes, I am

HaeckseAlex pushed to main_memory_wip at HaeckseAlex/cpu 2025-10-19 08:26:51 +00:00
8433f4f150 increase memory bandwidth and size
HaeckseAlex pushed to main_memory_wip at HaeckseAlex/cpu 2025-10-14 18:11:43 +00:00
672a29e76d run cargo fmt on main_memory
35ea85d074 add write port
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