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add write port

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This commit is contained in:
Tobias Alexandra Platen 2025-10-14 20:08:29 +02:00
parent 1ead550d13
commit 35ea85d074
2 changed files with 30 additions and 0 deletions
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14
crates/cpu/src/main_memory.rs
View file

@ -29,6 +29,11 @@ pub fn main_memory(config: &CpuConfig) {
let read_data: UInt<8> = m.output();
#[hdl]
let en: Bool = m.input();
// add write support
#[hdl]
let write_en: Bool = m.input();
#[hdl]
let write_data: UInt<8> = m.input();
#[hdl]
let cd: ClockDomain = m.input();
@ -48,6 +53,15 @@ pub fn main_memory(config: &CpuConfig) {
connect(read_port.clk, cd.clk);
connect(read_data,read_port.data);
let write_port = my_memory.new_write_port();
connect_any(write_port.addr, addr);
connect_any(write_port.en, addr.cmp_lt(4u64) & write_en);
connect_any(write_port.data, write_data);
connect(write_port.clk, cd.clk);
//connect_any(write_port.mask, 0xFFu8); //try that one
connect_any(write_port.mask, true);

16
crates/cpu/tests/main_memory.rs
View file

@ -41,6 +41,8 @@ fn test_main_memory() {
sim.write(sim.io().en, true);
sim.write(sim.io().cd.rst, false);
sim.write(sim.io().cd.clk, false);
sim.write(sim.io().write_en, false);
sim.write(sim.io().write_data, 0xFFu8);
// TODO convert to for loop
// you need to write an initial value to all inputs before you can start running the simulation
@ -57,6 +59,20 @@ fn test_main_memory() {
sim.advance_time(SimDuration::from_micros(1));
}
sim.write(sim.io().write_en, true);
sim.write(sim.io().addr, 0u64);
sim.write(sim.io().write_data, 0x11u8);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 1u64);
sim.write(sim.io().write_data, 0x22u8);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 2u64);
sim.write(sim.io().write_data, 0x33u8);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 3u64);
sim.write(sim.io().write_data, 0x44u8);
sim.advance_time(SimDuration::from_micros(1));