Run Rocq tests.

this makes cpu/crates/cpu/tests/next_pc.rs take 56s instead of 168s

.forgejo/workflows/test.yml

@@ -16,6 +16,9 @@ jobs:
       - uses: https://git.libre-chip.org/mirrors/rust-cache@v2
         with:
           save-if: ${{ github.ref == 'refs/heads/master' }}
+      - run: rustup override set 1.93.0
+      - run: rustup component add rust-src
+      - run: make -C rocq-demo
       - run: cargo test
       - run: cargo build --tests --features=unstable-doc
       - run: cargo test --doc --features=unstable-doc

Cargo.lock

@@ -319,10 +319,12 @@ dependencies = [
  "jobslot",
  "num-bigint",
  "num-traits",
+ "once_cell",
  "ordered-float",
  "petgraph",
  "serde",
  "serde_json",
+ "sha2",
  "tempfile",
  "trybuild",
  "vec_map",
@@ -521,9 +523,9 @@ dependencies = [
 
 [[package]]
 name = "once_cell"
-version = "1.19.0"
+version = "1.21.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92"
+checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d"
 
 [[package]]
 name = "ordered-float"

Cargo.toml

@@ -11,7 +11,7 @@ edition = "2024"
 repository = "https://git.libre-chip.org/libre-chip/fayalite"
 keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"]
 categories = ["simulation", "development-tools", "compilers"]
-rust-version = "1.89.0"
+rust-version = "1.93.0"
 
 [workspace.dependencies]
 fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" }
@@ -30,6 +30,7 @@ indexmap = { version = "2.5.0", features = ["serde"] }
 jobslot = "0.2.23"
 num-bigint = "0.4.6"
 num-traits = "0.2.16"
+once_cell = "1.21.3"
 ordered-float = { version = "5.1.0", features = ["serde"] }
 petgraph = "0.8.1"
 prettyplease = "0.2.20"

crates/fayalite-proc-macros-impl/src/hdl_enum.rs

@@ -888,6 +888,7 @@ impl ToTokens for ParsedEnum {
                         #(#sim_value_from_opaque_match_arms)*
                     }
                 }
+                #[allow(irrefutable_let_patterns)]
                 fn sim_value_clone_from_opaque(
                     &self,
                     value: &mut <Self as ::fayalite::ty::Type>::SimValue,

crates/fayalite/Cargo.toml

@@ -26,10 +26,12 @@ hashbrown.workspace = true
 jobslot.workspace = true
 num-bigint.workspace = true
 num-traits.workspace = true
+once_cell.workspace = true
 ordered-float.workspace = true
 petgraph.workspace = true
 serde_json.workspace = true
 serde.workspace = true
+sha2.workspace = true
 tempfile.workspace = true
 vec_map.workspace = true
 which.workspace = true

crates/fayalite/src/array.rs

@@ -109,14 +109,42 @@ impl<T: StaticType, Len: KnownSize> Default for ArrayType<T, Len> {
     }
 }
 
+struct MakeType<T: StaticType>(Interned<T>);
+
+impl<T: StaticType> From<MakeType<T>> for Interned<T> {
+    fn from(value: MakeType<T>) -> Self {
+        value.0
+    }
+}
+
+impl<T: StaticType> Default for MakeType<T> {
+    fn default() -> Self {
+        Self(T::TYPE.intern_sized())
+    }
+}
+
+struct MakeMaskType<T: StaticType>(Interned<T::MaskType>);
+
+impl<T: StaticType> From<MakeMaskType<T>> for Interned<T::MaskType> {
+    fn from(value: MakeMaskType<T>) -> Self {
+        value.0
+    }
+}
+
+impl<T: StaticType> Default for MakeMaskType<T> {
+    fn default() -> Self {
+        Self(T::MASK_TYPE.intern_sized())
+    }
+}
+
 impl<T: StaticType, Len: KnownSize> StaticType for ArrayType<T, Len> {
     const TYPE: Self = Self {
-        element: LazyInterned::new_lazy(&|| T::TYPE.intern_sized()),
+        element: LazyInterned::new_const::<MakeType<T>>(),
         len: Len::SIZE,
         type_properties: Self::TYPE_PROPERTIES,
     };
     const MASK_TYPE: Self::MaskType = ArrayType::<T::MaskType, Len> {
-        element: LazyInterned::new_lazy(&|| T::MASK_TYPE.intern_sized()),
+        element: LazyInterned::new_const::<MakeMaskType<T>>(),
         len: Len::SIZE,
         type_properties: Self::MASK_TYPE_PROPERTIES,
     };

crates/fayalite/src/expr/ops.rs

@@ -579,6 +579,8 @@ macro_rules! make_impls {
     (#[kind(i64)] $($rest:tt)*) => {make_impls! { #[type([][] (i64))] $($rest)* }};
     (#[kind(i128)] $($rest:tt)*) => {make_impls! { #[type([][] (i128))] $($rest)* }};
 }
+
+#[cfg(test)]
 pub(crate) use make_impls;
 
 #[cfg(test)]

crates/fayalite/src/int.rs

@@ -10,7 +10,7 @@ use crate::{
         value_category::ValueCategoryValue,
     },
     hdl,
-    intern::{Intern, Interned, Memoize},
+    intern::{Intern, Interned, Memoize, OnceInterned},
     sim::value::{SimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{
@@ -65,14 +65,21 @@ pub type DynSize = ConstUsize<DYN_SIZE>;
 
 trait KnownSizeBaseSealed {}
 
-impl<const N: usize> KnownSizeBaseSealed for [(); N] {}
+impl<const N: usize> KnownSizeBaseSealed for ConstUsize<N> {}
 
 #[expect(private_bounds)]
-pub trait KnownSizeBase: KnownSizeBaseSealed {}
+pub trait KnownSizeBase: KnownSizeBaseSealed + GetInternedIntCaches {}
 
 macro_rules! impl_known_size_base {
     ($($size:literal),* $(,)?) => {
-        $(impl KnownSizeBase for [(); $size] {})*
+        $(impl KnownSizeBase for ConstUsize<$size> {})*
+        $(impl GetInternedIntCaches for ConstUsize<$size> {
+            #[inline(always)]
+            fn get_interned_int_caches() -> &'static InternedIntCaches<Self> {
+                static CACHES: InternedIntCaches<ConstUsize<$size>> = InternedIntCaches::new();
+                &CACHES
+            }
+        })*
     };
 }
 
@@ -113,12 +120,34 @@ impl_known_size_base! {
     0x200,
 }
 
+trait GetInternedIntCaches {
+    fn get_interned_int_caches() -> &'static InternedIntCaches<Self>
+    where
+        Self: KnownSize;
+}
+
+struct InternedIntCaches<Width: KnownSize> {
+    uint: OnceInterned<UIntType<Width>>,
+    sint: OnceInterned<SIntType<Width>>,
+}
+
+impl<Width: KnownSize> InternedIntCaches<Width> {
+    const fn new() -> Self {
+        Self {
+            uint: OnceInterned::new(),
+            sint: OnceInterned::new(),
+        }
+    }
+}
+
+#[expect(private_bounds)]
 pub trait KnownSize:
     GenericConstUsize
     + sealed::SizeTypeSealed
     + sealed::SizeSealed
     + Default
     + FillInDefaultedGenerics<Type = Self>
+    + GetInternedIntCaches
 {
     const SIZE: Self;
     type ArrayMatch<Element: Type>: AsRef<[Expr<Element>]>
@@ -148,7 +177,7 @@ pub trait KnownSize:
 
 impl<const N: usize> KnownSize for ConstUsize<N>
 where
-    [(); N]: KnownSizeBase,
+    ConstUsize<N>: KnownSizeBase,
 {
     const SIZE: Self = Self;
     type ArrayMatch<Element: Type> = [Expr<Element>; N];
@@ -221,6 +250,10 @@ pub trait Size:
     fn from_usize(v: usize) -> Self::SizeType {
         Self::try_from_usize(v).expect("wrong size")
     }
+    #[doc(hidden)]
+    fn interned_uint(size_type: Self::SizeType) -> Interned<UIntType<Self>>;
+    #[doc(hidden)]
+    fn interned_sint(size_type: Self::SizeType) -> Interned<SIntType<Self>>;
 }
 
 impl sealed::SizeTypeSealed for usize {}
@@ -229,6 +262,8 @@ impl SizeType for usize {
     type Size = DynSize;
 }
 
+const MAX_CACHED_INT_WIDTH: usize = 1 << 10;
+
 impl Size for DynSize {
     type ArrayMatch<Element: Type> = Box<[Expr<Element>]>;
     type ArraySimValue<Element: Type> = Box<[SimValue<Element>]>;
@@ -242,6 +277,36 @@ impl Size for DynSize {
     fn try_from_usize(v: usize) -> Option<Self::SizeType> {
         Some(v)
     }
+
+    #[doc(hidden)]
+    fn interned_uint(size_type: Self::SizeType) -> Interned<UIntType<Self>> {
+        static CACHED: [OnceInterned<UInt>; MAX_CACHED_INT_WIDTH] =
+            [const { OnceInterned::new() }; _];
+        #[cold]
+        fn intern_cold(width: usize) -> Interned<UInt> {
+            Intern::intern_sized(UInt::new(width))
+        }
+        if let Some(cached) = CACHED.get(size_type) {
+            cached.get_or_init(|| intern_cold(size_type))
+        } else {
+            intern_cold(size_type)
+        }
+    }
+
+    #[doc(hidden)]
+    fn interned_sint(size_type: Self::SizeType) -> Interned<SIntType<Self>> {
+        static CACHED: [OnceInterned<SInt>; MAX_CACHED_INT_WIDTH] =
+            [const { OnceInterned::new() }; _];
+        #[cold]
+        fn intern_cold(width: usize) -> Interned<SInt> {
+            Intern::intern_sized(SInt::new(width))
+        }
+        if let Some(cached) = CACHED.get(size_type) {
+            cached.get_or_init(|| intern_cold(size_type))
+        } else {
+            intern_cold(size_type)
+        }
+    }
 }
 
 impl<const VALUE: usize> sealed::SizeSealed for ConstUsize<VALUE> {}
@@ -267,6 +332,20 @@ impl<T: KnownSize> Size for T {
     fn try_from_usize(v: usize) -> Option<Self::SizeType> {
         if v == T::VALUE { Some(T::SIZE) } else { None }
     }
+
+    #[doc(hidden)]
+    fn interned_uint(_size_type: Self::SizeType) -> Interned<UIntType<Self>> {
+        T::get_interned_int_caches()
+            .uint
+            .get_or_init(|| UIntType::new_static().intern_sized())
+    }
+
+    #[doc(hidden)]
+    fn interned_sint(_size_type: Self::SizeType) -> Interned<SIntType<Self>> {
+        T::get_interned_int_caches()
+            .sint
+            .get_or_init(|| SIntType::new_static().intern_sized())
+    }
 }
 
 #[derive(Clone, PartialEq, Eq, Debug)]
@@ -586,7 +665,7 @@ macro_rules! impl_valueless_op_forward {
 }
 
 macro_rules! impl_int {
-    ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal) => {
+    ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal, $interned_int:ident) => {
         #[derive(Copy, Clone, PartialEq, Eq, Hash)]
         #[repr(transparent)]
         pub struct $name<Width: Size = DynSize> {
@@ -1003,7 +1082,7 @@ macro_rules! impl_int {
             type Output = $name<Width::Size>;
 
             fn index(&self, width: Width) -> &Self::Output {
-                Interned::into_inner(Intern::intern_sized($name::new(width)))
+                Interned::into_inner(Width::Size::$interned_int(width))
             }
         }
 
@@ -1184,8 +1263,22 @@ macro_rules! impl_int {
     };
 }
 
-impl_int!(UInt, UIntType, UIntWithoutGenerics, UIntValue, false);
-impl_int!(SInt, SIntType, SIntWithoutGenerics, SIntValue, true);
+impl_int!(
+    UInt,
+    UIntType,
+    UIntWithoutGenerics,
+    UIntValue,
+    false,
+    interned_uint
+);
+impl_int!(
+    SInt,
+    SIntType,
+    SIntWithoutGenerics,
+    SIntValue,
+    true,
+    interned_sint
+);
 
 impl UInt {
     /// gets the smallest `UInt` that fits `v` losslessly

crates/fayalite/src/intern.rs

@@ -4,68 +4,191 @@
 use crate::{intern::type_map::TypeIdMap, util::DefaultBuildHasher};
 use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec};
 use hashbrown::HashTable;
+use once_cell::race::OnceRef;
 use serde::{Deserialize, Serialize};
 use std::{
     any::{Any, TypeId},
     borrow::{Borrow, Cow},
+    cell::RefCell,
     cmp::Ordering,
     ffi::{OsStr, OsString},
     fmt,
     hash::{BuildHasher, Hash, Hasher},
     iter::FusedIterator,
-    marker::PhantomData,
     ops::Deref,
     path::{Path, PathBuf},
-    sync::{Mutex, RwLock},
+    sync::RwLock,
 };
 
+mod interner;
 mod type_map;
 
-pub trait LazyInternedTrait<T: ?Sized + Send + Sync + 'static>: Send + Sync + Any {
-    fn get(&self) -> Interned<T>;
+/// invariant: T must be zero-sized, `type_id` is unique for every possible T value.
+struct LazyInternedLazyInner<T: ?Sized + 'static> {
+    type_id: TypeId,
+    value: T,
 }
 
-impl<T: ?Sized + Send + Sync + 'static, F: ?Sized + Fn() -> Interned<T> + Send + Sync + Any>
-    LazyInternedTrait<T> for F
-{
-    fn get(&self) -> Interned<T> {
-        self()
+impl<T: ?Sized + 'static> Hash for LazyInternedLazyInner<T> {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        let Self { type_id, value: _ } = self;
+        type_id.hash(state);
     }
 }
 
-#[repr(transparent)]
-pub struct LazyInternedFn<T: ?Sized + Send + Sync + 'static>(pub &'static dyn LazyInternedTrait<T>);
+impl<T: ?Sized + 'static> PartialEq for LazyInternedLazyInner<T> {
+    fn eq(&self, other: &Self) -> bool {
+        let Self { type_id, value: _ } = self;
+        *type_id == other.type_id
+    }
+}
 
-impl<T: ?Sized + Send + Sync + 'static> Copy for LazyInternedFn<T> {}
+impl<T: ?Sized + 'static> Eq for LazyInternedLazyInner<T> {}
 
-impl<T: ?Sized + Send + Sync + 'static> Clone for LazyInternedFn<T> {
+impl<T: ?Sized + 'static> fmt::Debug for LazyInternedLazyInner<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("LazyInternedLazyInner")
+            .finish_non_exhaustive()
+    }
+}
+
+impl<T: ?Sized + 'static> LazyInternedLazyInner<T> {
+    const fn new(value: T) -> Self
+    where
+        T: Sized,
+    {
+        const { assert!(size_of::<T>() == 0) };
+        Self {
+            type_id: TypeId::of::<T>(),
+            value,
+        }
+    }
+}
+
+pub struct LazyInternedLazy<T: ?Sized + Send + Sync + 'static>(
+    &'static LazyInternedLazyInner<dyn Fn() -> Interned<T> + Send + Sync>,
+);
+
+impl<T: ?Sized + Send + Sync + 'static> LazyInternedLazy<T> {
+    pub const fn new_const<V: Default + Into<Interned<T>>>() -> Self {
+        Self(&const { LazyInternedLazyInner::new(|| V::default().into()) })
+    }
+    pub const fn new_const_default() -> Self
+    where
+        Interned<T>: Default,
+    {
+        Self::new_const::<Interned<T>>()
+    }
+    pub fn interned(self) -> Interned<T> {
+        struct Map(hashbrown::HashTable<(TypeId, &'static (dyn Any + Send + Sync))>);
+        impl Map {
+            const EMPTY: Self = Self(hashbrown::HashTable::new());
+            fn get<T: ?Sized + Send + Sync + 'static>(
+                &self,
+                lazy_interned_lazy: LazyInternedLazy<T>,
+                hash: u64,
+            ) -> Option<&'static Interned<T>> {
+                let &(_, v) = self.0.find(hash, |v| v.0 == lazy_interned_lazy.0.type_id)?;
+                let Some(retval) = v.downcast_ref::<Interned<T>>() else {
+                    unreachable!();
+                };
+                Some(retval)
+            }
+            fn get_or_insert<T: ?Sized + Send + Sync + 'static>(
+                &mut self,
+                lazy_interned_lazy: LazyInternedLazy<T>,
+                hash: u64,
+                v: &'static Interned<T>,
+            ) -> &'static Interned<T> {
+                let entry = self
+                    .0
+                    .entry(
+                        hash,
+                        |&(k, _)| k == lazy_interned_lazy.0.type_id,
+                        |&(k, _)| type_map::TypeIdBuildHasher.hash_one(k),
+                    )
+                    .or_insert_with(|| (lazy_interned_lazy.0.type_id, v));
+                let &(_, v) = entry.get();
+                let Some(retval) = v.downcast_ref::<Interned<T>>() else {
+                    unreachable!();
+                };
+                retval
+            }
+        }
+        static GLOBAL_CACHE: RwLock<Map> = RwLock::new(Map::EMPTY);
+        #[cold]
+        fn insert_in_thread_local_cache<T: ?Sized + Send + Sync + 'static>(
+            cache: &RefCell<Map>,
+            this: LazyInternedLazy<T>,
+            hash: u64,
+        ) -> Interned<T> {
+            let read_lock = GLOBAL_CACHE.read().unwrap();
+            let v = read_lock.get(this, hash);
+            drop(read_lock);
+            let v = v.unwrap_or_else(|| {
+                let v = Box::leak(Box::new((this.0.value)()));
+                GLOBAL_CACHE.write().unwrap().get_or_insert(this, hash, v)
+            });
+            *cache.borrow_mut().get_or_insert(this, hash, v)
+        }
+        thread_local! {
+            static THREAD_LOCAL_CACHE: RefCell<Map> = const { RefCell::new(Map::EMPTY) };
+        }
+        let hash = type_map::TypeIdBuildHasher.hash_one(self.0.type_id);
+        THREAD_LOCAL_CACHE.with(|cache| {
+            let borrow = cache.borrow();
+            if let Some(v) = borrow.get(self, hash) {
+                *v
+            } else {
+                drop(borrow);
+                insert_in_thread_local_cache(cache, self, hash)
+            }
+        })
+    }
+}
+
+impl<T: ?Sized + Send + Sync + 'static> Copy for LazyInternedLazy<T> {}
+
+impl<T: ?Sized + Send + Sync + 'static> Clone for LazyInternedLazy<T> {
     fn clone(&self) -> Self {
         *self
     }
 }
 
-impl<T: ?Sized + Send + Sync + 'static> Hash for LazyInternedFn<T> {
+impl<T: ?Sized + Send + Sync + 'static> Hash for LazyInternedLazy<T> {
     fn hash<H: Hasher>(&self, state: &mut H) {
-        self.0.get_ptr_eq_with_type_id().hash(state);
+        self.0.hash(state);
     }
 }
 
-impl<T: ?Sized + Send + Sync + 'static> Eq for LazyInternedFn<T> {}
+impl<T: ?Sized + Send + Sync + 'static> Eq for LazyInternedLazy<T> {}
 
-impl<T: ?Sized + Send + Sync + 'static> PartialEq for LazyInternedFn<T> {
+impl<T: ?Sized + Send + Sync + 'static> PartialEq for LazyInternedLazy<T> {
     fn eq(&self, other: &Self) -> bool {
-        self.0.get_ptr_eq_with_type_id() == other.0.get_ptr_eq_with_type_id()
+        self.0 == other.0
     }
 }
 
 pub enum LazyInterned<T: ?Sized + Send + Sync + 'static> {
     Interned(Interned<T>),
-    Lazy(LazyInternedFn<T>),
+    Lazy(LazyInternedLazy<T>),
 }
 
 impl<T: ?Sized + Send + Sync + 'static> LazyInterned<T> {
-    pub const fn new_lazy(v: &'static dyn LazyInternedTrait<T>) -> Self {
-        Self::Lazy(LazyInternedFn(v))
+    pub const fn new_const<V: Default + Into<Interned<T>>>() -> Self {
+        Self::Lazy(LazyInternedLazy::new_const::<V>())
+    }
+    pub const fn new_const_default() -> Self
+    where
+        Interned<T>: Default,
+    {
+        Self::new_const::<Interned<T>>()
+    }
+    pub fn interned(self) -> Interned<T> {
+        match self {
+            Self::Interned(retval) => retval,
+            Self::Lazy(retval) => retval.interned(),
+        }
     }
 }
 
@@ -77,7 +200,7 @@ impl<T: ?Sized + Sync + Send + 'static> Clone for LazyInterned<T> {
 
 impl<T: ?Sized + Sync + Send + 'static> Copy for LazyInterned<T> {}
 
-impl<T: ?Sized + Sync + Send + 'static + Intern> Deref for LazyInterned<T> {
+impl<T: ?Sized + Sync + Send + 'static> Deref for LazyInterned<T> {
     type Target = T;
 
     fn deref(&self) -> &Self::Target {
@@ -85,9 +208,9 @@ impl<T: ?Sized + Sync + Send + 'static + Intern> Deref for LazyInterned<T> {
     }
 }
 
-impl<T: ?Sized + Sync + Send + 'static + Intern> Eq for LazyInterned<T> where Interned<T>: Eq {}
+impl<T: ?Sized + Sync + Send + 'static> Eq for LazyInterned<T> where Interned<T>: Eq {}
 
-impl<T: ?Sized + Sync + Send + 'static + Intern> PartialEq for LazyInterned<T>
+impl<T: ?Sized + Sync + Send + 'static> PartialEq for LazyInterned<T>
 where
     Interned<T>: PartialEq,
 {
@@ -96,7 +219,7 @@ where
     }
 }
 
-impl<T: ?Sized + Sync + Send + 'static + Intern> Ord for LazyInterned<T>
+impl<T: ?Sized + Sync + Send + 'static> Ord for LazyInterned<T>
 where
     Interned<T>: Ord,
 {
@@ -105,7 +228,7 @@ where
     }
 }
 
-impl<T: ?Sized + Sync + Send + 'static + Intern> PartialOrd for LazyInterned<T>
+impl<T: ?Sized + Sync + Send + 'static> PartialOrd for LazyInterned<T>
 where
     Interned<T>: PartialOrd,
 {
@@ -114,7 +237,7 @@ where
     }
 }
 
-impl<T: ?Sized + Sync + Send + 'static + Intern> Hash for LazyInterned<T>
+impl<T: ?Sized + Sync + Send + 'static> Hash for LazyInterned<T>
 where
     Interned<T>: Hash,
 {
@@ -123,77 +246,6 @@ where
     }
 }
 
-impl<T: ?Sized + Sync + Send + 'static> LazyInterned<T> {
-    pub fn interned(self) -> Interned<T>
-    where
-        T: Intern,
-    {
-        struct MemoizeInterned<T: ?Sized + Intern>(PhantomData<T>);
-
-        impl<T: ?Sized + Intern> Hash for MemoizeInterned<T> {
-            fn hash<H: Hasher>(&self, _state: &mut H) {}
-        }
-
-        impl<T: ?Sized + Intern> PartialEq for MemoizeInterned<T> {
-            fn eq(&self, _other: &Self) -> bool {
-                true
-            }
-        }
-
-        impl<T: ?Sized + Intern> Eq for MemoizeInterned<T> {}
-
-        impl<T: ?Sized + Intern> Clone for MemoizeInterned<T> {
-            fn clone(&self) -> Self {
-                *self
-            }
-        }
-
-        impl<T: ?Sized + Intern> Copy for MemoizeInterned<T> {}
-
-        impl<T: ?Sized + Intern> MemoizeGeneric for MemoizeInterned<T> {
-            type InputRef<'a> = LazyInternedFn<T>;
-
-            type InputOwned = LazyInternedFn<T>;
-
-            type InputCow<'a> = LazyInternedFn<T>;
-
-            type Output = Interned<T>;
-
-            fn input_eq(a: Self::InputRef<'_>, b: Self::InputRef<'_>) -> bool {
-                a == b
-            }
-
-            fn input_borrow(input: &Self::InputOwned) -> Self::InputRef<'_> {
-                *input
-            }
-
-            fn input_cow_into_owned(input: Self::InputCow<'_>) -> Self::InputOwned {
-                input
-            }
-
-            fn input_cow_borrow<'a>(input: &'a Self::InputCow<'_>) -> Self::InputRef<'a> {
-                *input
-            }
-
-            fn input_cow_from_owned<'a>(input: Self::InputOwned) -> Self::InputCow<'a> {
-                input
-            }
-
-            fn input_cow_from_ref(input: Self::InputRef<'_>) -> Self::InputCow<'_> {
-                input
-            }
-
-            fn inner(self, input: Self::InputRef<'_>) -> Self::Output {
-                input.0.get()
-            }
-        }
-        match self {
-            Self::Interned(retval) => retval,
-            Self::Lazy(retval) => MemoizeInterned(PhantomData).get(retval),
-        }
-    }
-}
-
 pub trait InternedCompare {
     type InternedCompareKey: Ord + Hash;
     fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey;
@@ -593,71 +645,6 @@ impl<T: ?Sized + 'static + Send + Sync + ToOwned> From<Interned<T>> for Cow<'_,
     }
 }
 
-struct InternerState<T: ?Sized + 'static + Send + Sync> {
-    table: HashTable<&'static T>,
-    hasher: DefaultBuildHasher,
-}
-
-pub struct Interner<T: ?Sized + 'static + Send + Sync> {
-    state: Mutex<InternerState<T>>,
-}
-
-impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
-    fn get() -> &'static Interner<T> {
-        static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new();
-        TYPE_ID_MAP.get_or_insert_default()
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync> Default for Interner<T> {
-    fn default() -> Self {
-        Self {
-            state: Mutex::new(InternerState {
-                table: HashTable::new(),
-                hasher: Default::default(),
-            }),
-        }
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync + Hash + Eq + ToOwned> Interner<T> {
-    fn intern<F: FnOnce(Cow<'_, T>) -> &'static T>(
-        &self,
-        alloc: F,
-        value: Cow<'_, T>,
-    ) -> Interned<T> {
-        let mut state = self.state.lock().unwrap();
-        let InternerState { table, hasher } = &mut *state;
-        let inner = *table
-            .entry(
-                hasher.hash_one(&*value),
-                |k| **k == *value,
-                |k| hasher.hash_one(&**k),
-            )
-            .or_insert_with(|| alloc(value))
-            .get();
-        Interned { inner }
-    }
-}
-
-impl<T: Clone + 'static + Send + Sync + Hash + Eq> Interner<T> {
-    fn intern_sized(&self, value: Cow<'_, T>) -> Interned<T> {
-        self.intern(|value| Box::leak(Box::new(value.into_owned())), value)
-    }
-}
-
-impl<T: Clone + 'static + Send + Sync + Hash + Eq> Interner<[T]> {
-    fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> {
-        self.intern(|value| value.into_owned().leak(), value)
-    }
-}
-
-impl Interner<BitSlice> {
-    fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned<BitSlice> {
-        self.intern(|value| value.into_owned().leak(), value)
-    }
-}
-
 pub struct Interned<T: ?Sized + 'static + Send + Sync> {
     inner: &'static T,
 }
@@ -977,7 +964,7 @@ impl<T: Clone + Send + Sync + 'static + Hash + Eq> Intern for T {
     where
         Self: ToOwned,
     {
-        Interner::get().intern_sized(this)
+        interner::Interner::get().intern_sized(this)
     }
 }
 
@@ -997,7 +984,7 @@ impl<T: Clone + Send + Sync + 'static + Hash + Eq> Intern for [T] {
     where
         Self: ToOwned,
     {
-        Interner::get().intern_slice(this)
+        interner::Interner::get().intern_slice(this)
     }
 }
 
@@ -1017,7 +1004,7 @@ impl Intern for BitSlice {
     where
         Self: ToOwned,
     {
-        Interner::get().intern_bit_slice(this)
+        interner::Interner::get().intern_bit_slice(this)
     }
 }
 
@@ -1035,10 +1022,17 @@ pub trait MemoizeGeneric: 'static + Send + Sync + Hash + Eq + Copy {
     fn inner(self, input: Self::InputRef<'_>) -> Self::Output;
     fn get_cow(self, input: Self::InputCow<'_>) -> Self::Output {
         static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new();
+        thread_local! {
+            static TYPE_ID_MAP_CACHE: TypeIdMap = const { TypeIdMap::new() };
+        }
         let map: &RwLock<(
             DefaultBuildHasher,
             HashTable<(Self, Self::InputOwned, Self::Output)>,
-        )> = TYPE_ID_MAP.get_or_insert_default();
+        )> = TYPE_ID_MAP_CACHE.with(|cache| {
+            cache.get_or_insert_with(|| {
+                TYPE_ID_MAP.get_or_insert_with(|| Box::leak(Default::default()))
+            })
+        });
         fn hash_eq_key<'a, 'b, T: MemoizeGeneric>(
             this: &'a T,
             input: T::InputRef<'b>,
@@ -1140,3 +1134,35 @@ pub trait Memoize: 'static + Send + Sync + Hash + Eq + Copy {
         self.get_cow(Cow::Borrowed(input))
     }
 }
+
+/// like `once_cell::race::OnceBox` but for `Interned<T>` instead of `Box<T>`
+pub struct OnceInterned<T: 'static + Send + Sync>(OnceRef<'static, T>);
+
+impl<T: 'static + Send + Sync + fmt::Debug> fmt::Debug for OnceInterned<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_tuple("OnceInterned").field(&self.get()).finish()
+    }
+}
+
+impl<T: 'static + Send + Sync> Default for OnceInterned<T> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl<T: 'static + Send + Sync> OnceInterned<T> {
+    pub const fn new() -> Self {
+        Self(OnceRef::new())
+    }
+    pub fn set(&self, v: Interned<T>) -> Result<(), ()> {
+        self.0.set(v.inner)
+    }
+    pub fn get(&self) -> Option<Interned<T>> {
+        self.0.get().map(|inner| Interned { inner })
+    }
+    pub fn get_or_init<F: FnOnce() -> Interned<T>>(&self, f: F) -> Interned<T> {
+        Interned {
+            inner: self.0.get_or_init(|| f().inner),
+        }
+    }
+}

crates/fayalite/src/intern/interner.rs

@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    intern::{Interned, type_map::TypeIdMap},
+    util::DefaultBuildHasher,
+};
+use bitvec::slice::BitSlice;
+use hashbrown::HashTable;
+use std::{
+    borrow::Cow,
+    hash::{BuildHasher, Hash},
+    sync::RwLock,
+};
+
+struct InternerShard<T: ?Sized + 'static + Send + Sync> {
+    table: HashTable<&'static T>,
+}
+
+const LOG2_SHARD_COUNT: u32 = 6;
+
+fn shard_index_from_hash(hash: u64) -> usize {
+    // number of bits used for hashbrown's Tag
+    const HASH_BROWN_TAG_BITS: u32 = 7;
+    // try to extract bits of the hash that hashbrown isn't using,
+    // while accounting for some hash functions only returning `usize` bits.
+    const SHARD_INDEX_START: u32 = usize::BITS
+        .saturating_sub(HASH_BROWN_TAG_BITS)
+        .saturating_sub(LOG2_SHARD_COUNT);
+    let mut shard_index = hash >> SHARD_INDEX_START;
+    shard_index %= 1 << LOG2_SHARD_COUNT;
+    shard_index as usize
+}
+
+pub(crate) struct Interner<T: ?Sized + 'static + Send + Sync> {
+    shards: [RwLock<InternerShard<T>>; 1 << LOG2_SHARD_COUNT],
+    hasher: DefaultBuildHasher,
+}
+
+impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
+    pub(crate) fn get() -> &'static Interner<T> {
+        static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new();
+        thread_local! {
+            static TYPE_ID_MAP_CACHE: TypeIdMap = const { TypeIdMap::new() };
+        }
+        TYPE_ID_MAP_CACHE.with(|cache| {
+            cache.get_or_insert_with(|| {
+                TYPE_ID_MAP.get_or_insert_with(|| Box::leak(Default::default()))
+            })
+        })
+    }
+}
+
+impl<T: ?Sized + 'static + Send + Sync> Default for Interner<T> {
+    fn default() -> Self {
+        Self {
+            shards: [const {
+                RwLock::new(InternerShard {
+                    table: HashTable::new(),
+                })
+            }; _],
+            hasher: Default::default(),
+        }
+    }
+}
+
+impl<T: ?Sized + 'static + Send + Sync + Hash + Eq + ToOwned> Interner<T> {
+    fn intern<F: FnOnce(Cow<'_, T>) -> &'static T>(
+        &self,
+        alloc: F,
+        value: Cow<'_, T>,
+    ) -> Interned<T> {
+        let hash = self.hasher.hash_one(&*value);
+        let shard_index = shard_index_from_hash(hash);
+        let shard = &self.shards[shard_index];
+        let shard_read = shard.read().unwrap();
+        let Some(&inner) = shard_read.table.find(hash, |k| **k == *value) else {
+            drop(shard_read);
+            return self.intern_cold(alloc, value, hash, shard);
+        };
+        Interned { inner }
+    }
+    #[cold]
+    fn intern_cold<F: FnOnce(Cow<'_, T>) -> &'static T>(
+        &self,
+        alloc: F,
+        value: Cow<'_, T>,
+        hash: u64,
+        shard: &RwLock<InternerShard<T>>,
+    ) -> Interned<T> {
+        let mut shard = shard.write().unwrap();
+        let inner = *shard
+            .table
+            .entry(hash, |k| **k == *value, |k| self.hasher.hash_one(&**k))
+            .or_insert_with(|| alloc(value))
+            .get();
+        Interned { inner }
+    }
+}
+
+impl<T: Clone + 'static + Send + Sync + Hash + Eq> Interner<T> {
+    pub(crate) fn intern_sized(&self, value: Cow<'_, T>) -> Interned<T> {
+        self.intern(|value| Box::leak(Box::new(value.into_owned())), value)
+    }
+}
+
+impl<T: Clone + 'static + Send + Sync + Hash + Eq> Interner<[T]> {
+    pub(crate) fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> {
+        self.intern(|value| value.into_owned().leak(), value)
+    }
+}
+
+impl Interner<BitSlice> {
+    pub(crate) fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned<BitSlice> {
+        self.intern(|value| value.into_owned().leak(), value)
+    }
+}

crates/fayalite/src/intern/type_map.rs

@@ -6,7 +6,7 @@ use std::{
     sync::RwLock,
 };
 
-struct TypeIdHasher(u64);
+pub(crate) struct TypeIdHasher(u64);
 
 // assumes TypeId has at least 64 bits that is a good hash
 impl Hasher for TypeIdHasher {
@@ -63,7 +63,7 @@ impl Hasher for TypeIdHasher {
     }
 }
 
-struct TypeIdBuildHasher;
+pub(crate) struct TypeIdBuildHasher;
 
 impl BuildHasher for TypeIdBuildHasher {
     type Hasher = TypeIdHasher;
@@ -87,20 +87,23 @@ impl TypeIdMap {
     fn insert_slow(
         &self,
         type_id: TypeId,
-        make: fn() -> Box<dyn Any + Sync + Send>,
+        make: impl FnOnce() -> &'static (dyn Any + Sync + Send),
     ) -> &'static (dyn Any + Sync + Send) {
-        let value = Box::leak(make());
+        let value = make();
         let mut write_guard = self.0.write().unwrap();
         *write_guard.entry(type_id).or_insert(value)
     }
-    pub(crate) fn get_or_insert_default<T: Sized + Any + Send + Sync + Default>(&self) -> &T {
+    pub(crate) fn get_or_insert_with<T: Sized + Any + Send + Sync>(
+        &self,
+        make: impl FnOnce() -> &'static T,
+    ) -> &'static T {
         let type_id = TypeId::of::<T>();
         let read_guard = self.0.read().unwrap();
         let retval = read_guard.get(&type_id).map(|v| *v);
         drop(read_guard);
         let retval = match retval {
             Some(retval) => retval,
-            None => self.insert_slow(type_id, move || Box::new(T::default())),
+            None => self.insert_slow(type_id, move || make()),
         };
         retval.downcast_ref().expect("known to have correct TypeId")
     }

crates/fayalite/src/phantom_const.rs

@@ -4,7 +4,7 @@
 use crate::{
     expr::{Expr, HdlPartialEqImpl, HdlPartialOrdImpl, ToExpr, ValueType},
     int::Bool,
-    intern::{Intern, Interned, InternedCompare, LazyInterned, LazyInternedTrait, Memoize},
+    intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
     sim::value::{SimValue, ToSimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{
@@ -240,11 +240,17 @@ impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
     {
         Self::new_interned(value.intern_deref())
     }
-    pub const fn new_lazy(v: &'static dyn LazyInternedTrait<T>) -> Self {
+    pub const fn new_const<V: Default + Into<Interned<T>>>() -> Self {
         Self {
-            value: LazyInterned::new_lazy(v),
+            value: LazyInterned::new_const::<V>(),
         }
     }
+    pub const fn new_const_default() -> Self
+    where
+        Interned<T>: Default,
+    {
+        Self::new_const::<Interned<T>>()
+    }
     pub fn get(self) -> Interned<T> {
         self.value.interned()
     }
@@ -334,9 +340,7 @@ impl<T: ?Sized + PhantomConstValue> StaticType for PhantomConst<T>
 where
     Interned<T>: Default,
 {
-    const TYPE: Self = PhantomConst {
-        value: LazyInterned::new_lazy(&Interned::<T>::default),
-    };
+    const TYPE: Self = Self::new_const_default();
     const MASK_TYPE: Self::MaskType = ();
     const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
     const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;

crates/fayalite/src/sim.rs

@@ -40,7 +40,7 @@ use crate::{
         OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSizeRange, OpaqueSimValueSlice,
         OpaqueSimValueWriter,
     },
-    util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet},
+    util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet, copy_le_bytes_to_bitslice},
 };
 use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use num_bigint::BigInt;
@@ -1295,10 +1295,16 @@ impl SimulationModuleState {
                 if !self.uninitialized_ios.is_empty() {
                     match which_module {
                         WhichModule::Main => {
-                            panic!("can't read from an output before initializing all inputs");
+                            panic!(
+                                "can't read from an output before initializing all inputs\nuninitialized_ios={:#?}",
+                                SortedSetDebug(&self.uninitialized_ios),
+                            );
                         }
                         WhichModule::Extern { .. } => {
-                            panic!("can't read from an input before initializing all outputs");
+                            panic!(
+                                "can't read from an input before initializing all outputs\nuninitialized_ios={:#?}",
+                                SortedSetDebug(&self.uninitialized_ios),
+                            );
                         }
                     }
                 }
@@ -2198,14 +2204,11 @@ impl SimulationImpl {
                 SimTraceKind::BigUInt { index, ty: _ } | SimTraceKind::BigSInt { index, ty: _ } => {
                     let state = state.unwrap_bits_mut();
                     let bigint = &self.state.big_slots[index];
-                    let mut bytes = bigint.to_signed_bytes_le();
-                    bytes.resize(
-                        state.len().div_ceil(8),
-                        if bigint.is_negative() { 0xFF } else { 0 },
+                    copy_le_bytes_to_bitslice(
+                        state,
+                        &bigint.to_signed_bytes_le(),
+                        bigint.is_negative(),
                     );
-                    let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
-                    let bitslice = &bitslice[..state.len()];
-                    state.clone_from_bitslice(bitslice);
                 }
                 SimTraceKind::BigBool { index }
                 | SimTraceKind::BigAsyncReset { index }

crates/fayalite/src/sim/compiler.rs

@@ -4087,6 +4087,15 @@ impl Compiler {
             let init = self.compiled_expr_to_value(init, reg.source_location());
             (reg.clock_domain().rst, init)
         });
+
+        // next value defaults to current value
+        self.compile_simple_connect(
+            [].intern_slice(),
+            value.into(),
+            value,
+            reg.source_location(),
+        );
+
         self.compile_reg(
             clk,
             reset_and_init,

crates/fayalite/src/sim/vcd.rs

@@ -21,14 +21,31 @@ use crate::{
 };
 use bitvec::{order::Lsb0, slice::BitSlice};
 use hashbrown::hash_map::Entry;
+use sha2::{Digest, Sha256};
 use std::{
+    collections::BTreeMap,
     fmt::{self, Write as _},
     io, mem,
+    num::NonZeroU64,
 };
 
-#[derive(Default)]
+#[derive(Default, Clone)]
+struct PathHash(Sha256);
+
+impl PathHash {
+    fn joined(mut self, segment: impl AsRef<[u8]>) -> Self {
+        let segment = segment.as_ref();
+        self.0.update(u32::to_le_bytes(
+            segment.len().try_into().expect("path segment is too big"),
+        ));
+        self.0.update(segment);
+        self
+    }
+}
+
 struct Scope {
     last_inserted: HashMap<Interned<str>, usize>,
+    path_hash: PathHash,
 }
 
 #[derive(Copy, Clone)]
@@ -61,6 +78,13 @@ impl fmt::Display for VerilogIdentifier {
 }
 
 impl Scope {
+    fn new(path_hash: PathHash) -> Self {
+        Self {
+            last_inserted: Default::default(),
+            path_hash,
+        }
+    }
+
     fn new_identifier(&mut self, unescaped_name: Interned<str>) -> VerilogIdentifier {
         let next_disambiguator = match self.last_inserted.entry(unescaped_name) {
             Entry::Vacant(entry) => {
@@ -163,6 +187,26 @@ impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
     }
 }
 
+/// pass in scope to ensure it's not available in child scope
+fn try_write_vcd_scope<W: io::Write, R>(
+    writer: &mut W,
+    scope_type: &str,
+    scope_name: Interned<str>,
+    scope: Option<&mut Scope>,
+    f: impl FnOnce(&mut W, Option<&mut Scope>) -> io::Result<R>,
+) -> io::Result<R> {
+    let Some(scope) = scope else {
+        return f(writer, None);
+    };
+    write_vcd_scope(
+        writer,
+        scope_type,
+        scope_name,
+        scope,
+        move |writer, scope| f(writer, Some(scope)),
+    )
+}
+
 /// pass in scope to ensure it's not available in child scope
 fn write_vcd_scope<W: io::Write, R>(
     writer: &mut W,
@@ -171,12 +215,10 @@ fn write_vcd_scope<W: io::Write, R>(
     scope: &mut Scope,
     f: impl FnOnce(&mut W, &mut Scope) -> io::Result<R>,
 ) -> io::Result<R> {
-    writeln!(
-        writer,
-        "$scope {scope_type} {} $end",
-        scope.new_identifier(scope_name),
-    )?;
-    let retval = f(writer, &mut Scope::default())?;
+    let path_hash = scope.path_hash.clone().joined(scope_name);
+    let scope_name = scope.new_identifier(scope_name);
+    writeln!(writer, "$scope {scope_type} {scope_name} $end")?;
+    let retval = f(writer, &mut Scope::new(path_hash))?;
     writeln!(writer, "$upscope $end")?;
     Ok(retval)
 }
@@ -216,6 +258,7 @@ trait_arg! {
 struct ArgModule<'a> {
     properties: &'a mut VcdWriterProperties,
     scope: &'a mut Scope,
+    instance_name: Option<Interned<str>>,
 }
 
 impl<'a> ArgModule<'a> {
@@ -223,6 +266,7 @@ impl<'a> ArgModule<'a> {
         ArgModule {
             properties: self.properties,
             scope: self.scope,
+            instance_name: self.instance_name,
         }
     }
 }
@@ -246,7 +290,7 @@ struct ArgInType<'a> {
     sink_var_type: &'static str,
     duplex_var_type: &'static str,
     properties: &'a mut VcdWriterProperties,
-    scope: &'a mut Scope,
+    scope: Option<&'a mut Scope>,
 }
 
 impl<'a> ArgInType<'a> {
@@ -256,7 +300,7 @@ impl<'a> ArgInType<'a> {
             sink_var_type: self.sink_var_type,
             duplex_var_type: self.duplex_var_type,
             properties: self.properties,
-            scope: self.scope,
+            scope: self.scope.as_deref_mut(),
         }
     }
 }
@@ -291,19 +335,78 @@ impl WriteTrace for TraceScalar {
     }
 }
 
-fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
-    let min_char = b'!';
-    let max_char = b'~';
-    let base = (max_char - min_char + 1) as usize;
-    loop {
-        let digit = (id % base) as u8 + min_char;
-        id /= base;
-        writer.write_all(&[digit])?;
-        if id == 0 {
-            break;
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[repr(transparent)]
+struct VcdId(NonZeroU64);
+
+impl VcdId {
+    const CHAR_RANGE: std::ops::RangeInclusive<u8> = b'!'..=b'~';
+    const BASE: u8 = *Self::CHAR_RANGE.end() - *Self::CHAR_RANGE.start() + 1;
+    const LOW_HALF_CHARS: u32 = 5;
+    const LOW_HALF_MODULUS: u64 = (Self::BASE as u64).pow(Self::LOW_HALF_CHARS);
+
+    const fn from_str(s: &str) -> Option<Self> {
+        if s.is_empty() {
+            return None;
         }
+        let mut retval = 0u64;
+        let mut bytes = s.as_bytes();
+        while let [ref rest @ .., digit] = *bytes {
+            bytes = rest;
+            let Some(digit) = digit.checked_sub(*Self::CHAR_RANGE.start()) else {
+                return None;
+            };
+            if digit >= Self::BASE {
+                return None;
+            }
+            let Some(v) = retval.checked_mul(Self::BASE as _) else {
+                return None;
+            };
+            let Some(v) = v.checked_add(digit as _) else {
+                return None;
+            };
+            retval = v;
+        }
+        let Some(retval) = NonZeroU64::new(retval) else {
+            return None;
+        };
+        Some(Self(retval))
     }
-    Ok(())
+    #[must_use]
+    const fn write(self, out: &mut [u8]) -> usize {
+        let mut id = self.0.get();
+        let mut len = 0;
+        loop {
+            let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start();
+            id /= Self::BASE as u64;
+            if len < out.len() {
+                out[len] = digit;
+            }
+            len += 1;
+            if id == 0 {
+                break;
+            }
+        }
+        len
+    }
+    const MAX_ID_LEN: usize = Self(NonZeroU64::MAX).write(&mut []);
+}
+
+/// check that VcdId properly round-trips
+const _: () = {
+    let s = "RoundTrip";
+    let Some(id) = VcdId::from_str(s) else {
+        unreachable!();
+    };
+    let mut buf = [0u8; VcdId::MAX_ID_LEN];
+    let len = id.write(&mut buf);
+    assert!(crate::util::const_bytes_cmp(buf.split_at(len).0, s.as_bytes()).is_eq());
+};
+
+fn write_vcd_id<W: io::Write>(writer: &mut W, id: VcdId) -> io::Result<()> {
+    let mut buf = [0u8; VcdId::MAX_ID_LEN];
+    let len = id.write(&mut buf);
+    writer.write_all(&buf[..len])
 }
 
 struct Escaped<T: fmt::Display>(T);
@@ -346,12 +449,13 @@ impl<T: fmt::Display> fmt::Display for Escaped<T> {
 
 fn write_vcd_var<W: io::Write>(
     properties: &mut VcdWriterProperties,
+    scope: Option<&mut Scope>,
     memory_element_part_body: MemoryElementPartBody,
     writer: &mut W,
     var_type: &str,
     size: usize,
     location: TraceLocation,
-    name: VerilogIdentifier,
+    name: Interned<str>,
 ) -> io::Result<()> {
     let id = match location {
         TraceLocation::Scalar(id) => id.as_usize(),
@@ -384,9 +488,21 @@ fn write_vcd_var<W: io::Write>(
             first_id + *element_index
         }
     };
-    write!(writer, "$var {var_type} {size} ")?;
-    write_vcd_id(writer, id)?;
-    writeln!(writer, " {name} $end")
+    if let Some(scope) = scope {
+        let path_hash = scope.path_hash.clone().joined(name);
+        let name = scope.new_identifier(name);
+        let id = properties
+            .scalar_id_to_vcd_id_map
+            .builder_get_or_insert(id, &path_hash);
+        write!(writer, "$var {var_type} {size} ")?;
+        write_vcd_id(writer, id)?;
+        writeln!(writer, " {name} $end")
+    } else {
+        properties
+            .scalar_id_to_vcd_id_map
+            .builder_unused_scalar_id(id);
+        Ok(())
+    }
 }
 
 impl WriteTrace for TraceUInt {
@@ -414,12 +530,13 @@ impl WriteTrace for TraceUInt {
         }
         write_vcd_var(
             properties,
+            scope,
             MemoryElementPartBody::Scalar,
             writer,
             var_type,
             ty.width(),
             location,
-            scope.new_identifier(name),
+            name,
         )
     }
 }
@@ -494,12 +611,13 @@ impl WriteTrace for TraceEnumDiscriminant {
         } = self;
         write_vcd_var(
             properties,
+            scope,
             MemoryElementPartBody::EnumDiscriminant { ty },
             writer,
             "string",
             1,
             location,
-            scope.new_identifier(name),
+            name,
         )
     }
 }
@@ -569,12 +687,13 @@ impl WriteTrace for TracePhantomConst {
         } = self;
         write_vcd_var(
             properties,
+            scope,
             MemoryElementPartBody::Scalar,
             writer,
             "string",
             1,
             location,
-            scope.new_identifier(name),
+            name,
         )
     }
 }
@@ -596,12 +715,13 @@ impl WriteTrace for TraceSimOnly {
         } = self;
         write_vcd_var(
             properties,
+            scope,
             MemoryElementPartBody::Scalar,
             writer,
             "string",
             1,
             location,
-            scope.new_identifier(name),
+            name,
         )
     }
 }
@@ -625,14 +745,24 @@ impl WriteTrace for TraceScope {
 
 impl WriteTrace for TraceModule {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModule { properties, scope } = arg.module();
+        let ArgModule {
+            properties,
+            scope,
+            instance_name,
+        } = arg.module();
         let Self { name, children } = self;
-        write_vcd_scope(writer, "module", name, scope, |writer, scope| {
-            for child in children {
-                child.write_trace(writer, ArgModuleBody { properties, scope })?;
-            }
-            Ok(())
-        })
+        write_vcd_scope(
+            writer,
+            "module",
+            instance_name.unwrap_or(name),
+            scope,
+            |writer, scope| {
+                for child in children {
+                    child.write_trace(writer, ArgModuleBody { properties, scope })?;
+                }
+                Ok(())
+            },
+        )
     }
 }
 
@@ -640,7 +770,7 @@ impl WriteTrace for TraceInstance {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
         let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
-            name: _,
+            name,
             instance_io,
             module,
             ty: _,
@@ -652,10 +782,17 @@ impl WriteTrace for TraceInstance {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
-                scope,
+                scope: None,
             },
         )?;
-        module.write_trace(writer, ArgModule { properties, scope })
+        module.write_trace(
+            writer,
+            ArgModule {
+                properties,
+                scope,
+                instance_name: Some(name),
+            },
+        )
     }
 }
 
@@ -694,7 +831,7 @@ impl WriteTrace for TraceMem {
                                         sink_var_type: "reg",
                                         duplex_var_type: "reg",
                                         properties,
-                                        scope,
+                                        scope: Some(scope),
                                     },
                                 )
                             },
@@ -726,7 +863,7 @@ impl WriteTrace for TraceMemPort {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
-                scope,
+                scope: Some(scope),
             },
         )
     }
@@ -747,7 +884,7 @@ impl WriteTrace for TraceWire {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
-                scope,
+                scope: Some(scope),
             },
         )
     }
@@ -768,7 +905,7 @@ impl WriteTrace for TraceReg {
                 sink_var_type: "reg",
                 duplex_var_type: "reg",
                 properties,
-                scope,
+                scope: Some(scope),
             },
         )
     }
@@ -790,7 +927,7 @@ impl WriteTrace for TraceModuleIO {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
-                scope,
+                scope: Some(scope),
             },
         )
     }
@@ -811,7 +948,7 @@ impl WriteTrace for TraceBundle {
             ty: _,
             flow: _,
         } = self;
-        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+        try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
             for field in fields {
                 field.write_trace(
                     writer,
@@ -820,7 +957,7 @@ impl WriteTrace for TraceBundle {
                         sink_var_type,
                         duplex_var_type,
                         properties,
-                        scope,
+                        scope: scope.as_deref_mut(),
                     },
                 )?;
             }
@@ -844,7 +981,7 @@ impl WriteTrace for TraceArray {
             ty: _,
             flow: _,
         } = self;
-        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+        try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
             for element in elements {
                 element.write_trace(
                     writer,
@@ -853,7 +990,7 @@ impl WriteTrace for TraceArray {
                         sink_var_type,
                         duplex_var_type,
                         properties,
-                        scope,
+                        scope: scope.as_deref_mut(),
                     },
                 )?;
             }
@@ -878,7 +1015,7 @@ impl WriteTrace for TraceEnumWithFields {
             ty: _,
             flow: _,
         } = self;
-        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+        try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
             discriminant.write_trace(
                 writer,
                 ArgInType {
@@ -886,7 +1023,7 @@ impl WriteTrace for TraceEnumWithFields {
                     sink_var_type,
                     duplex_var_type,
                     properties,
-                    scope,
+                    scope: scope.as_deref_mut(),
                 },
             )?;
             for field in non_empty_fields {
@@ -897,7 +1034,7 @@ impl WriteTrace for TraceEnumWithFields {
                         sink_var_type,
                         duplex_var_type,
                         properties,
-                        scope,
+                        scope: scope.as_deref_mut(),
                     },
                 )?;
             }
@@ -923,6 +1060,9 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
         writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
         let mut properties = VcdWriterProperties {
             next_scalar_id: trace_scalar_id_count,
+            scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder::Builder(
+                ScalarIdToVcdIdMapBuilder::default(),
+            ),
             memory_properties: (0..trace_memory_id_count)
                 .map(|_| MemoryProperties {
                     element_parts: Vec::with_capacity(8),
@@ -935,9 +1075,17 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
             &mut writer,
             ArgModule {
                 properties: &mut properties,
-                scope: &mut Scope::default(),
+                scope: &mut Scope::new(PathHash::default()),
+                instance_name: None,
             },
         )?;
+        let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) =
+            properties.scalar_id_to_vcd_id_map
+        else {
+            unreachable!();
+        };
+        properties.scalar_id_to_vcd_id_map =
+            ScalarIdToVcdIdMapOrBuilder::Built(scalar_id_to_vcd_id_map_builder.build());
         writeln!(writer, "$enddefinitions $end")?;
         writeln!(writer, "$dumpvars")?;
         Ok(VcdWriter {
@@ -967,8 +1115,100 @@ struct MemoryProperties {
     element_index: usize,
 }
 
+struct ScalarIdToVcdIdMap {
+    scalar_id_to_vcd_id_map: Box<[Option<VcdId>]>,
+}
+
+#[derive(Default)]
+struct ScalarIdToVcdIdMapBuilder {
+    scalar_id_to_vcd_id_map: BTreeMap<usize, Option<VcdId>>,
+    lower_half_to_next_upper_half_map: HashMap<u64, u64>,
+}
+
+impl ScalarIdToVcdIdMapBuilder {
+    fn unused_scalar_id(&mut self, scalar_id: usize) {
+        self.scalar_id_to_vcd_id_map
+            .entry(scalar_id)
+            .or_insert(None);
+    }
+    /// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change
+    /// when unrelated variables are added/removed, making the generated VCD more friendly for git diff.
+    fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId {
+        *self
+            .scalar_id_to_vcd_id_map
+            .entry(scalar_id)
+            .or_insert(None)
+            .get_or_insert_with(|| {
+                let hash = u128::from_le_bytes(
+                    *path_hash
+                        .0
+                        .clone()
+                        .finalize()
+                        .first_chunk()
+                        .expect("known to be bigger than u128"),
+                );
+                let lower_half = (hash % VcdId::LOW_HALF_MODULUS as u128) as u64;
+                let next_upper_half = self
+                    .lower_half_to_next_upper_half_map
+                    .entry(lower_half)
+                    .or_insert(if lower_half == 0 { 1 } else { 0 });
+                let upper_half = *next_upper_half;
+                *next_upper_half += 1;
+                let Some(id) = upper_half
+                    .checked_mul(VcdId::LOW_HALF_MODULUS)
+                    .and_then(|v| v.checked_add(lower_half))
+                else {
+                    panic!("too many VcdIds");
+                };
+                VcdId(NonZeroU64::new(id).expect("known to not be zero"))
+            })
+    }
+    fn build(self) -> ScalarIdToVcdIdMap {
+        ScalarIdToVcdIdMap {
+            scalar_id_to_vcd_id_map: self
+                .scalar_id_to_vcd_id_map
+                .into_iter()
+                .enumerate()
+                .map(|(index, (scalar_id, vcd_id))| {
+                    if index != scalar_id {
+                        panic!("missing scalar id {index}");
+                    }
+                    vcd_id
+                })
+                .collect(),
+        }
+    }
+}
+
+enum ScalarIdToVcdIdMapOrBuilder {
+    Builder(ScalarIdToVcdIdMapBuilder),
+    Built(ScalarIdToVcdIdMap),
+}
+
+impl ScalarIdToVcdIdMapOrBuilder {
+    fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> Option<VcdId> {
+        let Self::Built(v) = self else {
+            panic!("ScalarIdToVcdIdMap isn't built yet");
+        };
+        v.scalar_id_to_vcd_id_map[scalar_id]
+    }
+    fn builder_get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId {
+        let Self::Builder(v) = self else {
+            panic!("ScalarIdToVcdIdMap is already built");
+        };
+        v.get_or_insert(scalar_id, path_hash)
+    }
+    fn builder_unused_scalar_id(&mut self, scalar_id: usize) {
+        let Self::Builder(v) = self else {
+            panic!("ScalarIdToVcdIdMap is already built");
+        };
+        v.unused_scalar_id(scalar_id)
+    }
+}
+
 struct VcdWriterProperties {
     next_scalar_id: usize,
+    scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder,
     memory_properties: Box<[MemoryProperties]>,
 }
 
@@ -988,8 +1228,11 @@ impl<W: io::Write + 'static> VcdWriter<W> {
 fn write_string_value_change(
     writer: &mut impl io::Write,
     value: impl fmt::Display,
-    id: usize,
+    id: Option<VcdId>,
 ) -> io::Result<()> {
+    let Some(id) = id else {
+        return Ok(());
+    };
     write!(writer, "s{} ", Escaped(value))?;
     write_vcd_id(writer, id)?;
     writer.write_all(b"\n")
@@ -998,8 +1241,11 @@ fn write_string_value_change(
 fn write_bits_value_change(
     writer: &mut impl io::Write,
     value: &BitSlice,
-    id: usize,
+    id: Option<VcdId>,
 ) -> io::Result<()> {
+    let Some(id) = id else {
+        return Ok(());
+    };
     match value.len() {
         0 => writer.write_all(b"s0 ")?,
         1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
@@ -1028,7 +1274,7 @@ fn write_enum_discriminant_value_change(
     writer: &mut impl io::Write,
     variant_index: usize,
     ty: Enum,
-    id: usize,
+    id: Option<VcdId>,
 ) -> io::Result<()> {
     write_string_value_change(
         writer,
@@ -1063,7 +1309,9 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
                 MemoryElementPartBody::Scalar => write_bits_value_change(
                     &mut self.writer,
                     &element_data[start..start + len],
-                    first_id + element_index,
+                    self.properties
+                        .scalar_id_to_vcd_id_map
+                        .built_scalar_id_to_vcd_id(first_id + element_index),
                 )?,
                 MemoryElementPartBody::EnumDiscriminant { ty } => {
                     let mut variant_index = 0;
@@ -1073,7 +1321,9 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
                         &mut self.writer,
                         variant_index,
                         *ty,
-                        first_id + element_index,
+                        self.properties
+                            .scalar_id_to_vcd_id_map
+                            .built_scalar_id_to_vcd_id(first_id + element_index),
                     )?
                 }
             }
@@ -1082,11 +1332,23 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
     }
 
     fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        write_bits_value_change(&mut self.writer, value, id.as_usize())
+        write_bits_value_change(
+            &mut self.writer,
+            value,
+            self.properties
+                .scalar_id_to_vcd_id_map
+                .built_scalar_id_to_vcd_id(id.as_usize()),
+        )
     }
 
     fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        write_bits_value_change(&mut self.writer, value, id.as_usize())
+        write_bits_value_change(
+            &mut self.writer,
+            value,
+            self.properties
+                .scalar_id_to_vcd_id_map
+                .built_scalar_id_to_vcd_id(id.as_usize()),
+        )
     }
 
     fn finish_init(&mut self) -> Result<(), Self::Error> {
@@ -1118,7 +1380,14 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
         variant_index: usize,
         ty: Enum,
     ) -> Result<(), Self::Error> {
-        write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize())
+        write_enum_discriminant_value_change(
+            &mut self.writer,
+            variant_index,
+            ty,
+            self.properties
+                .scalar_id_to_vcd_id_map
+                .built_scalar_id_to_vcd_id(id.as_usize()),
+        )
     }
 
     fn set_signal_phantom_const(
@@ -1128,7 +1397,13 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
     ) -> Result<(), Self::Error> {
         // avoid multi-line strings because GTKWave can't display them properly:
         // https://github.com/gtkwave/gtkwave/issues/460
-        write_string_value_change(&mut self.writer, format_args!("{ty:?}"), id.as_usize())
+        write_string_value_change(
+            &mut self.writer,
+            format_args!("{ty:?}"),
+            self.properties
+                .scalar_id_to_vcd_id_map
+                .built_scalar_id_to_vcd_id(id.as_usize()),
+        )
     }
 
     fn set_signal_sim_only_value(
@@ -1136,7 +1411,13 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
         id: TraceScalarId,
         value: &DynSimOnlyValue,
     ) -> Result<(), Self::Error> {
-        write_string_value_change(&mut self.writer, format_args!("{value:?}"), id.as_usize())
+        write_string_value_change(
+            &mut self.writer,
+            format_args!("{value:?}"),
+            self.properties
+                .scalar_id_to_vcd_id_map
+                .built_scalar_id_to_vcd_id(id.as_usize()),
+        )
     }
 }
 
@@ -1161,7 +1442,7 @@ mod tests {
 
     #[test]
     fn test_scope() {
-        let mut scope = Scope::default();
+        let mut scope = Scope::new(PathHash::default());
         assert_eq!(&*scope.new_identifier("foo".intern()).unescaped_name, "foo");
         assert_eq!(
             &*scope.new_identifier("foo_0".intern()).unescaped_name,

crates/fayalite/src/util.rs

@@ -41,7 +41,7 @@ pub use misc::{
     os_str_strip_suffix, serialize_to_json_ascii, serialize_to_json_ascii_pretty,
     serialize_to_json_ascii_pretty_with_indent, slice_range, try_slice_range,
 };
-pub(crate) use misc::{InternedStrCompareAsStr, chain};
+pub(crate) use misc::{InternedStrCompareAsStr, chain, copy_le_bytes_to_bitslice};
 
 pub mod job_server;
 pub mod prefix_sum;

crates/fayalite/src/util/misc.rs

@@ -612,3 +612,43 @@ impl std::borrow::Borrow<str> for InternedStrCompareAsStr {
         &self.0
     }
 }
+
+pub(crate) fn copy_le_bytes_to_bitslice(
+    dest: &mut BitSlice<usize, Lsb0>,
+    bytes: &[u8],
+    msb_fill: bool,
+) {
+    let (chunks, remainder) = bytes.as_chunks();
+    let mut filled_to = 0;
+    for (i, chunk) in chunks.iter().enumerate() {
+        if let Some(start_bit_index) = i.checked_mul(usize::BITS as usize)
+            && start_bit_index < dest.len()
+        {
+            let end_bit_index = start_bit_index
+                .saturating_add(usize::BITS as usize)
+                .min(dest.len());
+            let bit_len = end_bit_index - start_bit_index;
+            let chunk = usize::from_le_bytes(*chunk);
+            dest[start_bit_index..end_bit_index].copy_from_bitslice(&chunk.view_bits()[..bit_len]);
+            filled_to = end_bit_index;
+        } else {
+            break;
+        }
+    }
+    if !remainder.is_empty() {
+        if let Some(start_bit_index) = chunks.len().checked_mul(usize::BITS as usize)
+            && start_bit_index < dest.len()
+        {
+            let end_bit_index = start_bit_index
+                .saturating_add(usize::BITS as usize)
+                .min(dest.len());
+            let bit_len = end_bit_index - start_bit_index;
+            let mut chunk = [if msb_fill { !0 } else { 0 }; _];
+            chunk[..remainder.len()].copy_from_slice(remainder);
+            let chunk = usize::from_le_bytes(chunk);
+            dest[start_bit_index..end_bit_index].copy_from_bitslice(&chunk.view_bits()[..bit_len]);
+            filled_to = end_bit_index;
+        }
+    }
+    dest[filled_to..].fill(msb_fill);
+}

crates/fayalite/tests/hdl_types.rs

@@ -244,3 +244,13 @@ pub struct MyTypeWithPrivateMembersWithArg<T> {
     pub(crate) b: MyPubCrateTypeWithArg<T>,
     pub c: T,
 }
+
+#[hdl(outline_generated)]
+pub enum EnumWithOnlyOneVariant {
+    A,
+}
+
+#[hdl(outline_generated)]
+pub enum EnumWithOnlyOneVariant2<T> {
+    A(T),
+}

crates/fayalite/tests/sim.rs

@@ -7,7 +7,7 @@ use fayalite::{
     prelude::*,
     reset::ResetType,
     sim::vcd::VcdWriterDecls,
-    util::RcWriter,
+    util::{RcWriter, ready_valid::queue},
 };
 use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc};
 
@@ -2495,3 +2495,349 @@ fn test_sim_read_past() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated)]
+pub fn last_connect() {
+    #[hdl]
+    let inp: HdlOption<Array<Bool, 4>> = m.input();
+    #[hdl]
+    let out: HdlOption<UInt<8>> = m.output();
+    connect(out, HdlNone());
+    #[hdl]
+    if let HdlSome(v) = inp {
+        #[hdl]
+        let w = wire();
+        connect(out, HdlSome(w));
+        connect(w, v.len() as u8);
+        for (i, v) in v.into_iter().enumerate() {
+            #[hdl]
+            if v {
+                connect(w, i as u8);
+            }
+        }
+    }
+}
+
+#[hdl]
+#[test]
+fn test_last_connect() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(last_connect());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    let bools = [false, true];
+    sim.write(sim.io().inp, HdlNone());
+    sim.advance_time(SimDuration::from_micros(1));
+    let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
+    HdlNone();
+    assert_eq!(sim.read(sim.io().out), expected);
+    for a in bools {
+        for b in bools {
+            for c in bools {
+                for d in bools {
+                    let inp = [a, b, c, d];
+                    sim.write(sim.io().inp, HdlSome(inp));
+                    sim.advance_time(SimDuration::from_micros(1));
+                    let mut expected = inp.len() as u8;
+                    for (i, v) in inp.into_iter().enumerate() {
+                        if v {
+                            expected = i as u8;
+                        }
+                    }
+                    let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
+                    HdlSome(expected);
+                    let out = sim.read(sim.io().out);
+                    println!("expected={expected:?} out={out:?} inp={inp:?}");
+                    assert_eq!(expected, out);
+                }
+            }
+        }
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/last_connect.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/last_connect.txt") {
+        panic!();
+    }
+}
+
+#[track_caller]
+#[hdl]
+fn test_queue_helper(
+    capacity: usize,
+    inp_ready_is_comb: bool,
+    out_valid_is_comb: bool,
+    expected_vcd: &str,
+    expected_sim_debug: &str,
+) {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(queue(
+        UInt::<8>::new_static(),
+        NonZeroUsize::new(capacity).expect("capacity should be non-zero"),
+        inp_ready_is_comb,
+        out_valid_is_comb,
+    ));
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    let mut input_value = 0u8;
+    let mut expected_output_value = 0u8;
+    /// deterministic random numbers
+    fn rand(mut v: u32) -> bool {
+        // random 32-bit primes
+        v = v.wrapping_mul(0xF807B7EF).rotate_left(16);
+        v ^= 0xA1E24BBA; // random 32-bit constant
+        v = v.wrapping_mul(0xE9D30017).rotate_left(16);
+        v = v.wrapping_mul(0x3895AFFB).rotate_left(16);
+        v & 1 != 0
+    }
+    for cycle in 0..100u32 {
+        println!("cycle: {cycle}");
+        sim.write(
+            sim.io().inp.data,
+            if rand(cycle) {
+                #[hdl(sim)]
+                HdlSome(input_value)
+            } else {
+                #[hdl(sim)]
+                HdlNone()
+            },
+        );
+        sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle));
+        sim.advance_time(SimDuration::from_nanos(500));
+        if !sim.read_reset(sim.io().cd.rst) {
+            let inp_ready = sim.read_bool(sim.io().inp.ready);
+            if inp_ready {
+                #[hdl(sim)]
+                if let HdlSome(v) = sim.read(sim.io().inp.data) {
+                    println!("enqueued {v}, expected {input_value:#x}");
+                    assert_eq!(v.as_int(), input_value);
+                    input_value = input_value.wrapping_add(1);
+                }
+            }
+            let out_valid = #[hdl(sim)]
+            if let HdlSome(v) = sim.read(sim.io().out.data) {
+                if sim.read_bool(sim.io().out.ready) {
+                    println!("dequeued {v}, expected {expected_output_value:#x}");
+                    assert_eq!(v.as_int(), expected_output_value);
+                    expected_output_value = expected_output_value.wrapping_add(1);
+                }
+                true
+            } else {
+                false
+            };
+            assert!(inp_ready || out_valid, "queue isn't making progress");
+        }
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != expected_vcd {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != expected_sim_debug {
+        panic!();
+    }
+}
+
+#[test]
+fn test_queue_1_false_false() {
+    test_queue_helper(
+        1,
+        false,
+        false,
+        include_str!("sim/expected/queue_1_false_false.vcd"),
+        include_str!("sim/expected/queue_1_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_false_true() {
+    test_queue_helper(
+        1,
+        false,
+        true,
+        include_str!("sim/expected/queue_1_false_true.vcd"),
+        include_str!("sim/expected/queue_1_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_true_false() {
+    test_queue_helper(
+        1,
+        true,
+        false,
+        include_str!("sim/expected/queue_1_true_false.vcd"),
+        include_str!("sim/expected/queue_1_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_1_true_true() {
+    test_queue_helper(
+        1,
+        true,
+        true,
+        include_str!("sim/expected/queue_1_true_true.vcd"),
+        include_str!("sim/expected/queue_1_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_false_false() {
+    test_queue_helper(
+        2,
+        false,
+        false,
+        include_str!("sim/expected/queue_2_false_false.vcd"),
+        include_str!("sim/expected/queue_2_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_false_true() {
+    test_queue_helper(
+        2,
+        false,
+        true,
+        include_str!("sim/expected/queue_2_false_true.vcd"),
+        include_str!("sim/expected/queue_2_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_true_false() {
+    test_queue_helper(
+        2,
+        true,
+        false,
+        include_str!("sim/expected/queue_2_true_false.vcd"),
+        include_str!("sim/expected/queue_2_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_2_true_true() {
+    test_queue_helper(
+        2,
+        true,
+        true,
+        include_str!("sim/expected/queue_2_true_true.vcd"),
+        include_str!("sim/expected/queue_2_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_false_false() {
+    test_queue_helper(
+        3,
+        false,
+        false,
+        include_str!("sim/expected/queue_3_false_false.vcd"),
+        include_str!("sim/expected/queue_3_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_false_true() {
+    test_queue_helper(
+        3,
+        false,
+        true,
+        include_str!("sim/expected/queue_3_false_true.vcd"),
+        include_str!("sim/expected/queue_3_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_true_false() {
+    test_queue_helper(
+        3,
+        true,
+        false,
+        include_str!("sim/expected/queue_3_true_false.vcd"),
+        include_str!("sim/expected/queue_3_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_3_true_true() {
+    test_queue_helper(
+        3,
+        true,
+        true,
+        include_str!("sim/expected/queue_3_true_true.vcd"),
+        include_str!("sim/expected/queue_3_true_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_false_false() {
+    test_queue_helper(
+        4,
+        false,
+        false,
+        include_str!("sim/expected/queue_4_false_false.vcd"),
+        include_str!("sim/expected/queue_4_false_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_false_true() {
+    test_queue_helper(
+        4,
+        false,
+        true,
+        include_str!("sim/expected/queue_4_false_true.vcd"),
+        include_str!("sim/expected/queue_4_false_true.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_true_false() {
+    test_queue_helper(
+        4,
+        true,
+        false,
+        include_str!("sim/expected/queue_4_true_false.vcd"),
+        include_str!("sim/expected/queue_4_true_false.txt"),
+    );
+}
+
+#[test]
+fn test_queue_4_true_true() {
+    test_queue_helper(
+        4,
+        true,
+        true,
+        include_str!("sim/expected/queue_4_true_true.vcd"),
+        include_str!("sim/expected/queue_4_true_true.txt"),
+    );
+}

crates/fayalite/tests/sim/expected/array_rw.vcd

@@ -1,283 +1,283 @@
 $timescale 1 ps $end
 $scope module array_rw $end
 $scope struct array_in $end
-$var wire 8 ! \[0] $end
-$var wire 8 " \[1] $end
-$var wire 8 # \[2] $end
-$var wire 8 $ \[3] $end
-$var wire 8 % \[4] $end
-$var wire 8 & \[5] $end
-$var wire 8 ' \[6] $end
-$var wire 8 ( \[7] $end
-$var wire 8 ) \[8] $end
-$var wire 8 * \[9] $end
-$var wire 8 + \[10] $end
-$var wire 8 , \[11] $end
-$var wire 8 - \[12] $end
-$var wire 8 . \[13] $end
-$var wire 8 / \[14] $end
-$var wire 8 0 \[15] $end
+$var wire 8 Yvfu^ \[0] $end
+$var wire 8 |Cs`W \[1] $end
+$var wire 8 M!nsb \[2] $end
+$var wire 8 59L{w \[3] $end
+$var wire 8 o2+|F \[4] $end
+$var wire 8 ikzV5 \[5] $end
+$var wire 8 [E$Z* \[6] $end
+$var wire 8 ?"~01 \[7] $end
+$var wire 8 /kghT \[8] $end
+$var wire 8 +}(9) \[9] $end
+$var wire 8 iMP}= \[10] $end
+$var wire 8 2M0tL \[11] $end
+$var wire 8 :AjkA \[12] $end
+$var wire 8 VM_:8 \[13] $end
+$var wire 8 UveL2 \[14] $end
+$var wire 8 A)9Z6 \[15] $end
 $upscope $end
 $scope struct array_out $end
-$var wire 8 1 \[0] $end
-$var wire 8 2 \[1] $end
-$var wire 8 3 \[2] $end
-$var wire 8 4 \[3] $end
-$var wire 8 5 \[4] $end
-$var wire 8 6 \[5] $end
-$var wire 8 7 \[6] $end
-$var wire 8 8 \[7] $end
-$var wire 8 9 \[8] $end
-$var wire 8 : \[9] $end
-$var wire 8 ; \[10] $end
-$var wire 8 < \[11] $end
-$var wire 8 = \[12] $end
-$var wire 8 > \[13] $end
-$var wire 8 ? \[14] $end
-$var wire 8 @ \[15] $end
+$var wire 8 2zdj1 \[0] $end
+$var wire 8 =;m_[ \[1] $end
+$var wire 8 @9Hd \[2] $end
+$var wire 8 C:="| \[3] $end
+$var wire 8 IDk7# \[4] $end
+$var wire 8 i]E1i \[5] $end
+$var wire 8 tK,M] \[6] $end
+$var wire 8 tGp!\ \[7] $end
+$var wire 8 ."qjK \[8] $end
+$var wire 8 AUO:R \[9] $end
+$var wire 8 'kx`n \[10] $end
+$var wire 8 U&(K\ \[11] $end
+$var wire 8 q<O41 \[12] $end
+$var wire 8 zvj)] \[13] $end
+$var wire 8 >0H<( \[14] $end
+$var wire 8 ARhXJ \[15] $end
 $upscope $end
-$var wire 8 A read_index $end
-$var wire 8 B read_data $end
-$var wire 8 C write_index $end
-$var wire 8 D write_data $end
-$var wire 1 E write_en $end
+$var wire 8 -n:7@ read_index $end
+$var wire 8 >h<=Z read_data $end
+$var wire 8 [xld3 write_index $end
+$var wire 8 J+DYh write_data $end
+$var wire 1 z,@WW write_en $end
 $scope struct array_wire $end
-$var wire 8 F \[0] $end
-$var wire 8 G \[1] $end
-$var wire 8 H \[2] $end
-$var wire 8 I \[3] $end
-$var wire 8 J \[4] $end
-$var wire 8 K \[5] $end
-$var wire 8 L \[6] $end
-$var wire 8 M \[7] $end
-$var wire 8 N \[8] $end
-$var wire 8 O \[9] $end
-$var wire 8 P \[10] $end
-$var wire 8 Q \[11] $end
-$var wire 8 R \[12] $end
-$var wire 8 S \[13] $end
-$var wire 8 T \[14] $end
-$var wire 8 U \[15] $end
+$var wire 8 B{KJS \[0] $end
+$var wire 8 V'K*& \[1] $end
+$var wire 8 4zI$O \[2] $end
+$var wire 8 %TTk[ \[3] $end
+$var wire 8 IgSeY \[4] $end
+$var wire 8 &&1T" \[5] $end
+$var wire 8 5)-l\ \[6] $end
+$var wire 8 0RsLb \[7] $end
+$var wire 8 T>:}D \[8] $end
+$var wire 8 DPpZ* \[9] $end
+$var wire 8 %E(nf \[10] $end
+$var wire 8 2'pba \[11] $end
+$var wire 8 e/c1: \[12] $end
+$var wire 8 ;w.C7 \[13] $end
+$var wire 8 fwdfu \[14] $end
+$var wire 8 *R\vx \[15] $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-b11111111 !
-b1111111 "
-b111111 #
-b11111 $
-b1111 %
-b111 &
-b11 '
-b1 (
-b0 )
-b10000000 *
-b11000000 +
-b11100000 ,
-b11110000 -
-b11111000 .
-b11111100 /
-b11111110 0
-b11111111 1
-b1111111 2
-b111111 3
-b11111 4
-b1111 5
-b111 6
-b11 7
-b1 8
-b0 9
-b10000000 :
-b11000000 ;
-b11100000 <
-b11110000 =
-b11111000 >
-b11111100 ?
-b11111110 @
-b0 A
-b11111111 B
-b0 C
-b0 D
-0E
-b11111111 F
-b1111111 G
-b111111 H
-b11111 I
-b1111 J
-b111 K
-b11 L
-b1 M
-b0 N
-b10000000 O
-b11000000 P
-b11100000 Q
-b11110000 R
-b11111000 S
-b11111100 T
-b11111110 U
+b11111111 Yvfu^
+b1111111 |Cs`W
+b111111 M!nsb
+b11111 59L{w
+b1111 o2+|F
+b111 ikzV5
+b11 [E$Z*
+b1 ?"~01
+b0 /kghT
+b10000000 +}(9)
+b11000000 iMP}=
+b11100000 2M0tL
+b11110000 :AjkA
+b11111000 VM_:8
+b11111100 UveL2
+b11111110 A)9Z6
+b11111111 2zdj1
+b1111111 =;m_[
+b111111 @9Hd
+b11111 C:="|
+b1111 IDk7#
+b111 i]E1i
+b11 tK,M]
+b1 tGp!\
+b0 ."qjK
+b10000000 AUO:R
+b11000000 'kx`n
+b11100000 U&(K\
+b11110000 q<O41
+b11111000 zvj)]
+b11111100 >0H<(
+b11111110 ARhXJ
+b0 -n:7@
+b11111111 >h<=Z
+b0 [xld3
+b0 J+DYh
+0z,@WW
+b11111111 B{KJS
+b1111111 V'K*&
+b111111 4zI$O
+b11111 %TTk[
+b1111 IgSeY
+b111 &&1T"
+b11 5)-l\
+b1 0RsLb
+b0 T>:}D
+b10000000 DPpZ*
+b11000000 %E(nf
+b11100000 2'pba
+b11110000 e/c1:
+b11111000 ;w.C7
+b11111100 fwdfu
+b11111110 *R\vx
 $end
 #1000000
-b1 A
-b1111111 B
+b1 -n:7@
+b1111111 >h<=Z
 #2000000
-b10 A
-b111111 B
+b10 -n:7@
+b111111 >h<=Z
 #3000000
-b11 A
-b11111 B
+b11 -n:7@
+b11111 >h<=Z
 #4000000
-b100 A
-b1111 B
+b100 -n:7@
+b1111 >h<=Z
 #5000000
-b101 A
-b111 B
+b101 -n:7@
+b111 >h<=Z
 #6000000
-b110 A
-b11 B
+b110 -n:7@
+b11 >h<=Z
 #7000000
-b111 A
-b1 B
+b111 -n:7@
+b1 >h<=Z
 #8000000
-b1000 A
-b0 B
+b1000 -n:7@
+b0 >h<=Z
 #9000000
-b1001 A
-b10000000 B
+b1001 -n:7@
+b10000000 >h<=Z
 #10000000
-b1010 A
-b11000000 B
+b1010 -n:7@
+b11000000 >h<=Z
 #11000000
-b1011 A
-b11100000 B
+b1011 -n:7@
+b11100000 >h<=Z
 #12000000
-b1100 A
-b11110000 B
+b1100 -n:7@
+b11110000 >h<=Z
 #13000000
-b1101 A
-b11111000 B
+b1101 -n:7@
+b11111000 >h<=Z
 #14000000
-b1110 A
-b11111100 B
+b1110 -n:7@
+b11111100 >h<=Z
 #15000000
-b1111 A
-b11111110 B
+b1111 -n:7@
+b11111110 >h<=Z
 #16000000
-b10000 A
-b0 B
+b10000 -n:7@
+b0 >h<=Z
 #17000000
-b0 1
-b0 A
-1E
-b0 F
+b0 2zdj1
+b0 -n:7@
+1z,@WW
+b0 B{KJS
 #18000000
-b11111111 1
-b1 2
-b11111111 B
-b1 C
-b1 D
-b11111111 F
-b1 G
+b11111111 2zdj1
+b1 =;m_[
+b11111111 >h<=Z
+b1 [xld3
+b1 J+DYh
+b11111111 B{KJS
+b1 V'K*&
 #19000000
-b1111111 2
-b100 3
-b10 C
-b100 D
-b1111111 G
-b100 H
+b1111111 =;m_[
+b100 @9Hd
+b10 [xld3
+b100 J+DYh
+b1111111 V'K*&
+b100 4zI$O
 #20000000
-b111111 3
-b1001 4
-b11 C
-b1001 D
-b111111 H
-b1001 I
+b111111 @9Hd
+b1001 C:="|
+b11 [xld3
+b1001 J+DYh
+b111111 4zI$O
+b1001 %TTk[
 #21000000
-b11111 4
-b10000 5
-b100 C
-b10000 D
-b11111 I
-b10000 J
+b11111 C:="|
+b10000 IDk7#
+b100 [xld3
+b10000 J+DYh
+b11111 %TTk[
+b10000 IgSeY
 #22000000
-b1111 5
-b11001 6
-b101 C
-b11001 D
-b1111 J
-b11001 K
+b1111 IDk7#
+b11001 i]E1i
+b101 [xld3
+b11001 J+DYh
+b1111 IgSeY
+b11001 &&1T"
 #23000000
-b111 6
-b100100 7
-b110 C
-b100100 D
-b111 K
-b100100 L
+b111 i]E1i
+b100100 tK,M]
+b110 [xld3
+b100100 J+DYh
+b111 &&1T"
+b100100 5)-l\
 #24000000
-b11 7
-b110001 8
-b111 C
-b110001 D
-b11 L
-b110001 M
+b11 tK,M]
+b110001 tGp!\
+b111 [xld3
+b110001 J+DYh
+b11 5)-l\
+b110001 0RsLb
 #25000000
-b1 8
-b1000000 9
-b1000 C
-b1000000 D
-b1 M
-b1000000 N
+b1 tGp!\
+b1000000 ."qjK
+b1000 [xld3
+b1000000 J+DYh
+b1 0RsLb
+b1000000 T>:}D
 #26000000
-b0 9
-b1010001 :
-b1001 C
-b1010001 D
-b0 N
-b1010001 O
+b0 ."qjK
+b1010001 AUO:R
+b1001 [xld3
+b1010001 J+DYh
+b0 T>:}D
+b1010001 DPpZ*
 #27000000
-b10000000 :
-b1100100 ;
-b1010 C
-b1100100 D
-b10000000 O
-b1100100 P
+b10000000 AUO:R
+b1100100 'kx`n
+b1010 [xld3
+b1100100 J+DYh
+b10000000 DPpZ*
+b1100100 %E(nf
 #28000000
-b11000000 ;
-b1111001 <
-b1011 C
-b1111001 D
-b11000000 P
-b1111001 Q
+b11000000 'kx`n
+b1111001 U&(K\
+b1011 [xld3
+b1111001 J+DYh
+b11000000 %E(nf
+b1111001 2'pba
 #29000000
-b11100000 <
-b10010000 =
-b1100 C
-b10010000 D
-b11100000 Q
-b10010000 R
+b11100000 U&(K\
+b10010000 q<O41
+b1100 [xld3
+b10010000 J+DYh
+b11100000 2'pba
+b10010000 e/c1:
 #30000000
-b11110000 =
-b10101001 >
-b1101 C
-b10101001 D
-b11110000 R
-b10101001 S
+b11110000 q<O41
+b10101001 zvj)]
+b1101 [xld3
+b10101001 J+DYh
+b11110000 e/c1:
+b10101001 ;w.C7
 #31000000
-b11111000 >
-b11000100 ?
-b1110 C
-b11000100 D
-b11111000 S
-b11000100 T
+b11111000 zvj)]
+b11000100 >0H<(
+b1110 [xld3
+b11000100 J+DYh
+b11111000 ;w.C7
+b11000100 fwdfu
 #32000000
-b11111100 ?
-b11100001 @
-b1111 C
-b11100001 D
-b11111100 T
-b11100001 U
+b11111100 >0H<(
+b11100001 ARhXJ
+b1111 [xld3
+b11100001 J+DYh
+b11111100 fwdfu
+b11100001 *R\vx
 #33000000
-b11111110 @
-b10000 C
-b0 D
-b11111110 U
+b11111110 ARhXJ
+b10000 [xld3
+b0 J+DYh
+b11111110 *R\vx
 #34000000

crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd

@@ -1,14 +1,14 @@
 $timescale 1 ps $end
 $scope module conditional_assignment_last $end
-$var wire 1 ! i $end
-$var wire 1 " w $end
+$var wire 1 xt~(W i $end
+$var wire 1 6:7im w $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
+0xt~(W
+16:7im
 $end
 #1000000
-1!
-0"
+1xt~(W
+06:7im
 #2000000

crates/fayalite/tests/sim/expected/connect_const_reset.vcd

@@ -1,11 +1,11 @@
 $timescale 1 ps $end
 $scope module connect_const_reset $end
-$var wire 1 ! reset_out $end
-$var wire 1 " bit_out $end
+$var wire 1 8ke|= reset_out $end
+$var wire 1 {"c@= bit_out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-1!
-1"
+18ke|=
+1{"c@=
 $end
 #1000000

crates/fayalite/tests/sim/expected/counter_async.txt

@@ -123,58 +123,62 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                8: Add {
+                9: Add {
                     dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                9: CastToUInt {
+                10: CastToUInt {
                     dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                10: Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                11: Copy {
+                12: Copy {
                     dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                12: BranchIfSmallNonZero {
-                    target: 16,
+                13: BranchIfSmallNonZero {
+                    target: 17,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                13: BranchIfSmallZero {
-                    target: 17,
+                14: BranchIfSmallZero {
+                    target: 18,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                14: Copy {
+                15: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                15: Branch {
-                    target: 17,
+                16: Branch {
+                    target: 18,
                 },
-                16: Copy {
+                17: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                17: XorSmallImmediate {
+                18: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                18: Return,
+                19: Return,
             ],
             ..
         },
-        pc: 18,
+        pc: 19,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/counter_async.vcd

@@ -1,217 +1,217 @@
 $timescale 1 ps $end
 $scope module counter $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 `[J;" clk $end
+$var wire 1 4pZx7 rst $end
 $upscope $end
-$var wire 4 # count $end
-$var reg 4 $ count_reg $end
+$var wire 4 rPs;{ count $end
+$var reg 4 6_+(g count_reg $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-0"
-b0 #
-b0 $
+0`[J;"
+04pZx7
+b0 rPs;{
+b0 6_+(g
 $end
 #500000
-1"
-b11 #
-b11 $
+14pZx7
+b11 rPs;{
+b11 6_+(g
 #1000000
-1!
+1`[J;"
 #1500000
-0"
+04pZx7
 #2000000
-0!
+0`[J;"
 #3000000
-1!
-b100 #
-b100 $
+1`[J;"
+b100 rPs;{
+b100 6_+(g
 #4000000
-0!
+0`[J;"
 #5000000
-1!
-b101 #
-b101 $
+1`[J;"
+b101 rPs;{
+b101 6_+(g
 #6000000
-0!
+0`[J;"
 #7000000
-1!
-b110 #
-b110 $
+1`[J;"
+b110 rPs;{
+b110 6_+(g
 #8000000
-0!
+0`[J;"
 #9000000
-1!
-b111 #
-b111 $
+1`[J;"
+b111 rPs;{
+b111 6_+(g
 #10000000
-0!
+0`[J;"
 #11000000
-1!
-b1000 #
-b1000 $
+1`[J;"
+b1000 rPs;{
+b1000 6_+(g
 #12000000
-0!
+0`[J;"
 #13000000
-1!
-b1001 #
-b1001 $
+1`[J;"
+b1001 rPs;{
+b1001 6_+(g
 #14000000
-0!
+0`[J;"
 #15000000
-1!
-b1010 #
-b1010 $
+1`[J;"
+b1010 rPs;{
+b1010 6_+(g
 #16000000
-0!
+0`[J;"
 #17000000
-1!
-b1011 #
-b1011 $
+1`[J;"
+b1011 rPs;{
+b1011 6_+(g
 #18000000
-0!
+0`[J;"
 #19000000
-1!
-b1100 #
-b1100 $
+1`[J;"
+b1100 rPs;{
+b1100 6_+(g
 #20000000
-0!
+0`[J;"
 #21000000
-1!
-b1101 #
-b1101 $
+1`[J;"
+b1101 rPs;{
+b1101 6_+(g
 #22000000
-0!
+0`[J;"
 #23000000
-1!
-b1110 #
-b1110 $
+1`[J;"
+b1110 rPs;{
+b1110 6_+(g
 #24000000
-0!
+0`[J;"
 #25000000
-1!
-b1111 #
-b1111 $
+1`[J;"
+b1111 rPs;{
+b1111 6_+(g
 #26000000
-0!
+0`[J;"
 #27000000
-1!
-b0 #
-b0 $
+1`[J;"
+b0 rPs;{
+b0 6_+(g
 #28000000
-0!
+0`[J;"
 #29000000
-1!
-b1 #
-b1 $
+1`[J;"
+b1 rPs;{
+b1 6_+(g
 #30000000
-0!
+0`[J;"
 #31000000
-1!
-b10 #
-b10 $
+1`[J;"
+b10 rPs;{
+b10 6_+(g
 #32000000
-0!
+0`[J;"
 #33000000
-1!
-b11 #
-b11 $
+1`[J;"
+b11 rPs;{
+b11 6_+(g
 #34000000
-0!
+0`[J;"
 #35000000
-1!
-b100 #
-b100 $
+1`[J;"
+b100 rPs;{
+b100 6_+(g
 #36000000
-0!
+0`[J;"
 #37000000
-1!
-b101 #
-b101 $
+1`[J;"
+b101 rPs;{
+b101 6_+(g
 #38000000
-0!
+0`[J;"
 #39000000
-1!
-b110 #
-b110 $
+1`[J;"
+b110 rPs;{
+b110 6_+(g
 #40000000
-0!
+0`[J;"
 #41000000
-1!
-b111 #
-b111 $
+1`[J;"
+b111 rPs;{
+b111 6_+(g
 #42000000
-0!
+0`[J;"
 #43000000
-1!
-b1000 #
-b1000 $
+1`[J;"
+b1000 rPs;{
+b1000 6_+(g
 #44000000
-0!
+0`[J;"
 #45000000
-1!
-b1001 #
-b1001 $
+1`[J;"
+b1001 rPs;{
+b1001 6_+(g
 #46000000
-0!
+0`[J;"
 #47000000
-1!
-b1010 #
-b1010 $
+1`[J;"
+b1010 rPs;{
+b1010 6_+(g
 #48000000
-0!
+0`[J;"
 #49000000
-1!
-b1011 #
-b1011 $
+1`[J;"
+b1011 rPs;{
+b1011 6_+(g
 #50000000
-0!
+0`[J;"
 #51000000
-1!
-b1100 #
-b1100 $
+1`[J;"
+b1100 rPs;{
+b1100 6_+(g
 #52000000
-0!
+0`[J;"
 #53000000
-1!
-b1101 #
-b1101 $
+1`[J;"
+b1101 rPs;{
+b1101 6_+(g
 #54000000
-0!
+0`[J;"
 #55000000
-1!
-b1110 #
-b1110 $
+1`[J;"
+b1110 rPs;{
+b1110 6_+(g
 #56000000
-0!
+0`[J;"
 #57000000
-1!
-b1111 #
-b1111 $
+1`[J;"
+b1111 rPs;{
+b1111 6_+(g
 #58000000
-0!
+0`[J;"
 #59000000
-1!
-b0 #
-b0 $
+1`[J;"
+b0 rPs;{
+b0 6_+(g
 #60000000
-0!
+0`[J;"
 #61000000
-1!
-b1 #
-b1 $
+1`[J;"
+b1 rPs;{
+b1 6_+(g
 #62000000
-0!
+0`[J;"
 #63000000
-1!
-b10 #
-b10 $
+1`[J;"
+b10 rPs;{
+b10 6_+(g
 #64000000
-0!
+0`[J;"
 #65000000
-1!
-b11 #
-b11 $
+1`[J;"
+b11 rPs;{
+b11 6_+(g
 #66000000

crates/fayalite/tests/sim/expected/counter_sync.txt

@@ -102,61 +102,65 @@ Simulation {
                     src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
-                // at: module-XXXXXXXXXX.rs:4:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                },
                 // at: module-XXXXXXXXXX.rs:3:1
-                5: IsNonZeroDestIsSmall {
+                4: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
                 },
-                6: IsNonZeroDestIsSmall {
+                5: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
-                7: AndSmall {
+                6: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                8: Const {
+                9: Const {
                     dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                     value: 0x3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                9: BranchIfSmallZero {
-                    target: 14,
+                10: BranchIfSmallZero {
+                    target: 15,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                10: BranchIfSmallNonZero {
-                    target: 13,
+                11: BranchIfSmallNonZero {
+                    target: 14,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                11: Copy {
+                12: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                12: Branch {
-                    target: 14,
+                13: Branch {
+                    target: 15,
                 },
-                13: Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                14: XorSmallImmediate {
+                15: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                15: Return,
+                16: Return,
             ],
             ..
         },
-        pc: 15,
+        pc: 16,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/counter_sync.vcd

@@ -1,214 +1,214 @@
 $timescale 1 ps $end
 $scope module counter $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 `[J;" clk $end
+$var wire 1 4pZx7 rst $end
 $upscope $end
-$var wire 4 # count $end
-$var reg 4 $ count_reg $end
+$var wire 4 rPs;{ count $end
+$var reg 4 6_+(g count_reg $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
-b0 #
-b0 $
+0`[J;"
+14pZx7
+b0 rPs;{
+b0 6_+(g
 $end
 #1000000
-1!
-b11 #
-b11 $
-0"
+1`[J;"
+b11 rPs;{
+b11 6_+(g
+04pZx7
 #2000000
-0!
+0`[J;"
 #3000000
-1!
-b100 #
-b100 $
+1`[J;"
+b100 rPs;{
+b100 6_+(g
 #4000000
-0!
+0`[J;"
 #5000000
-1!
-b101 #
-b101 $
+1`[J;"
+b101 rPs;{
+b101 6_+(g
 #6000000
-0!
+0`[J;"
 #7000000
-1!
-b110 #
-b110 $
+1`[J;"
+b110 rPs;{
+b110 6_+(g
 #8000000
-0!
+0`[J;"
 #9000000
-1!
-b111 #
-b111 $
+1`[J;"
+b111 rPs;{
+b111 6_+(g
 #10000000
-0!
+0`[J;"
 #11000000
-1!
-b1000 #
-b1000 $
+1`[J;"
+b1000 rPs;{
+b1000 6_+(g
 #12000000
-0!
+0`[J;"
 #13000000
-1!
-b1001 #
-b1001 $
+1`[J;"
+b1001 rPs;{
+b1001 6_+(g
 #14000000
-0!
+0`[J;"
 #15000000
-1!
-b1010 #
-b1010 $
+1`[J;"
+b1010 rPs;{
+b1010 6_+(g
 #16000000
-0!
+0`[J;"
 #17000000
-1!
-b1011 #
-b1011 $
+1`[J;"
+b1011 rPs;{
+b1011 6_+(g
 #18000000
-0!
+0`[J;"
 #19000000
-1!
-b1100 #
-b1100 $
+1`[J;"
+b1100 rPs;{
+b1100 6_+(g
 #20000000
-0!
+0`[J;"
 #21000000
-1!
-b1101 #
-b1101 $
+1`[J;"
+b1101 rPs;{
+b1101 6_+(g
 #22000000
-0!
+0`[J;"
 #23000000
-1!
-b1110 #
-b1110 $
+1`[J;"
+b1110 rPs;{
+b1110 6_+(g
 #24000000
-0!
+0`[J;"
 #25000000
-1!
-b1111 #
-b1111 $
+1`[J;"
+b1111 rPs;{
+b1111 6_+(g
 #26000000
-0!
+0`[J;"
 #27000000
-1!
-b0 #
-b0 $
+1`[J;"
+b0 rPs;{
+b0 6_+(g
 #28000000
-0!
+0`[J;"
 #29000000
-1!
-b1 #
-b1 $
+1`[J;"
+b1 rPs;{
+b1 6_+(g
 #30000000
-0!
+0`[J;"
 #31000000
-1!
-b10 #
-b10 $
+1`[J;"
+b10 rPs;{
+b10 6_+(g
 #32000000
-0!
+0`[J;"
 #33000000
-1!
-b11 #
-b11 $
+1`[J;"
+b11 rPs;{
+b11 6_+(g
 #34000000
-0!
+0`[J;"
 #35000000
-1!
-b100 #
-b100 $
+1`[J;"
+b100 rPs;{
+b100 6_+(g
 #36000000
-0!
+0`[J;"
 #37000000
-1!
-b101 #
-b101 $
+1`[J;"
+b101 rPs;{
+b101 6_+(g
 #38000000
-0!
+0`[J;"
 #39000000
-1!
-b110 #
-b110 $
+1`[J;"
+b110 rPs;{
+b110 6_+(g
 #40000000
-0!
+0`[J;"
 #41000000
-1!
-b111 #
-b111 $
+1`[J;"
+b111 rPs;{
+b111 6_+(g
 #42000000
-0!
+0`[J;"
 #43000000
-1!
-b1000 #
-b1000 $
+1`[J;"
+b1000 rPs;{
+b1000 6_+(g
 #44000000
-0!
+0`[J;"
 #45000000
-1!
-b1001 #
-b1001 $
+1`[J;"
+b1001 rPs;{
+b1001 6_+(g
 #46000000
-0!
+0`[J;"
 #47000000
-1!
-b1010 #
-b1010 $
+1`[J;"
+b1010 rPs;{
+b1010 6_+(g
 #48000000
-0!
+0`[J;"
 #49000000
-1!
-b1011 #
-b1011 $
+1`[J;"
+b1011 rPs;{
+b1011 6_+(g
 #50000000
-0!
+0`[J;"
 #51000000
-1!
-b1100 #
-b1100 $
+1`[J;"
+b1100 rPs;{
+b1100 6_+(g
 #52000000
-0!
+0`[J;"
 #53000000
-1!
-b1101 #
-b1101 $
+1`[J;"
+b1101 rPs;{
+b1101 6_+(g
 #54000000
-0!
+0`[J;"
 #55000000
-1!
-b1110 #
-b1110 $
+1`[J;"
+b1110 rPs;{
+b1110 6_+(g
 #56000000
-0!
+0`[J;"
 #57000000
-1!
-b1111 #
-b1111 $
+1`[J;"
+b1111 rPs;{
+b1111 6_+(g
 #58000000
-0!
+0`[J;"
 #59000000
-1!
-b0 #
-b0 $
+1`[J;"
+b0 rPs;{
+b0 6_+(g
 #60000000
-0!
+0`[J;"
 #61000000
-1!
-b1 #
-b1 $
+1`[J;"
+b1 rPs;{
+b1 6_+(g
 #62000000
-0!
+0`[J;"
 #63000000
-1!
-b10 #
-b10 $
+1`[J;"
+b10 rPs;{
+b10 6_+(g
 #64000000
-0!
+0`[J;"
 #65000000
-1!
-b11 #
-b11 $
+1`[J;"
+b11 rPs;{
+b11 6_+(g
 #66000000

crates/fayalite/tests/sim/expected/duplicate_names.vcd

@@ -1,11 +1,11 @@
 $timescale 1 ps $end
 $scope module duplicate_names $end
-$var wire 8 ! w $end
-$var wire 8 " w_2 $end
+$var wire 8 7[_7. w $end
+$var wire 8 7[_7." w_2 $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-b101 !
-b110 "
+b101 7[_7.
+b110 7[_7."
 $end
 #1000000

crates/fayalite/tests/sim/expected/enums.txt

@@ -1012,173 +1012,177 @@ Simulation {
                     lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
+                99: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                99: Const {
+                100: Const {
                     dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     value: 0x0,
                 },
-                100: Copy {
+                101: Copy {
                     dest: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
-                101: BranchIfZero {
-                    target: 109,
+                102: BranchIfZero {
+                    target: 110,
                     value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                102: BranchIfZero {
-                    target: 104,
+                103: BranchIfZero {
+                    target: 105,
                     value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                103: Copy {
+                104: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                104: BranchIfNonZero {
-                    target: 109,
+                105: BranchIfNonZero {
+                    target: 110,
                     value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                105: BranchIfZero {
-                    target: 107,
+                106: BranchIfZero {
+                    target: 108,
                     value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:16:1
-                106: Copy {
+                107: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                107: BranchIfNonZero {
-                    target: 109,
+                108: BranchIfNonZero {
+                    target: 110,
                     value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:17:1
-                108: Copy {
+                109: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                109: Copy {
+                110: Copy {
                     dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                110: Copy {
+                111: Copy {
                     dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
-                111: SliceInt {
+                112: SliceInt {
                     dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     start: 1,
                     len: 2,
                 },
-                112: SliceInt {
+                113: SliceInt {
                     dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                113: SliceInt {
+                114: SliceInt {
                     dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                114: Copy {
+                115: Copy {
                     dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                115: Copy {
+                116: Copy {
                     dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                116: Copy {
+                117: Copy {
                     dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                117: AndBigWithSmallImmediate {
+                118: AndBigWithSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
                     lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                118: Copy {
+                119: Copy {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
-                119: SliceInt {
+                120: SliceInt {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     start: 1,
                     len: 2,
                 },
-                120: SliceInt {
+                121: SliceInt {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                121: SliceInt {
+                122: SliceInt {
                     dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                122: Copy {
+                123: Copy {
                     dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                123: Copy {
+                124: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                124: Copy {
+                125: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                125: AndBigWithSmallImmediate {
+                126: AndBigWithSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
                     lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                126: BranchIfSmallZero {
-                    target: 131,
+                127: BranchIfSmallZero {
+                    target: 132,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                127: BranchIfSmallNonZero {
-                    target: 130,
+                128: BranchIfSmallNonZero {
+                    target: 131,
                     value: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                128: Copy {
+                129: Copy {
                     dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                129: Branch {
-                    target: 131,
+                130: Branch {
+                    target: 132,
                 },
-                130: Copy {
+                131: Copy {
                     dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                131: XorSmallImmediate {
+                132: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                132: Return,
+                133: Return,
             ],
             ..
         },
-        pc: 132,
+        pc: 133,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/enums.vcd

@@ -1,126 +1,126 @@
 $timescale 1 ps $end
 $scope module enums $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 0n\U< clk $end
+$var wire 1 a?A!) rst $end
 $upscope $end
-$var wire 1 # en $end
-$var wire 2 $ which_in $end
-$var wire 4 % data_in $end
-$var wire 2 & which_out $end
-$var wire 4 ' data_out $end
+$var wire 1 #ZQY# en $end
+$var wire 2 8?II+ which_in $end
+$var wire 4 OO,N+ data_in $end
+$var wire 2 yr2gr which_out $end
+$var wire 4 q_O;Y data_out $end
 $scope struct b_out $end
-$var string 1 ( \$tag $end
+$var string 1 7L1gf \$tag $end
 $scope struct HdlSome $end
-$var wire 1 ) \0 $end
-$var wire 1 * \1 $end
+$var wire 1 EO?Ju \0 $end
+$var wire 1 cGtNN \1 $end
 $upscope $end
 $upscope $end
 $scope struct b2_out $end
-$var string 1 + \$tag $end
+$var string 1 dqd@B \$tag $end
 $scope struct HdlSome $end
-$var wire 1 , \0 $end
-$var wire 1 - \1 $end
+$var wire 1 (FG:I \0 $end
+$var wire 1 dzy-= \1 $end
 $upscope $end
 $upscope $end
 $scope struct the_reg $end
-$var string 1 . \$tag $end
+$var string 1 J#9uO \$tag $end
 $scope struct B $end
-$var reg 1 / \0 $end
-$var reg 1 0 \1 $end
+$var reg 1 ca2Gh \0 $end
+$var reg 1 f)r)? \1 $end
 $upscope $end
 $scope struct C $end
 $scope struct a $end
-$var reg 1 1 \[0] $end
-$var reg 1 2 \[1] $end
+$var reg 1 ;BepJ \[0] $end
+$var reg 1 J~2;e \[1] $end
 $upscope $end
-$var reg 2 3 b $end
+$var reg 2 w\b)K b $end
 $upscope $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
-0#
-b0 $
-b0 %
-b0 &
-b0 '
-sHdlNone\x20(0) (
-0)
-0*
-sHdlNone\x20(0) +
-0,
-0-
-sA\x20(0) .
-0/
-00
-01
-02
-b0 3
+00n\U<
+1a?A!)
+0#ZQY#
+b0 8?II+
+b0 OO,N+
+b0 yr2gr
+b0 q_O;Y
+sHdlNone\x20(0) 7L1gf
+0EO?Ju
+0cGtNN
+sHdlNone\x20(0) dqd@B
+0(FG:I
+0dzy-=
+sA\x20(0) J#9uO
+0ca2Gh
+0f)r)?
+0;BepJ
+0J~2;e
+b0 w\b)K
 $end
 #1000000
-1!
+10n\U<
 #1100000
-0"
+0a?A!)
 #2000000
-0!
+00n\U<
 #3000000
-1!
+10n\U<
 #4000000
-1#
-b1 $
-0!
+1#ZQY#
+b1 8?II+
+00n\U<
 #5000000
-1!
-b1 &
-sHdlSome\x20(1) (
-sHdlSome\x20(1) +
-sB\x20(1) .
+10n\U<
+b1 yr2gr
+sHdlSome\x20(1) 7L1gf
+sHdlSome\x20(1) dqd@B
+sB\x20(1) J#9uO
 #6000000
-0#
-b0 $
-0!
+0#ZQY#
+b0 8?II+
+00n\U<
 #7000000
-1!
+10n\U<
 #8000000
-1#
-b1 $
-b1111 %
-0!
+1#ZQY#
+b1 8?II+
+b1111 OO,N+
+00n\U<
 #9000000
-1!
-b11 '
-1)
-1*
-1,
-1-
-1/
-10
-11
-12
+10n\U<
+b11 q_O;Y
+1EO?Ju
+1cGtNN
+1(FG:I
+1dzy-=
+1ca2Gh
+1f)r)?
+1;BepJ
+1J~2;e
 #10000000
-0!
+00n\U<
 #11000000
-1!
+10n\U<
 #12000000
-b10 $
-0!
+b10 8?II+
+00n\U<
 #13000000
-1!
-b10 &
-b1111 '
-sHdlNone\x20(0) (
-0)
-0*
-sHdlNone\x20(0) +
-0,
-0-
-sC\x20(2) .
-b11 3
+10n\U<
+b10 yr2gr
+b1111 q_O;Y
+sHdlNone\x20(0) 7L1gf
+0EO?Ju
+0cGtNN
+sHdlNone\x20(0) dqd@B
+0(FG:I
+0dzy-=
+sC\x20(2) J#9uO
+b11 w\b)K
 #14000000
-0!
+00n\U<
 #15000000
-1!
+10n\U<
 #16000000

crates/fayalite/tests/sim/expected/extern_module.vcd

@@ -1,52 +1,52 @@
 $timescale 1 ps $end
 $scope module extern_module $end
-$var wire 1 ! i $end
-$var wire 1 " o $end
+$var wire 1 `MLd_ i $end
+$var wire 1 ^;OnJ o $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-0"
+0`MLd_
+0^;OnJ
 $end
-1"
+1^;OnJ
 #500000
 #1500000
-0"
+0^;OnJ
 #2500000
-1"
+1^;OnJ
 #3500000
-0"
+0^;OnJ
 #4500000
-1"
+1^;OnJ
 #5500000
-0"
+0^;OnJ
 #6500000
-1"
+1^;OnJ
 #7500000
-0"
+0^;OnJ
 #8500000
-1"
+1^;OnJ
 #9500000
-0"
+0^;OnJ
 #10000000
-1!
+1`MLd_
 #10500000
 #11500000
-1"
+1^;OnJ
 #12500000
-0"
+0^;OnJ
 #13500000
-1"
+1^;OnJ
 #14500000
-0"
+0^;OnJ
 #15500000
-1"
+1^;OnJ
 #16500000
-0"
+0^;OnJ
 #17500000
-1"
+1^;OnJ
 #18500000
-0"
+0^;OnJ
 #19500000
-1"
+1^;OnJ
 #20000000

crates/fayalite/tests/sim/expected/extern_module2.vcd

@@ -1,151 +1,151 @@
 $timescale 1 ps $end
 $scope module extern_module2 $end
-$var wire 1 ! en $end
-$var wire 1 " clk $end
-$var wire 8 # o $end
+$var wire 1 oHT(x en $end
+$var wire 1 nHT-: clk $end
+$var wire 8 0:wF& o $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-1!
-0"
-b0 #
+1oHT(x
+0nHT-:
+b0 0:wF&
 $end
-b1001000 #
+b1001000 0:wF&
 #1000000
-1"
-b1100101 #
+1nHT-:
+b1100101 0:wF&
 #2000000
-0"
+0nHT-:
 #3000000
-1"
-b1101100 #
+1nHT-:
+b1101100 0:wF&
 #4000000
-0"
+0nHT-:
 #5000000
-1"
+1nHT-:
 #6000000
-0"
+0nHT-:
 #7000000
-1"
-b1101111 #
+1nHT-:
+b1101111 0:wF&
 #8000000
-0"
+0nHT-:
 #9000000
-1"
-b101100 #
+1nHT-:
+b101100 0:wF&
 #10000000
-0!
-0"
+0oHT(x
+0nHT-:
 #11000000
-1"
+1nHT-:
 #12000000
-0"
+0nHT-:
 #13000000
-1"
+1nHT-:
 #14000000
-0"
+0nHT-:
 #15000000
-1"
+1nHT-:
 #16000000
-0"
+0nHT-:
 #17000000
-1"
+1nHT-:
 #18000000
-0"
+0nHT-:
 #19000000
-1"
+1nHT-:
 #20000000
-1!
-0"
+1oHT(x
+0nHT-:
 #21000000
-1"
-b100000 #
+1nHT-:
+b100000 0:wF&
 #22000000
-0"
+0nHT-:
 #23000000
-1"
-b1010111 #
+1nHT-:
+b1010111 0:wF&
 #24000000
-0"
+0nHT-:
 #25000000
-1"
-b1101111 #
+1nHT-:
+b1101111 0:wF&
 #26000000
-0"
+0nHT-:
 #27000000
-1"
-b1110010 #
+1nHT-:
+b1110010 0:wF&
 #28000000
-0"
+0nHT-:
 #29000000
-1"
-b1101100 #
+1nHT-:
+b1101100 0:wF&
 #30000000
-0!
-0"
+0oHT(x
+0nHT-:
 #31000000
-1"
+1nHT-:
 #32000000
-0"
+0nHT-:
 #33000000
-1"
+1nHT-:
 #34000000
-0"
+0nHT-:
 #35000000
-1"
+1nHT-:
 #36000000
-0"
+0nHT-:
 #37000000
-1"
+1nHT-:
 #38000000
-0"
+0nHT-:
 #39000000
-1"
+1nHT-:
 #40000000
-1!
-0"
+1oHT(x
+0nHT-:
 #41000000
-1"
-b1100100 #
+1nHT-:
+b1100100 0:wF&
 #42000000
-0"
+0nHT-:
 #43000000
-1"
-b100001 #
+1nHT-:
+b100001 0:wF&
 #44000000
-0"
+0nHT-:
 #45000000
-1"
-b1010 #
+1nHT-:
+b1010 0:wF&
 #46000000
-0"
+0nHT-:
 #47000000
-1"
-b1001000 #
+1nHT-:
+b1001000 0:wF&
 #48000000
-0"
+0nHT-:
 #49000000
-1"
-b1100101 #
+1nHT-:
+b1100101 0:wF&
 #50000000
-0!
-0"
+0oHT(x
+0nHT-:
 #51000000
-1"
+1nHT-:
 #52000000
-0"
+0nHT-:
 #53000000
-1"
+1nHT-:
 #54000000
-0"
+0nHT-:
 #55000000
-1"
+1nHT-:
 #56000000
-0"
+0nHT-:
 #57000000
-1"
+1nHT-:
 #58000000
-0"
+0nHT-:
 #59000000
-1"
+1nHT-:
 #60000000

crates/fayalite/tests/sim/expected/last_connect.txt

@@ -0,0 +1,701 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 33,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(last_connect: last_connect).last_connect::inp",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Array<Bool, 4>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(last_connect: last_connect).last_connect::out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(UInt<8>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(UInt<8>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(last_connect: last_connect).last_connect::w",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<9>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(UInt<8>),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x3,
+                },
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x2,
+                },
+                2: Const {
+                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x1,
+                },
+                3: Const {
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x0,
+                },
+                4: Const {
+                    dest: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x4,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                6: Const {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                7: Const {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
+                    value: 0x0,
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
+                    src: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
+                },
+                11: SliceInt {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
+                    start: 1,
+                    len: 4,
+                },
+                12: SliceInt {
+                    dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 0,
+                    len: 1,
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                14: SliceInt {
+                    dest: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 1,
+                    len: 1,
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                16: SliceInt {
+                    dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 2,
+                    len: 1,
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                18: SliceInt {
+                    dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    start: 3,
+                    len: 1,
+                },
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                24: BranchIfZero {
+                    target: 26,
+                    value: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                26: BranchIfZero {
+                    target: 28,
+                    value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                28: BranchIfZero {
+                    target: 30,
+                    value: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                30: BranchIfZero {
+                    target: 32,
+                    value: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                31: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
+                },
+                34: Shl {
+                    dest: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
+                    lhs: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
+                    rhs: 1,
+                },
+                35: Or {
+                    dest: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    lhs: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
+                },
+                36: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    src: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    dest_width: 9,
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                38: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                39: BranchIfSmallNeImmediate {
+                    target: 41,
+                    lhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                40: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    src: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                41: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                42: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    src: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
+                },
+                43: SliceInt {
+                    dest: StatePartIndex<BigSlots>(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
+                    start: 1,
+                    len: 8,
+                },
+                44: Return,
+            ],
+            ..
+        },
+        pc: 44,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                1,
+                1,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                31,
+                1,
+                1,
+                1,
+                1,
+                31,
+                15,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                7,
+                7,
+                3,
+                0,
+                0,
+                3,
+                1,
+                3,
+                1,
+                6,
+                7,
+                7,
+                7,
+                4,
+                0,
+                1,
+                2,
+                3,
+            ],
+        },
+        sim_only_slots: StatePart {
+            value: [],
+        },
+    },
+    io: Instance {
+        name: <simulator>::last_connect,
+        instantiated: Module {
+            name: last_connect,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.inp,
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.out,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.inp,
+            Instance {
+                name: <simulator>::last_connect,
+                instantiated: Module {
+                    name: last_connect,
+                    ..
+                },
+            }.out,
+        },
+        did_initial_settle: true,
+        clocks_for_past: {},
+    },
+    extern_modules: [],
+    trace_decls: TraceModule {
+        name: "last_connect",
+        children: [
+            TraceModuleIO {
+                name: "inp",
+                child: TraceEnumWithFields {
+                    name: "inp",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(0),
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(Array<Bool, 4>),
+                        },
+                        flow: Source,
+                    },
+                    non_empty_fields: [
+                        TraceArray {
+                            name: "HdlSome",
+                            elements: [
+                                TraceBool {
+                                    location: TraceScalarId(1),
+                                    name: "[0]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(2),
+                                    name: "[1]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(3),
+                                    name: "[2]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(4),
+                                    name: "[3]",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Array<Bool, 4>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Array<Bool, 4>),
+                    },
+                    flow: Source,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Array<Bool, 4>),
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "out",
+                child: TraceEnumWithFields {
+                    name: "out",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(5),
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(UInt<8>),
+                        },
+                        flow: Sink,
+                    },
+                    non_empty_fields: [
+                        TraceUInt {
+                            location: TraceScalarId(6),
+                            name: "HdlSome",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(UInt<8>),
+                    },
+                    flow: Sink,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(UInt<8>),
+                },
+                flow: Sink,
+            },
+            TraceWire {
+                name: "w",
+                child: TraceUInt {
+                    location: TraceScalarId(7),
+                    name: "w",
+                    ty: UInt<8>,
+                    flow: Duplex,
+                },
+                ty: UInt<8>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(0),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Array<Bool, 4>),
+                },
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x1,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(1),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(UInt<8>),
+                },
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x02,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x02,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 17 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
+    ..
+}

crates/fayalite/tests/sim/expected/last_connect.vcd

@@ -0,0 +1,104 @@
+$timescale 1 ps $end
+$scope module last_connect $end
+$scope struct inp $end
+$var string 1 !C&}* \$tag $end
+$scope struct HdlSome $end
+$var wire 1 D_viZ \[0] $end
+$var wire 1 b5gFK \[1] $end
+$var wire 1 xUBRH \[2] $end
+$var wire 1 Gp7Xm \[3] $end
+$upscope $end
+$upscope $end
+$scope struct out $end
+$var string 1 ^Z_p3 \$tag $end
+$var wire 8 rz~), HdlSome $end
+$upscope $end
+$var wire 8 dlea> w $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+sHdlNone\x20(0) !C&}*
+0D_viZ
+0b5gFK
+0xUBRH
+0Gp7Xm
+sHdlNone\x20(0) ^Z_p3
+b0 rz~),
+b100 dlea>
+$end
+#1000000
+sHdlSome\x20(1) !C&}*
+sHdlSome\x20(1) ^Z_p3
+b100 rz~),
+#2000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#3000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#4000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#5000000
+1b5gFK
+0xUBRH
+0Gp7Xm
+b1 rz~),
+b1 dlea>
+#6000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#7000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#8000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#9000000
+1D_viZ
+0b5gFK
+0xUBRH
+0Gp7Xm
+b0 rz~),
+b0 dlea>
+#10000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#11000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#12000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#13000000
+1b5gFK
+0xUBRH
+0Gp7Xm
+b1 rz~),
+b1 dlea>
+#14000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#15000000
+1xUBRH
+0Gp7Xm
+b10 rz~),
+b10 dlea>
+#16000000
+1Gp7Xm
+b11 rz~),
+b11 dlea>
+#17000000

crates/fayalite/tests/sim/expected/memories.vcd

@@ -1,408 +1,408 @@
 $timescale 1 ps $end
 $scope module memories $end
 $scope struct r $end
-$var wire 4 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
+$var wire 4 z&0Qk addr $end
+$var wire 1 o.T)# en $end
+$var wire 1 :XNoK clk $end
 $scope struct data $end
-$var wire 8 $ \0 $end
-$var wire 8 % \1 $end
+$var wire 8 Cq]A% \0 $end
+$var wire 8 avKNj \1 $end
 $upscope $end
 $upscope $end
 $scope struct w $end
-$var wire 4 & addr $end
-$var wire 1 ' en $end
-$var wire 1 ( clk $end
+$var wire 4 p<O.M addr $end
+$var wire 1 #9)l8 en $end
+$var wire 1 QX!^| clk $end
 $scope struct data $end
-$var wire 8 ) \0 $end
-$var wire 8 * \1 $end
+$var wire 8 G"IXQ \0 $end
+$var wire 8 h\t:E \1 $end
 $upscope $end
 $scope struct mask $end
-$var wire 1 + \0 $end
-$var wire 1 , \1 $end
+$var wire 1 FCuNz \0 $end
+$var wire 1 /Y7%J \1 $end
 $upscope $end
 $upscope $end
 $scope struct mem $end
 $scope struct contents $end
 $scope struct \[0] $end
 $scope struct mem $end
-$var reg 8 9 \0 $end
-$var reg 8 I \1 $end
+$var reg 8 4d[cL \0 $end
+$var reg 8 {qEUV \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
 $scope struct mem $end
-$var reg 8 : \0 $end
-$var reg 8 J \1 $end
+$var reg 8 c`NPR \0 $end
+$var reg 8 vK:33 \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[2] $end
 $scope struct mem $end
-$var reg 8 ; \0 $end
-$var reg 8 K \1 $end
+$var reg 8 ihYp_ \0 $end
+$var reg 8 QZb%P \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[3] $end
 $scope struct mem $end
-$var reg 8 < \0 $end
-$var reg 8 L \1 $end
+$var reg 8 ,O%<$ \0 $end
+$var reg 8 @?uSf \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[4] $end
 $scope struct mem $end
-$var reg 8 = \0 $end
-$var reg 8 M \1 $end
+$var reg 8 N[IF& \0 $end
+$var reg 8 Zf9lw \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[5] $end
 $scope struct mem $end
-$var reg 8 > \0 $end
-$var reg 8 N \1 $end
+$var reg 8 dr6lq \0 $end
+$var reg 8 fc"UR \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[6] $end
 $scope struct mem $end
-$var reg 8 ? \0 $end
-$var reg 8 O \1 $end
+$var reg 8 xpw5\ \0 $end
+$var reg 8 dd$?K \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[7] $end
 $scope struct mem $end
-$var reg 8 @ \0 $end
-$var reg 8 P \1 $end
+$var reg 8 vH;}2 \0 $end
+$var reg 8 ILB?4 \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[8] $end
 $scope struct mem $end
-$var reg 8 A \0 $end
-$var reg 8 Q \1 $end
+$var reg 8 /X4v> \0 $end
+$var reg 8 &V*EE \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[9] $end
 $scope struct mem $end
-$var reg 8 B \0 $end
-$var reg 8 R \1 $end
+$var reg 8 IczZe \0 $end
+$var reg 8 unX>R \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[10] $end
 $scope struct mem $end
-$var reg 8 C \0 $end
-$var reg 8 S \1 $end
+$var reg 8 0hTyY \0 $end
+$var reg 8 9K_w) \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[11] $end
 $scope struct mem $end
-$var reg 8 D \0 $end
-$var reg 8 T \1 $end
+$var reg 8 +C/Sz \0 $end
+$var reg 8 }Y{:o \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[12] $end
 $scope struct mem $end
-$var reg 8 E \0 $end
-$var reg 8 U \1 $end
+$var reg 8 S6-5u \0 $end
+$var reg 8 9q6)w \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[13] $end
 $scope struct mem $end
-$var reg 8 F \0 $end
-$var reg 8 V \1 $end
+$var reg 8 !c<w* \0 $end
+$var reg 8 Ve@)M \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[14] $end
 $scope struct mem $end
-$var reg 8 G \0 $end
-$var reg 8 W \1 $end
+$var reg 8 OiF9* \0 $end
+$var reg 8 Ylyz~ \1 $end
 $upscope $end
 $upscope $end
 $scope struct \[15] $end
 $scope struct mem $end
-$var reg 8 H \0 $end
-$var reg 8 X \1 $end
+$var reg 8 ?+m9D \0 $end
+$var reg 8 A6sb~ \1 $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r0 $end
-$var wire 4 - addr $end
-$var wire 1 . en $end
-$var wire 1 / clk $end
+$var wire 4 ="2wN addr $end
+$var wire 1 jy78F en $end
+$var wire 1 \o>8T clk $end
 $scope struct data $end
-$var wire 8 0 \0 $end
-$var wire 8 1 \1 $end
+$var wire 8 \k#l \0 $end
+$var wire 8 olx7O \1 $end
 $upscope $end
 $upscope $end
 $scope struct w1 $end
-$var wire 4 2 addr $end
-$var wire 1 3 en $end
-$var wire 1 4 clk $end
+$var wire 4 H,W!J addr $end
+$var wire 1 "7?3I en $end
+$var wire 1 DC/;" clk $end
 $scope struct data $end
-$var wire 8 5 \0 $end
-$var wire 8 6 \1 $end
+$var wire 8 0DrV' \0 $end
+$var wire 8 wa!Cx \1 $end
 $upscope $end
 $scope struct mask $end
-$var wire 1 7 \0 $end
-$var wire 1 8 \1 $end
+$var wire 1 u^b&R \0 $end
+$var wire 1 Ic\|v \1 $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-b1 9
-b100011 I
-b1 :
-b100011 J
-b1 ;
-b100011 K
-b1 <
-b100011 L
-b1 =
-b100011 M
-b1 >
-b100011 N
-b1 ?
-b100011 O
-b1 @
-b100011 P
-b1 A
-b100011 Q
-b1 B
-b100011 R
-b1 C
-b100011 S
-b1 D
-b100011 T
-b1 E
-b100011 U
-b1 F
-b100011 V
-b1 G
-b100011 W
-b1 H
-b100011 X
-b0 !
-0"
-0#
-b0 $
-b0 %
-b0 &
-0'
-0(
-b0 )
-b0 *
-0+
-0,
-b0 -
-0.
-0/
-b0 0
-b0 1
-b0 2
-03
-04
-b0 5
-b0 6
-07
-08
+b1 4d[cL
+b100011 {qEUV
+b1 c`NPR
+b100011 vK:33
+b1 ihYp_
+b100011 QZb%P
+b1 ,O%<$
+b100011 @?uSf
+b1 N[IF&
+b100011 Zf9lw
+b1 dr6lq
+b100011 fc"UR
+b1 xpw5\
+b100011 dd$?K
+b1 vH;}2
+b100011 ILB?4
+b1 /X4v>
+b100011 &V*EE
+b1 IczZe
+b100011 unX>R
+b1 0hTyY
+b100011 9K_w)
+b1 +C/Sz
+b100011 }Y{:o
+b1 S6-5u
+b100011 9q6)w
+b1 !c<w*
+b100011 Ve@)M
+b1 OiF9*
+b100011 Ylyz~
+b1 ?+m9D
+b100011 A6sb~
+b0 z&0Qk
+0o.T)#
+0:XNoK
+b0 Cq]A%
+b0 avKNj
+b0 p<O.M
+0#9)l8
+0QX!^|
+b0 G"IXQ
+b0 h\t:E
+0FCuNz
+0/Y7%J
+b0 ="2wN
+0jy78F
+0\o>8T
+b0 \k#l
+b0 olx7O
+b0 H,W!J
+0"7?3I
+0DC/;"
+b0 0DrV'
+b0 wa!Cx
+0u^b&R
+0Ic\|v
 $end
 #1000000
-1#
-1(
-1/
-14
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #2000000
-1"
-0#
-b1 $
-b100011 %
-1'
-0(
-b10000 )
-b100000 *
-1+
-1,
-1.
-0/
-b1 0
-b100011 1
-13
-04
-b10000 5
-b100000 6
-17
-18
+1o.T)#
+0:XNoK
+b1 Cq]A%
+b100011 avKNj
+1#9)l8
+0QX!^|
+b10000 G"IXQ
+b100000 h\t:E
+1FCuNz
+1/Y7%J
+1jy78F
+0\o>8T
+b1 \k#l
+b100011 olx7O
+1"7?3I
+0DC/;"
+b10000 0DrV'
+b100000 wa!Cx
+1u^b&R
+1Ic\|v
 #3000000
-b10000 9
-b100000 I
-1#
-b10000 $
-b100000 %
-1(
-1/
-b10000 0
-b100000 1
-14
+b10000 4d[cL
+b100000 {qEUV
+1:XNoK
+b10000 Cq]A%
+b100000 avKNj
+1QX!^|
+1\o>8T
+b10000 \k#l
+b100000 olx7O
+1DC/;"
 #4000000
-0#
-0(
-b110000 )
-b1000000 *
-0+
-0/
-04
-b110000 5
-b1000000 6
-07
+0:XNoK
+0QX!^|
+b110000 G"IXQ
+b1000000 h\t:E
+0FCuNz
+0\o>8T
+0DC/;"
+b110000 0DrV'
+b1000000 wa!Cx
+0u^b&R
 #5000000
-b10000 9
-b1000000 I
-1#
-b1000000 %
-1(
-1/
-b1000000 1
-14
+b10000 4d[cL
+b1000000 {qEUV
+1:XNoK
+b1000000 avKNj
+1QX!^|
+1\o>8T
+b1000000 olx7O
+1DC/;"
 #6000000
-0#
-0(
-b1010000 )
-b1100000 *
-1+
-0,
-0/
-04
-b1010000 5
-b1100000 6
-17
-08
+0:XNoK
+0QX!^|
+b1010000 G"IXQ
+b1100000 h\t:E
+1FCuNz
+0/Y7%J
+0\o>8T
+0DC/;"
+b1010000 0DrV'
+b1100000 wa!Cx
+1u^b&R
+0Ic\|v
 #7000000
-b1010000 9
-b1000000 I
-1#
-b1010000 $
-1(
-1/
-b1010000 0
-14
+b1010000 4d[cL
+b1000000 {qEUV
+1:XNoK
+b1010000 Cq]A%
+1QX!^|
+1\o>8T
+b1010000 \k#l
+1DC/;"
 #8000000
-0#
-0(
-b1110000 )
-b10000000 *
-0+
-0/
-04
-b1110000 5
-b10000000 6
-07
+0:XNoK
+0QX!^|
+b1110000 G"IXQ
+b10000000 h\t:E
+0FCuNz
+0\o>8T
+0DC/;"
+b1110000 0DrV'
+b10000000 wa!Cx
+0u^b&R
 #9000000
-1#
-1(
-1/
-14
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #10000000
-0#
-0'
-0(
-b10010000 )
-b10100000 *
-0/
-03
-04
-b10010000 5
-b10100000 6
+0:XNoK
+0#9)l8
+0QX!^|
+b10010000 G"IXQ
+b10100000 h\t:E
+0\o>8T
+0"7?3I
+0DC/;"
+b10010000 0DrV'
+b10100000 wa!Cx
 #11000000
-1#
-1(
-1/
-14
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #12000000
-0#
-b1 &
-1'
-0(
-1+
-1,
-0/
-b1 2
-13
-04
-17
-18
+0:XNoK
+b1 p<O.M
+1#9)l8
+0QX!^|
+1FCuNz
+1/Y7%J
+0\o>8T
+b1 H,W!J
+1"7?3I
+0DC/;"
+1u^b&R
+1Ic\|v
 #13000000
-b10010000 :
-b10100000 J
-1#
-1(
-1/
-14
+b10010000 c`NPR
+b10100000 vK:33
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #14000000
-0#
-b10 &
-0(
-b10110000 )
-b11000000 *
-0/
-b10 2
-04
-b10110000 5
-b11000000 6
+0:XNoK
+b10 p<O.M
+0QX!^|
+b10110000 G"IXQ
+b11000000 h\t:E
+0\o>8T
+b10 H,W!J
+0DC/;"
+b10110000 0DrV'
+b11000000 wa!Cx
 #15000000
-b10110000 ;
-b11000000 K
-1#
-1(
-1/
-14
+b10110000 ihYp_
+b11000000 QZb%P
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #16000000
-0#
-0'
-0(
-b11010000 )
-b11100000 *
-0/
-03
-04
-b11010000 5
-b11100000 6
+0:XNoK
+0#9)l8
+0QX!^|
+b11010000 G"IXQ
+b11100000 h\t:E
+0\o>8T
+0"7?3I
+0DC/;"
+b11010000 0DrV'
+b11100000 wa!Cx
 #17000000
-1#
-1(
-1/
-14
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #18000000
-b1 !
-0#
-b10010000 $
-b10100000 %
-0(
-b1 -
-0/
-b10010000 0
-b10100000 1
-04
+b1 z&0Qk
+0:XNoK
+b10010000 Cq]A%
+b10100000 avKNj
+0QX!^|
+b1 ="2wN
+0\o>8T
+b10010000 \k#l
+b10100000 olx7O
+0DC/;"
 #19000000
-1#
-1(
-1/
-14
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #20000000
-b10 !
-0#
-b10110000 $
-b11000000 %
-0(
-b10 -
-0/
-b10110000 0
-b11000000 1
-04
+b10 z&0Qk
+0:XNoK
+b10110000 Cq]A%
+b11000000 avKNj
+0QX!^|
+b10 ="2wN
+0\o>8T
+b10110000 \k#l
+b11000000 olx7O
+0DC/;"
 #21000000
-1#
-1(
-1/
-14
+1:XNoK
+1QX!^|
+1\o>8T
+1DC/;"
 #22000000
-0#
-0(
-0/
-04
+0:XNoK
+0QX!^|
+0\o>8T
+0DC/;"

crates/fayalite/tests/sim/expected/memories2.vcd

@@ -1,363 +1,363 @@
 $timescale 1 ps $end
 $scope module memories2 $end
 $scope struct rw $end
-$var wire 3 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$var wire 2 $ rdata $end
-$var wire 1 % wmode $end
-$var wire 2 & wdata $end
-$var wire 1 ' wmask $end
+$var wire 3 xkkG> addr $end
+$var wire 1 HoA{1 en $end
+$var wire 1 C*2BQ clk $end
+$var wire 2 ueF!x rdata $end
+$var wire 1 m\l/p wmode $end
+$var wire 2 WmjEh wdata $end
+$var wire 1 +3E@H wmask $end
 $upscope $end
 $scope struct mem $end
 $scope struct contents $end
 $scope struct \[0] $end
 $scope struct mem $end
-$var string 1 1 \$tag $end
-$var reg 1 6 HdlSome $end
+$var string 1 ujd9u \$tag $end
+$var reg 1 *5lV# HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
 $scope struct mem $end
-$var string 1 2 \$tag $end
-$var reg 1 7 HdlSome $end
+$var string 1 *qL|n \$tag $end
+$var reg 1 ^/FDC HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[2] $end
 $scope struct mem $end
-$var string 1 3 \$tag $end
-$var reg 1 8 HdlSome $end
+$var string 1 r*7|@ \$tag $end
+$var reg 1 YMY"3 HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[3] $end
 $scope struct mem $end
-$var string 1 4 \$tag $end
-$var reg 1 9 HdlSome $end
+$var string 1 jj/6F \$tag $end
+$var reg 1 S+Uy} HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[4] $end
 $scope struct mem $end
-$var string 1 5 \$tag $end
-$var reg 1 : HdlSome $end
+$var string 1 H72IP \$tag $end
+$var reg 1 vH{({ HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct rw0 $end
-$var wire 3 ( addr $end
-$var wire 1 ) en $end
-$var wire 1 * clk $end
+$var wire 3 uabMI addr $end
+$var wire 1 LEn[l en $end
+$var wire 1 OpH)U clk $end
 $scope struct rdata $end
-$var string 1 + \$tag $end
-$var wire 1 , HdlSome $end
+$var string 1 [}rcZ \$tag $end
+$var wire 1 5f=Y~ HdlSome $end
 $upscope $end
-$var wire 1 - wmode $end
+$var wire 1 6c_9_ wmode $end
 $scope struct wdata $end
-$var string 1 . \$tag $end
-$var wire 1 / HdlSome $end
+$var string 1 $hfRN \$tag $end
+$var wire 1 rop,b HdlSome $end
 $upscope $end
-$var wire 1 0 wmask $end
+$var wire 1 Ly=US wmask $end
 $upscope $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-sHdlSome\x20(1) 1
-16
-sHdlSome\x20(1) 2
-17
-sHdlSome\x20(1) 3
-18
-sHdlSome\x20(1) 4
-19
-sHdlSome\x20(1) 5
-1:
-b0 !
-0"
-0#
-b0 $
-0%
-b0 &
-0'
-b0 (
-0)
-0*
-sHdlNone\x20(0) +
-0,
-0-
-sHdlNone\x20(0) .
-0/
-00
+sHdlSome\x20(1) ujd9u
+1*5lV#
+sHdlSome\x20(1) *qL|n
+1^/FDC
+sHdlSome\x20(1) r*7|@
+1YMY"3
+sHdlSome\x20(1) jj/6F
+1S+Uy}
+sHdlSome\x20(1) H72IP
+1vH{({
+b0 xkkG>
+0HoA{1
+0C*2BQ
+b0 ueF!x
+0m\l/p
+b0 WmjEh
+0+3E@H
+b0 uabMI
+0LEn[l
+0OpH)U
+sHdlNone\x20(0) [}rcZ
+05f=Y~
+06c_9_
+sHdlNone\x20(0) $hfRN
+0rop,b
+0Ly=US
 $end
 #250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #500000
 #750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #1000000
-1"
-1)
+1HoA{1
+1LEn[l
 #1250000
-1#
-b11 $
-1*
-sHdlSome\x20(1) +
-1,
+1C*2BQ
+b11 ueF!x
+1OpH)U
+sHdlSome\x20(1) [}rcZ
+15f=Y~
 #1500000
 #1750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #2000000
-0"
-0)
+0HoA{1
+0LEn[l
 #2250000
-1#
-b0 $
-1*
-sHdlNone\x20(0) +
-0,
+1C*2BQ
+b0 ueF!x
+1OpH)U
+sHdlNone\x20(0) [}rcZ
+05f=Y~
 #2500000
 #2750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #3000000
-1"
-1%
-1'
-1)
-1-
-10
+1HoA{1
+1m\l/p
+1+3E@H
+1LEn[l
+16c_9_
+1Ly=US
 #3250000
-sHdlNone\x20(0) 1
-06
-1#
-1*
+sHdlNone\x20(0) ujd9u
+0*5lV#
+1C*2BQ
+1OpH)U
 #3500000
 #3750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #4000000
-0%
-0'
-0-
-00
+0m\l/p
+0+3E@H
+06c_9_
+0Ly=US
 #4250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #4500000
 #4750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #5000000
-1%
-b11 &
-1-
-sHdlSome\x20(1) .
-1/
+1m\l/p
+b11 WmjEh
+16c_9_
+sHdlSome\x20(1) $hfRN
+1rop,b
 #5250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #5500000
 #5750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #6000000
-b1 !
-b1 &
-1'
-b1 (
-0/
-10
+b1 xkkG>
+b1 WmjEh
+1+3E@H
+b1 uabMI
+0rop,b
+1Ly=US
 #6250000
-sHdlSome\x20(1) 2
-07
-1#
-1*
+sHdlSome\x20(1) *qL|n
+0^/FDC
+1C*2BQ
+1OpH)U
 #6500000
 #6750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #7000000
-b10 !
-b10 &
-b10 (
-sHdlNone\x20(0) .
+b10 xkkG>
+b10 WmjEh
+b10 uabMI
+sHdlNone\x20(0) $hfRN
 #7250000
-sHdlNone\x20(0) 3
-08
-1#
-1*
+sHdlNone\x20(0) r*7|@
+0YMY"3
+1C*2BQ
+1OpH)U
 #7500000
 #7750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #8000000
-b11 !
-b11 &
-b11 (
-sHdlSome\x20(1) .
-1/
+b11 xkkG>
+b11 WmjEh
+b11 uabMI
+sHdlSome\x20(1) $hfRN
+1rop,b
 #8250000
-sHdlSome\x20(1) 4
-19
-1#
-1*
+sHdlSome\x20(1) jj/6F
+1S+Uy}
+1C*2BQ
+1OpH)U
 #8500000
 #8750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #9000000
-b100 !
-b10 &
-b100 (
-sHdlNone\x20(0) .
-0/
+b100 xkkG>
+b10 WmjEh
+b100 uabMI
+sHdlNone\x20(0) $hfRN
+0rop,b
 #9250000
-sHdlNone\x20(0) 5
-0:
-1#
-1*
+sHdlNone\x20(0) H72IP
+0vH{({
+1C*2BQ
+1OpH)U
 #9500000
 #9750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #10000000
-b101 !
-b1 &
-b101 (
-sHdlSome\x20(1) .
+b101 xkkG>
+b1 WmjEh
+b101 uabMI
+sHdlSome\x20(1) $hfRN
 #10250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #10500000
 #10750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #11000000
-b110 !
-b110 (
+b110 xkkG>
+b110 uabMI
 #11250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #11500000
 #11750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #12000000
-b111 !
-b111 (
+b111 xkkG>
+b111 uabMI
 #12250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #12500000
 #12750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #13000000
-0%
-b0 &
-0'
-0-
-sHdlNone\x20(0) .
-00
+0m\l/p
+b0 WmjEh
+0+3E@H
+06c_9_
+sHdlNone\x20(0) $hfRN
+0Ly=US
 #13250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #13500000
 #13750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #14000000
-b110 !
-b110 (
+b110 xkkG>
+b110 uabMI
 #14250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #14500000
 #14750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #15000000
-b101 !
-b101 (
+b101 xkkG>
+b101 uabMI
 #15250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #15500000
 #15750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #16000000
-b100 !
-b100 (
+b100 xkkG>
+b100 uabMI
 #16250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #16500000
 #16750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #17000000
-b11 !
-b11 (
+b11 xkkG>
+b11 uabMI
 #17250000
-1#
-b11 $
-1*
-sHdlSome\x20(1) +
-1,
+1C*2BQ
+b11 ueF!x
+1OpH)U
+sHdlSome\x20(1) [}rcZ
+15f=Y~
 #17500000
 #17750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #18000000
-b10 !
-b10 (
+b10 xkkG>
+b10 uabMI
 #18250000
-1#
-b0 $
-1*
-sHdlNone\x20(0) +
-0,
+1C*2BQ
+b0 ueF!x
+1OpH)U
+sHdlNone\x20(0) [}rcZ
+05f=Y~
 #18500000
 #18750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #19000000
-b0 !
-b0 (
+b0 xkkG>
+b0 uabMI
 #19250000
-1#
-1*
+1C*2BQ
+1OpH)U
 #19500000
 #19750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #20000000
-b1 !
-b1 (
+b1 xkkG>
+b1 uabMI
 #20250000
-1#
-b1 $
-1*
-sHdlSome\x20(1) +
+1C*2BQ
+b1 ueF!x
+1OpH)U
+sHdlSome\x20(1) [}rcZ
 #20500000
 #20750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #21000000
-b0 !
-0"
-b0 (
-0)
+b0 xkkG>
+0HoA{1
+b0 uabMI
+0LEn[l
 #21250000
-1#
-b0 $
-1*
-sHdlNone\x20(0) +
+1C*2BQ
+b0 ueF!x
+1OpH)U
+sHdlNone\x20(0) [}rcZ
 #21500000
 #21750000
-0#
-0*
+0C*2BQ
+0OpH)U
 #22000000

crates/fayalite/tests/sim/expected/mod1.vcd

@@ -1,47 +1,34 @@
 $timescale 1 ps $end
 $scope module mod1 $end
 $scope struct o $end
-$var wire 4 ! i $end
-$var wire 2 " o $end
-$var wire 2 # i2 $end
-$var wire 4 $ o2 $end
+$var wire 4 avK(^ i $end
+$var wire 2 Q2~aG o $end
+$var wire 2 DXK'| i2 $end
+$var wire 4 cPuix o2 $end
 $upscope $end
-$scope struct child $end
-$var wire 4 ) i $end
-$var wire 2 * o $end
-$var wire 2 + i2 $end
-$var wire 4 , o2 $end
-$upscope $end
-$scope module mod1_child $end
-$var wire 4 % i $end
-$var wire 2 & o $end
-$var wire 2 ' i2 $end
-$var wire 4 ( o2 $end
+$scope module child $end
+$var wire 4 ($5K7 i $end
+$var wire 2 %6Wv" o $end
+$var wire 2 +|-AU i2 $end
+$var wire 4 Hw?%j o2 $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-b11 !
-b11 "
-b10 #
-b1110 $
-b11 %
-b11 &
-b10 '
-b1110 (
-b11 )
-b11 *
-b10 +
-b1110 ,
+b11 avK(^
+b11 Q2~aG
+b10 DXK'|
+b1110 cPuix
+b11 ($5K7
+b11 %6Wv"
+b10 +|-AU
+b1110 Hw?%j
 $end
 #1000000
-b1010 !
-b10 "
-b1111 $
-b1010 %
-b10 &
-b1111 (
-b1010 )
-b10 *
-b1111 ,
+b1010 avK(^
+b10 Q2~aG
+b1111 cPuix
+b1010 ($5K7
+b10 %6Wv"
+b1111 Hw?%j
 #2000000

crates/fayalite/tests/sim/expected/phantom_const.vcd

@@ -1,31 +1,31 @@
 $timescale 1 ps $end
 $scope module phantom_const $end
 $scope struct out $end
-$var string 1 ! \[0] $end
-$var string 1 " \[1] $end
+$var string 1 Ru)8A \[0] $end
+$var string 1 y&ssi \[1] $end
 $upscope $end
 $scope struct mem $end
 $scope struct contents $end
 $scope struct \[0] $end
-$var string 1 ' mem $end
+$var string 1 =+olp mem $end
 $upscope $end
 $upscope $end
 $scope struct r0 $end
-$var string 0 # addr $end
-$var wire 1 $ en $end
-$var wire 1 % clk $end
-$var string 1 & data $end
+$var string 0 U5SS1 addr $end
+$var wire 1 rx@_T en $end
+$var wire 1 o[(us clk $end
+$var string 1 %Bg(6 data $end
 $upscope $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-s0 '
-sPhantomConst([\"a\",\"b\"]) !
-sPhantomConst([\"a\",\"b\"]) "
-s0 #
-0$
-0%
-sPhantomConst(\"mem_element\") &
+s0 =+olp
+sPhantomConst([\"a\",\"b\"]) Ru)8A
+sPhantomConst([\"a\",\"b\"]) y&ssi
+s0 U5SS1
+0rx@_T
+0o[(us
+sPhantomConst(\"mem_element\") %Bg(6
 $end
 #1000000

crates/fayalite/tests/sim/expected/ripple_counter.txt

@@ -314,55 +314,56 @@ Simulation {
                     src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
                     width: 1,
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:7:1
-                4: Copy {
+                3: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
                     src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                5: Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                6: Copy {
+                5: Copy {
                     dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                7: Copy {
+                6: Copy {
                     dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
                 },
+                // at: module-XXXXXXXXXX.rs:6:1
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
                 8: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                9: Copy {
                     dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
                     src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                9: Copy {
+                10: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
                     src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                10: Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
                 },
-                11: NotU {
+                12: NotU {
                     dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
                     width: 1,
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:7:1
                 13: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
@@ -383,241 +384,257 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
                 },
+                // at: module-XXXXXXXXXX.rs:6:1
                 17: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                19: Copy {
                     dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
                     src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                18: Copy {
+                20: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
                     src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                19: Copy {
+                21: Copy {
                     dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
                 },
-                20: NotU {
+                22: NotU {
                     dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
                     width: 1,
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:7:1
-                22: Copy {
+                23: Copy {
                     dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
                     src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                23: Copy {
+                24: Copy {
                     dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
                     src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                24: Copy {
+                25: Copy {
                     dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                25: Copy {
+                26: Copy {
                     dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
                 },
+                // at: module-XXXXXXXXXX.rs:6:1
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                26: Const {
+                29: Const {
                     dest: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     value: 0x0,
                 },
-                27: Copy {
+                30: Copy {
                     dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                28: Copy {
+                31: Copy {
                     dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock },
                 },
-                29: Copy {
+                32: Copy {
                     dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                30: IsNonZeroDestIsSmall {
+                33: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
                 },
-                31: AndSmall {
+                34: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                32: Copy {
+                35: Copy {
                     dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
-                33: Copy {
+                36: Copy {
                     dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                34: IsNonZeroDestIsSmall {
+                37: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                 },
-                35: AndSmall {
+                38: AndSmall {
                     dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                36: Copy {
+                39: Copy {
                     dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
                 },
-                37: Copy {
+                40: Copy {
                     dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                38: IsNonZeroDestIsSmall {
+                41: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
                 },
-                39: AndSmall {
+                42: AndSmall {
                     dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                40: Copy {
+                43: Copy {
                     dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
                 },
-                41: Shl {
+                44: Shl {
                     dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     lhs: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 5,
                 },
-                42: Copy {
+                45: Copy {
                     dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
                 },
-                43: Shl {
+                46: Shl {
                     dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 4,
                 },
-                44: Copy {
+                47: Copy {
                     dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
                 },
-                45: Shl {
+                48: Shl {
                     dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 3,
                 },
-                46: Copy {
+                49: Copy {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
                 },
-                47: Shl {
+                50: Shl {
                     dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 2,
                 },
-                48: Copy {
+                51: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
                 },
-                49: Shl {
+                52: Shl {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                50: Copy {
+                53: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
                 },
-                51: Or {
+                54: Or {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
-                52: Or {
+                55: Or {
                     dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     lhs: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                 },
-                53: Or {
+                56: Or {
                     dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     rhs: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                54: Or {
+                57: Or {
                     dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                 },
-                55: Or {
+                58: Or {
                     dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     lhs: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
                     rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                56: Copy {
+                59: Copy {
                     dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> },
                     src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                57: BranchIfSmallZero {
-                    target: 59,
+                60: BranchIfSmallZero {
+                    target: 62,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                58: Copy {
+                61: Copy {
                     dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
                     src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
                 },
-                59: BranchIfSmallZero {
-                    target: 61,
+                62: BranchIfSmallZero {
+                    target: 64,
                     value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                60: Copy {
+                63: Copy {
                     dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
                     src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
                 },
-                61: BranchIfSmallZero {
-                    target: 63,
+                64: BranchIfSmallZero {
+                    target: 66,
                     value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                62: Copy {
+                65: Copy {
                     dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
                     src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
                 },
-                63: XorSmallImmediate {
+                66: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
-                64: XorSmallImmediate {
+                67: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
-                65: XorSmallImmediate {
+                68: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                66: Return,
+                69: Return,
             ],
             ..
         },
-        pc: 66,
+        pc: 69,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/shift_register.txt

@@ -103,137 +103,156 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:12:1
+                // at: module-XXXXXXXXXX.rs:11:1
                 1: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                2: Copy {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                 },
+                // at: module-XXXXXXXXXX.rs:9:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:10:1
-                2: Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                 },
+                // at: module-XXXXXXXXXX.rs:7:1
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:8:1
-                3: Copy {
+                6: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:6:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
-                },
                 // at: module-XXXXXXXXXX.rs:5:1
-                5: IsNonZeroDestIsSmall {
+                7: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
                 },
-                6: IsNonZeroDestIsSmall {
+                8: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
                 },
-                7: AndSmall {
+                9: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
-                8: Const {
+                12: Const {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                     value: 0x0,
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                9: BranchIfSmallZero {
-                    target: 14,
+                13: BranchIfSmallZero {
+                    target: 18,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                10: BranchIfSmallNonZero {
-                    target: 13,
+                14: BranchIfSmallNonZero {
+                    target: 17,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                11: Copy {
+                15: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                     src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
                 },
-                12: Branch {
-                    target: 14,
+                16: Branch {
+                    target: 18,
                 },
-                13: Copy {
+                17: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
-                14: BranchIfSmallZero {
-                    target: 19,
+                18: BranchIfSmallZero {
+                    target: 23,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                15: BranchIfSmallNonZero {
-                    target: 18,
+                19: BranchIfSmallNonZero {
+                    target: 22,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                16: Copy {
+                20: Copy {
                     dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                     src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                 },
-                17: Branch {
-                    target: 19,
+                21: Branch {
+                    target: 23,
                 },
-                18: Copy {
+                22: Copy {
                     dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                19: BranchIfSmallZero {
-                    target: 24,
+                23: BranchIfSmallZero {
+                    target: 28,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                20: BranchIfSmallNonZero {
-                    target: 23,
+                24: BranchIfSmallNonZero {
+                    target: 27,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                21: Copy {
+                25: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                     src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                 },
-                22: Branch {
-                    target: 24,
+                26: Branch {
+                    target: 28,
                 },
-                23: Copy {
+                27: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                24: BranchIfSmallZero {
-                    target: 29,
+                28: BranchIfSmallZero {
+                    target: 33,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                25: BranchIfSmallNonZero {
-                    target: 28,
+                29: BranchIfSmallNonZero {
+                    target: 32,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                26: Copy {
+                30: Copy {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                     src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                 },
-                27: Branch {
-                    target: 29,
+                31: Branch {
+                    target: 33,
                 },
-                28: Copy {
+                32: Copy {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                29: XorSmallImmediate {
+                33: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                30: Return,
+                34: Return,
             ],
             ..
         },
-        pc: 30,
+        pc: 34,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/shift_register.vcd

@@ -1,193 +1,193 @@
 $timescale 1 ps $end
 $scope module shift_register $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 <Ol<I clk $end
+$var wire 1 ,E;9k rst $end
 $upscope $end
-$var wire 1 # d $end
-$var wire 1 $ q $end
-$var reg 1 % reg0 $end
-$var reg 1 & reg1 $end
-$var reg 1 ' reg2 $end
-$var reg 1 ( reg3 $end
+$var wire 1 %2/Zc d $end
+$var wire 1 '1p#x q $end
+$var reg 1 vd~J{ reg0 $end
+$var reg 1 ~7wBy reg1 $end
+$var reg 1 s@[|n reg2 $end
+$var reg 1 %.BqD reg3 $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
-0#
-0$
-0%
-0&
-0'
-0(
+0<Ol<I
+1,E;9k
+0%2/Zc
+0'1p#x
+0vd~J{
+0~7wBy
+0s@[|n
+0%.BqD
 $end
 #1000000
-1!
+1<Ol<I
 #1100000
-0"
+0,E;9k
 #2000000
-0!
+0<Ol<I
 #3000000
-1!
+1<Ol<I
 #4000000
-0!
-1#
+0<Ol<I
+1%2/Zc
 #5000000
-1!
-1%
+1<Ol<I
+1vd~J{
 #6000000
-0!
+0<Ol<I
 #7000000
-1!
-1&
+1<Ol<I
+1~7wBy
 #8000000
-0!
-0#
+0<Ol<I
+0%2/Zc
 #9000000
-1!
-0%
-1'
+1<Ol<I
+0vd~J{
+1s@[|n
 #10000000
-0!
+0<Ol<I
 #11000000
-1!
-1$
-0&
-1(
+1<Ol<I
+1'1p#x
+0~7wBy
+1%.BqD
 #12000000
-0!
-1#
+0<Ol<I
+1%2/Zc
 #13000000
-1!
-1%
-0'
+1<Ol<I
+1vd~J{
+0s@[|n
 #14000000
-0!
-0#
+0<Ol<I
+0%2/Zc
 #15000000
-1!
-0$
-0%
-1&
-0(
+1<Ol<I
+0'1p#x
+0vd~J{
+1~7wBy
+0%.BqD
 #16000000
-0!
-1#
+0<Ol<I
+1%2/Zc
 #17000000
-1!
-1%
-0&
-1'
+1<Ol<I
+1vd~J{
+0~7wBy
+1s@[|n
 #18000000
-0!
+0<Ol<I
 #19000000
-1!
-1$
-1&
-0'
-1(
+1<Ol<I
+1'1p#x
+1~7wBy
+0s@[|n
+1%.BqD
 #20000000
-0!
+0<Ol<I
 #21000000
-1!
-0$
-1'
-0(
+1<Ol<I
+0'1p#x
+1s@[|n
+0%.BqD
 #22000000
-0!
+0<Ol<I
 #23000000
-1!
-1$
-1(
+1<Ol<I
+1'1p#x
+1%.BqD
 #24000000
-0!
-0#
+0<Ol<I
+0%2/Zc
 #25000000
-1!
-0%
+1<Ol<I
+0vd~J{
 #26000000
-0!
+0<Ol<I
 #27000000
-1!
-0&
+1<Ol<I
+0~7wBy
 #28000000
-0!
+0<Ol<I
 #29000000
-1!
-0'
+1<Ol<I
+0s@[|n
 #30000000
-0!
+0<Ol<I
 #31000000
-1!
-0$
-0(
+1<Ol<I
+0'1p#x
+0%.BqD
 #32000000
-0!
+0<Ol<I
 #33000000
-1!
+1<Ol<I
 #34000000
-0!
+0<Ol<I
 #35000000
-1!
+1<Ol<I
 #36000000
-0!
+0<Ol<I
 #37000000
-1!
+1<Ol<I
 #38000000
-0!
+0<Ol<I
 #39000000
-1!
+1<Ol<I
 #40000000
-0!
+0<Ol<I
 #41000000
-1!
+1<Ol<I
 #42000000
-0!
+0<Ol<I
 #43000000
-1!
+1<Ol<I
 #44000000
-0!
+0<Ol<I
 #45000000
-1!
+1<Ol<I
 #46000000
-0!
+0<Ol<I
 #47000000
-1!
+1<Ol<I
 #48000000
-0!
+0<Ol<I
 #49000000
-1!
+1<Ol<I
 #50000000
-0!
+0<Ol<I
 #51000000
-1!
+1<Ol<I
 #52000000
-0!
+0<Ol<I
 #53000000
-1!
+1<Ol<I
 #54000000
-0!
+0<Ol<I
 #55000000
-1!
+1<Ol<I
 #56000000
-0!
+0<Ol<I
 #57000000
-1!
+1<Ol<I
 #58000000
-0!
+0<Ol<I
 #59000000
-1!
+1<Ol<I
 #60000000
-0!
+0<Ol<I
 #61000000
-1!
+1<Ol<I
 #62000000
-0!
+0<Ol<I
 #63000000
-1!
+1<Ol<I
 #64000000
-0!
+0<Ol<I
 #65000000
-1!
+1<Ol<I
 #66000000

crates/fayalite/tests/sim/expected/sim_only_connects.txt

@@ -212,55 +212,55 @@ Simulation {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
                     value: 0x0,
                 },
-                // at: module-XXXXXXXXXX.rs:17:1
-                7: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:16:1
-                8: CloneSimOnly {
-                    dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
-                    src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
-                },
                 // at: module-XXXXXXXXXX.rs:12:1
-                9: CloneSimOnly {
+                7: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                10: BranchIfZero {
-                    target: 12,
+                8: BranchIfZero {
+                    target: 10,
                     value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                11: CloneSimOnly {
+                9: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                12: CloneSimOnly {
+                10: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                13: BranchIfZero {
-                    target: 15,
+                11: BranchIfZero {
+                    target: 13,
                     value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                14: CloneSimOnly {
+                12: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                15: Copy {
+                13: Copy {
                     dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock },
                 },
-                16: Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset },
                 },
+                // at: module-XXXXXXXXXX.rs:9:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:17:1
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
                 // at: module-XXXXXXXXXX.rs:1:1
                 17: Const {
                     dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
@@ -280,91 +280,100 @@ Simulation {
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:7:1
                 21: CloneSimOnly {
+                    dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                    src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                },
+                // at: module-XXXXXXXXXX.rs:16:1
+                22: CloneSimOnly {
+                    dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                    src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                23: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:18:1
-                22: CloneSimOnly {
+                24: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:21:1
-                23: CloneSimOnly {
+                25: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:19:1
-                24: CloneSimOnly {
+                26: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
-                25: CloneSimOnly {
+                27: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
-                26: Copy {
+                28: Copy {
                     dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock },
                     src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
                 },
-                27: Copy {
+                29: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset },
                     src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                28: BranchIfSmallZero {
-                    target: 33,
+                30: BranchIfSmallZero {
+                    target: 35,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                29: BranchIfSmallNonZero {
-                    target: 32,
+                31: BranchIfSmallNonZero {
+                    target: 34,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                30: CloneSimOnly {
+                32: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
-                31: Branch {
-                    target: 33,
+                33: Branch {
+                    target: 35,
                 },
-                32: CloneSimOnly {
+                34: CloneSimOnly {
                     dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                     src: StatePartIndex<SimOnlySlots>(10), // ({}) SlotDebugData { name: "", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                33: BranchIfSmallZero {
-                    target: 38,
+                35: BranchIfSmallZero {
+                    target: 40,
                     value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                34: BranchIfSmallNonZero {
-                    target: 37,
+                36: BranchIfSmallNonZero {
+                    target: 39,
                     value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                35: Copy {
+                37: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
                 },
-                36: Branch {
-                    target: 38,
+                38: Branch {
+                    target: 40,
                 },
-                37: Copy {
+                39: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
                     src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                38: XorSmallImmediate {
+                40: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                39: Return,
+                41: Return,
             ],
             ..
         },
-        pc: 39,
+        pc: 41,
         memory_write_log: [],
         memories: StatePart {
             value: [],

crates/fayalite/tests/sim/expected/sim_only_connects.vcd

@@ -1,182 +1,122 @@
 $timescale 1 ps $end
 $scope module sim_only_connects $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 tq:(w clk $end
+$var wire 1 FVlgb rst $end
 $upscope $end
-$var string 1 # inp $end
-$var string 1 $ out1 $end
-$var string 1 % out2 $end
-$var string 1 & out3 $end
-$scope struct helper1 $end
+$var string 1 g:xf? inp $end
+$var string 1 [OKKg out1 $end
+$var string 1 9pB-> out2 $end
+$var string 1 8(7-4 out3 $end
+$scope module helper1 $end
 $scope struct cd $end
-$var wire 1 + clk $end
-$var wire 1 , rst $end
+$var wire 1 $Kwp\ clk $end
+$var wire 1 nmVq' rst $end
 $upscope $end
-$var string 1 - inp $end
-$var string 1 . out $end
+$var string 1 qS)@z inp $end
+$var string 1 ~je// out $end
 $upscope $end
-$scope module sim_only_connects_helper $end
+$var string 1 CyjVm delay1 $end
+$var reg 1 z~g{\ delay1_empty $end
+$scope module helper2 $end
 $scope struct cd $end
-$var wire 1 ' clk $end
-$var wire 1 ( rst $end
+$var wire 1 Ph.=# clk $end
+$var wire 1 !GXK\ rst $end
 $upscope $end
-$var string 1 ) inp $end
-$var string 1 * out $end
-$upscope $end
-$var string 1 / delay1 $end
-$var reg 1 0 delay1_empty $end
-$scope struct helper2 $end
-$scope struct cd $end
-$var wire 1 5 clk $end
-$var wire 1 6 rst $end
-$upscope $end
-$var string 1 7 inp $end
-$var string 1 8 out $end
-$upscope $end
-$scope module sim_only_connects_helper_2 $end
-$scope struct cd $end
-$var wire 1 1 clk $end
-$var wire 1 2 rst $end
-$upscope $end
-$var string 1 3 inp $end
-$var string 1 4 out $end
+$var string 1 /YVv: inp $end
+$var string 1 Kk*{# out $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
-s{\"extra\":\x20\"value\"} #
-s{} $
-s{} %
-s{} &
-0'
-1(
-s{} )
-s{} *
-0+
-1,
-s{} -
-s{} .
-s{} /
-00
-01
-12
-s{} 3
-s{} 4
-05
-16
-s{} 7
-s{} 8
+0tq:(w
+1FVlgb
+s{\"extra\":\x20\"value\"} g:xf?
+s{} [OKKg
+s{} 9pB->
+s{} 8(7-4
+0$Kwp\
+1nmVq'
+s{} qS)@z
+s{} ~je//
+s{} CyjVm
+0z~g{\
+0Ph.=#
+1!GXK\
+s{} /YVv:
+s{} Kk*{#
 $end
 #1000000
-1!
-s{\"extra\":\x20\"value\"} $
-1'
-s{\"extra\":\x20\"value\"} )
-1+
-s{\"extra\":\x20\"value\"} -
-10
-11
-15
-s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} %
-s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} *
-s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} .
-s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3
-s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7
-s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} &
-s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4
-s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8
+1tq:(w
+s{\"extra\":\x20\"value\"} [OKKg
+1$Kwp\
+s{\"extra\":\x20\"value\"} qS)@z
+1z~g{\
+1Ph.=#
+s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB->
+s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je//
+s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv:
+s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4
+s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{#
 #2000000
-0!
-0"
-0'
-0(
-0+
-0,
-01
-02
-05
-06
+0tq:(w
+0FVlgb
+0$Kwp\
+0nmVq'
+0Ph.=#
+0!GXK\
 #3000000
-1!
-1'
-1+
-s{\"extra\":\x20\"value\"} /
-00
-11
-15
+1tq:(w
+1$Kwp\
+s{\"extra\":\x20\"value\"} CyjVm
+0z~g{\
+1Ph.=#
 #4000000
-0!
-0'
-0+
-01
-05
+0tq:(w
+0$Kwp\
+0Ph.=#
 #5000000
-1!
-1'
-1+
-11
-15
+1tq:(w
+1$Kwp\
+1Ph.=#
 #6000000
-0!
-0'
-0+
-01
-05
+0tq:(w
+0$Kwp\
+0Ph.=#
 #7000000
-1!
-1'
-1+
-11
-15
+1tq:(w
+1$Kwp\
+1Ph.=#
 #8000000
-0!
-0'
-0+
-01
-05
+0tq:(w
+0$Kwp\
+0Ph.=#
 #9000000
-1!
-1'
-1+
-11
-15
+1tq:(w
+1$Kwp\
+1Ph.=#
 #10000000
-0!
-0'
-0+
-01
-05
+0tq:(w
+0$Kwp\
+0Ph.=#
 #11000000
-1!
-1'
-1+
-11
-15
+1tq:(w
+1$Kwp\
+1Ph.=#
 #12000000
-0!
-0'
-0+
-01
-05
+0tq:(w
+0$Kwp\
+0Ph.=#
 #13000000
-1!
-1'
-1+
-11
-15
+1tq:(w
+1$Kwp\
+1Ph.=#
 #14000000
-0!
-0'
-0+
-01
-05
+0tq:(w
+0$Kwp\
+0Ph.=#
 #15000000
-1!
-1'
-1+
-11
-15
+1tq:(w
+1$Kwp\
+1Ph.=#
 #16000000

crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd

@@ -1,68 +1,68 @@
 $timescale 1 ps $end
 $scope module sim_resettable_counter $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 zGup) clk $end
+$var wire 1 TfzI\ rst $end
 $upscope $end
-$var wire 8 # out $end
+$var wire 8 #$b%i out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-0"
-b0 #
+0zGup)
+0TfzI\
+b0 #$b%i
 $end
 #1000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #2000000
-0!
-1"
-b0 #
+0zGup)
+1TfzI\
+b0 #$b%i
 #3000000
-1!
+1zGup)
 #4000000
-0!
-0"
+0zGup)
+0TfzI\
 #5000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #6000000
-0!
+0zGup)
 #7000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #8000000
-0!
+0zGup)
 #9000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #10000000
-0!
+0zGup)
 #11000000
-1!
-b100 #
+1zGup)
+b100 #$b%i
 #12000000
-0!
-1"
-b0 #
+0zGup)
+1TfzI\
+b0 #$b%i
 #13000000
-1!
+1zGup)
 #14000000
-0!
-0"
+0zGup)
+0TfzI\
 #15000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #16000000
-0!
+0zGup)
 #17000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #18000000
-0!
+0zGup)
 #19000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #20000000
-0!
+0zGup)

crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd

@@ -1,65 +1,65 @@
 $timescale 1 ps $end
 $scope module sim_resettable_counter $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 zGup) clk $end
+$var wire 1 TfzI\ rst $end
 $upscope $end
-$var wire 8 # out $end
+$var wire 8 #$b%i out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
-b0 #
+0zGup)
+1TfzI\
+b0 #$b%i
 $end
 #1000000
-1!
+1zGup)
 #2000000
-0!
+0zGup)
 #3000000
-1!
+1zGup)
 #4000000
-0!
-0"
+0zGup)
+0TfzI\
 #5000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #6000000
-0!
+0zGup)
 #7000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #8000000
-0!
+0zGup)
 #9000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #10000000
-0!
+0zGup)
 #11000000
-1!
-b100 #
+1zGup)
+b100 #$b%i
 #12000000
-0!
-1"
-b0 #
+0zGup)
+1TfzI\
+b0 #$b%i
 #13000000
-1!
+1zGup)
 #14000000
-0!
-0"
+0zGup)
+0TfzI\
 #15000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #16000000
-0!
+0zGup)
 #17000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #18000000
-0!
+0zGup)
 #19000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #20000000
-0!
+0zGup)

crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd

@@ -1,70 +1,70 @@
 $timescale 1 ps $end
 $scope module sim_resettable_counter $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 zGup) clk $end
+$var wire 1 TfzI\ rst $end
 $upscope $end
-$var wire 8 # out $end
+$var wire 8 #$b%i out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-0"
-b0 #
+0zGup)
+0TfzI\
+b0 #$b%i
 $end
 #1000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #2000000
-0!
-1"
+0zGup)
+1TfzI\
 #3000000
-1!
-b10 #
-b0 #
+1zGup)
+b10 #$b%i
+b0 #$b%i
 #4000000
-0!
-0"
+0zGup)
+0TfzI\
 #5000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #6000000
-0!
+0zGup)
 #7000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #8000000
-0!
+0zGup)
 #9000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #10000000
-0!
+0zGup)
 #11000000
-1!
-b100 #
+1zGup)
+b100 #$b%i
 #12000000
-0!
-1"
+0zGup)
+1TfzI\
 #13000000
-1!
-b101 #
-b0 #
+1zGup)
+b101 #$b%i
+b0 #$b%i
 #14000000
-0!
-0"
+0zGup)
+0TfzI\
 #15000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #16000000
-0!
+0zGup)
 #17000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #18000000
-0!
+0zGup)
 #19000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #20000000
-0!
+0zGup)

crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd

@@ -1,70 +1,70 @@
 $timescale 1 ps $end
 $scope module sim_resettable_counter $end
 $scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
+$var wire 1 zGup) clk $end
+$var wire 1 TfzI\ rst $end
 $upscope $end
-$var wire 8 # out $end
+$var wire 8 #$b%i out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-0!
-1"
-b0 #
+0zGup)
+1TfzI\
+b0 #$b%i
 $end
 #1000000
-1!
-b1 #
-b0 #
+1zGup)
+b1 #$b%i
+b0 #$b%i
 #2000000
-0!
+0zGup)
 #3000000
-1!
-b1 #
-b0 #
+1zGup)
+b1 #$b%i
+b0 #$b%i
 #4000000
-0!
-0"
+0zGup)
+0TfzI\
 #5000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #6000000
-0!
+0zGup)
 #7000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #8000000
-0!
+0zGup)
 #9000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #10000000
-0!
+0zGup)
 #11000000
-1!
-b100 #
+1zGup)
+b100 #$b%i
 #12000000
-0!
-1"
+0zGup)
+1TfzI\
 #13000000
-1!
-b101 #
-b0 #
+1zGup)
+b101 #$b%i
+b0 #$b%i
 #14000000
-0!
-0"
+0zGup)
+0TfzI\
 #15000000
-1!
-b1 #
+1zGup)
+b1 #$b%i
 #16000000
-0!
+0zGup)
 #17000000
-1!
-b10 #
+1zGup)
+b10 #$b%i
 #18000000
-0!
+0zGup)
 #19000000
-1!
-b11 #
+1zGup)
+b11 #$b%i
 #20000000
-0!
+0zGup)

crates/fayalite/tests/ui/simvalue_is_not_internable.stderr

@@ -1,107 +1,107 @@
 error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:11:26
-   |
-11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
-   |                          ^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`
-   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+ --> tests/ui/simvalue_is_not_internable.rs:11:26
+  |
+ 11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+    |                          ^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+    |
+    = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`
+    = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+   --> src/util/alternating_cell.rs
+    |
+ 22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+    |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+   --> src/sim/value.rs
+    |
+    | pub struct SimValue<T: Type> {
+    |            ^^^^^^^^
 note: required by a bound in `fayalite::intern::Interned`
-  --> src/intern.rs
-   |
-   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
-   |                                                  ^^^^ required by this bound in `Interned`
+   --> src/intern.rs
+    |
+    | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+    |                                                  ^^^^ required by this bound in `Interned`
 
 error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:11:26
-   |
-11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
-   |                          ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`
+ --> tests/ui/simvalue_is_not_internable.rs:11:26
+  |
+ 11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+    |                          ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+    |
+    = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+   --> src/util/alternating_cell.rs
+    |
+ 22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+    |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+   --> src/sim/value.rs
+    |
+    | pub struct SimValue<T: Type> {
+    |            ^^^^^^^^
 note: required by a bound in `fayalite::intern::Interned`
-  --> src/intern.rs
-   |
-   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
-   |                                                  ^^^^ required by this bound in `Interned`
+   --> src/intern.rs
+    |
+    | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+    |                                                  ^^^^ required by this bound in `Interned`
 
 error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:11:26
-   |
-11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
-   |                          ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
+ --> tests/ui/simvalue_is_not_internable.rs:11:26
+  |
+  11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+     |                          ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
+     |
+     = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
 note: required because it appears within the type `DynSimOnlyValue`
-  --> src/sim/value/sim_only_value_unsafe.rs
-   |
-   | pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
-   |            ^^^^^^^^^^^^^^^
+    --> src/sim/value/sim_only_value_unsafe.rs
+     |
+ 271 | pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
+     |            ^^^^^^^^^^^^^^^
 note: required because it appears within the type `PhantomData<DynSimOnlyValue>`
-  --> $RUST/core/src/marker.rs
-   |
-   | pub struct PhantomData<T: PointeeSized>;
-   |            ^^^^^^^^^^^
+    --> $RUST/core/src/marker.rs
+     |
+ 819 | pub struct PhantomData<T: PointeeSized>;
+     |            ^^^^^^^^^^^
 note: required because it appears within the type `alloc::raw_vec::RawVec<DynSimOnlyValue>`
-  --> $RUST/alloc/src/raw_vec/mod.rs
-   |
-   | pub(crate) struct RawVec<T, A: Allocator = Global> {
-   |                   ^^^^^^
+    --> $RUST/alloc/src/raw_vec/mod.rs
+     |
+  73 | pub(crate) struct RawVec<T, A: Allocator = Global> {
+     |                   ^^^^^^
 note: required because it appears within the type `Vec<DynSimOnlyValue>`
-  --> $RUST/alloc/src/vec/mod.rs
-   |
-   | pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
-   |            ^^^
+    --> $RUST/alloc/src/vec/mod.rs
+     |
+ 438 | pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
+     |            ^^^
 note: required because it appears within the type `OpaqueSimValue`
-  --> src/ty.rs
-   |
-   | pub struct OpaqueSimValue {
-   |            ^^^^^^^^^^^^^^
+    --> src/ty.rs
+     |
+ 734 | pub struct OpaqueSimValue {
+     |            ^^^^^^^^^^^^^^
 note: required because it appears within the type `value::SimValueInner<()>`
-  --> src/sim/value.rs
-   |
-   | struct SimValueInner<T: Type> {
-   |        ^^^^^^^^^^^^^
+    --> src/sim/value.rs
+     |
+  51 | struct SimValueInner<T: Type> {
+     |        ^^^^^^^^^^^^^
 note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
-  --> $RUST/core/src/cell.rs
-   |
-   | pub struct UnsafeCell<T: ?Sized> {
-   |            ^^^^^^^^^^
+    --> $RUST/core/src/cell.rs
+     |
+     | pub struct UnsafeCell<T: ?Sized> {
+     |            ^^^^^^^^^^
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+    --> src/util/alternating_cell.rs
+     |
+  22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+     |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+    --> src/sim/value.rs
+     |
+ 160 | pub struct SimValue<T: Type> {
+     |            ^^^^^^^^
 note: required by a bound in `fayalite::intern::Interned`
-  --> src/intern.rs
-   |
-   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
-   |                                           ^^^^ required by this bound in `Interned`
+    --> src/intern.rs
+     |
+ 648 | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+     |                                           ^^^^ required by this bound in `Interned`
 
 error[E0277]: the trait bound `fayalite::prelude::SimValue<()>: Intern` is not satisfied
   --> tests/ui/simvalue_is_not_internable.rs:12:26
@@ -118,238 +118,238 @@ help: consider dereferencing here
    |                          +
 
 error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:12:26
-   |
-12 |     Intern::intern_sized(v)
-   |     -------------------- ^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
-   |     |
-   |     required by a bound introduced by this call
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`
-   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+ --> tests/ui/simvalue_is_not_internable.rs:12:26
+  |
+ 12 |     Intern::intern_sized(v)
+    |     -------------------- ^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+    |     |
+    |     required by a bound introduced by this call
+    |
+    = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`
+    = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+   --> src/util/alternating_cell.rs
+    |
+ 22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+    |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+   --> src/sim/value.rs
+    |
+    | pub struct SimValue<T: Type> {
+    |            ^^^^^^^^
 note: required by a bound in `intern_sized`
-  --> src/intern.rs
-   |
-   | pub trait Intern: Any + Send + Sync {
-   |                                ^^^^ required by this bound in `Intern::intern_sized`
+   --> src/intern.rs
+    |
+    | pub trait Intern: Any + Send + Sync {
+    |                                ^^^^ required by this bound in `Intern::intern_sized`
 ...
-   |     fn intern_sized(self) -> Interned<Self>
-   |        ------------ required by a bound in this associated function
+    |     fn intern_sized(self) -> Interned<Self>
+    |        ------------ required by a bound in this associated function
 help: consider dereferencing here
-   |
-12 |     Intern::intern_sized(*v)
-   |                          +
+    |
+ 12 |     Intern::intern_sized(*v)
+    |                          +
 
 error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:12:26
-   |
-12 |     Intern::intern_sized(v)
-   |     -------------------- ^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
-   |     |
-   |     required by a bound introduced by this call
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`
+ --> tests/ui/simvalue_is_not_internable.rs:12:26
+  |
+ 12 |     Intern::intern_sized(v)
+    |     -------------------- ^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+    |     |
+    |     required by a bound introduced by this call
+    |
+    = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+   --> src/util/alternating_cell.rs
+    |
+ 22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+    |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+   --> src/sim/value.rs
+    |
+    | pub struct SimValue<T: Type> {
+    |            ^^^^^^^^
 note: required by a bound in `intern_sized`
-  --> src/intern.rs
-   |
-   | pub trait Intern: Any + Send + Sync {
-   |                                ^^^^ required by this bound in `Intern::intern_sized`
+   --> src/intern.rs
+    |
+    | pub trait Intern: Any + Send + Sync {
+    |                                ^^^^ required by this bound in `Intern::intern_sized`
 ...
-   |     fn intern_sized(self) -> Interned<Self>
-   |        ------------ required by a bound in this associated function
+    |     fn intern_sized(self) -> Interned<Self>
+    |        ------------ required by a bound in this associated function
 help: consider dereferencing here
-   |
-12 |     Intern::intern_sized(*v)
-   |                          +
+    |
+ 12 |     Intern::intern_sized(*v)
+    |                          +
 
 error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:12:26
-   |
-12 |     Intern::intern_sized(v)
-   |     -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
-   |     |
-   |     required by a bound introduced by this call
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
+ --> tests/ui/simvalue_is_not_internable.rs:12:26
+  |
+  12 |     Intern::intern_sized(v)
+     |     -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
+     |     |
+     |     required by a bound introduced by this call
+     |
+     = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
 note: required because it appears within the type `DynSimOnlyValue`
-  --> src/sim/value/sim_only_value_unsafe.rs
-   |
-   | pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
-   |            ^^^^^^^^^^^^^^^
+    --> src/sim/value/sim_only_value_unsafe.rs
+     |
+ 271 | pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
+     |            ^^^^^^^^^^^^^^^
 note: required because it appears within the type `PhantomData<DynSimOnlyValue>`
-  --> $RUST/core/src/marker.rs
-   |
-   | pub struct PhantomData<T: PointeeSized>;
-   |            ^^^^^^^^^^^
+    --> $RUST/core/src/marker.rs
+     |
+ 819 | pub struct PhantomData<T: PointeeSized>;
+     |            ^^^^^^^^^^^
 note: required because it appears within the type `alloc::raw_vec::RawVec<DynSimOnlyValue>`
-  --> $RUST/alloc/src/raw_vec/mod.rs
-   |
-   | pub(crate) struct RawVec<T, A: Allocator = Global> {
-   |                   ^^^^^^
+    --> $RUST/alloc/src/raw_vec/mod.rs
+     |
+  73 | pub(crate) struct RawVec<T, A: Allocator = Global> {
+     |                   ^^^^^^
 note: required because it appears within the type `Vec<DynSimOnlyValue>`
-  --> $RUST/alloc/src/vec/mod.rs
-   |
-   | pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
-   |            ^^^
+    --> $RUST/alloc/src/vec/mod.rs
+     |
+ 438 | pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
+     |            ^^^
 note: required because it appears within the type `OpaqueSimValue`
-  --> src/ty.rs
-   |
-   | pub struct OpaqueSimValue {
-   |            ^^^^^^^^^^^^^^
+    --> src/ty.rs
+     |
+ 734 | pub struct OpaqueSimValue {
+     |            ^^^^^^^^^^^^^^
 note: required because it appears within the type `value::SimValueInner<()>`
-  --> src/sim/value.rs
-   |
-   | struct SimValueInner<T: Type> {
-   |        ^^^^^^^^^^^^^
+    --> src/sim/value.rs
+     |
+  51 | struct SimValueInner<T: Type> {
+     |        ^^^^^^^^^^^^^
 note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
-  --> $RUST/core/src/cell.rs
-   |
-   | pub struct UnsafeCell<T: ?Sized> {
-   |            ^^^^^^^^^^
+    --> $RUST/core/src/cell.rs
+     |
+     | pub struct UnsafeCell<T: ?Sized> {
+     |            ^^^^^^^^^^
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+    --> src/util/alternating_cell.rs
+     |
+  22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+     |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+    --> src/sim/value.rs
+     |
+ 160 | pub struct SimValue<T: Type> {
+     |            ^^^^^^^^
 note: required by a bound in `intern_sized`
-  --> src/intern.rs
-   |
-   | pub trait Intern: Any + Send + Sync {
-   |                         ^^^^ required by this bound in `Intern::intern_sized`
+    --> src/intern.rs
+     |
+ 596 | pub trait Intern: Any + Send + Sync {
+     |                         ^^^^ required by this bound in `Intern::intern_sized`
 ...
-   |     fn intern_sized(self) -> Interned<Self>
-   |        ------------ required by a bound in this associated function
+ 604 |     fn intern_sized(self) -> Interned<Self>
+     |        ------------ required by a bound in this associated function
 help: consider dereferencing here
-   |
-12 |     Intern::intern_sized(*v)
-   |                          +
+     |
+  12 |     Intern::intern_sized(*v)
+     |                          +
 
 error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:12:5
-   |
-12 |     Intern::intern_sized(v)
-   |     ^^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`
-   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+ --> tests/ui/simvalue_is_not_internable.rs:12:5
+  |
+ 12 |     Intern::intern_sized(v)
+    |     ^^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+    |
+    = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`
+    = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+   --> src/util/alternating_cell.rs
+    |
+ 22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+    |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+   --> src/sim/value.rs
+    |
+    | pub struct SimValue<T: Type> {
+    |            ^^^^^^^^
 note: required by a bound in `fayalite::intern::Interned`
-  --> src/intern.rs
-   |
-   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
-   |                                                  ^^^^ required by this bound in `Interned`
+   --> src/intern.rs
+    |
+    | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+    |                                                  ^^^^ required by this bound in `Interned`
 
 error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:12:5
-   |
-12 |     Intern::intern_sized(v)
-   |     ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`
+ --> tests/ui/simvalue_is_not_internable.rs:12:5
+  |
+ 12 |     Intern::intern_sized(v)
+    |     ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+    |
+    = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+   --> src/util/alternating_cell.rs
+    |
+ 22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+    |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+   --> src/sim/value.rs
+    |
+    | pub struct SimValue<T: Type> {
+    |            ^^^^^^^^
 note: required by a bound in `fayalite::intern::Interned`
-  --> src/intern.rs
-   |
-   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
-   |                                                  ^^^^ required by this bound in `Interned`
+   --> src/intern.rs
+    |
+    | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+    |                                                  ^^^^ required by this bound in `Interned`
 
 error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
-  --> tests/ui/simvalue_is_not_internable.rs:12:5
-   |
-12 |     Intern::intern_sized(v)
-   |     ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
-   |
-   = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
+ --> tests/ui/simvalue_is_not_internable.rs:12:5
+  |
+  12 |     Intern::intern_sized(v)
+     |     ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely
+     |
+     = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>`
 note: required because it appears within the type `DynSimOnlyValue`
-  --> src/sim/value/sim_only_value_unsafe.rs
-   |
-   | pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
-   |            ^^^^^^^^^^^^^^^
+    --> src/sim/value/sim_only_value_unsafe.rs
+     |
+ 271 | pub struct DynSimOnlyValue(Rc<dyn DynSimOnlyValueTrait>);
+     |            ^^^^^^^^^^^^^^^
 note: required because it appears within the type `PhantomData<DynSimOnlyValue>`
-  --> $RUST/core/src/marker.rs
-   |
-   | pub struct PhantomData<T: PointeeSized>;
-   |            ^^^^^^^^^^^
+    --> $RUST/core/src/marker.rs
+     |
+ 819 | pub struct PhantomData<T: PointeeSized>;
+     |            ^^^^^^^^^^^
 note: required because it appears within the type `alloc::raw_vec::RawVec<DynSimOnlyValue>`
-  --> $RUST/alloc/src/raw_vec/mod.rs
-   |
-   | pub(crate) struct RawVec<T, A: Allocator = Global> {
-   |                   ^^^^^^
+    --> $RUST/alloc/src/raw_vec/mod.rs
+     |
+  73 | pub(crate) struct RawVec<T, A: Allocator = Global> {
+     |                   ^^^^^^
 note: required because it appears within the type `Vec<DynSimOnlyValue>`
-  --> $RUST/alloc/src/vec/mod.rs
-   |
-   | pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
-   |            ^^^
+    --> $RUST/alloc/src/vec/mod.rs
+     |
+ 438 | pub struct Vec<T, #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global> {
+     |            ^^^
 note: required because it appears within the type `OpaqueSimValue`
-  --> src/ty.rs
-   |
-   | pub struct OpaqueSimValue {
-   |            ^^^^^^^^^^^^^^
+    --> src/ty.rs
+     |
+ 734 | pub struct OpaqueSimValue {
+     |            ^^^^^^^^^^^^^^
 note: required because it appears within the type `value::SimValueInner<()>`
-  --> src/sim/value.rs
-   |
-   | struct SimValueInner<T: Type> {
-   |        ^^^^^^^^^^^^^
+    --> src/sim/value.rs
+     |
+  51 | struct SimValueInner<T: Type> {
+     |        ^^^^^^^^^^^^^
 note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
-  --> $RUST/core/src/cell.rs
-   |
-   | pub struct UnsafeCell<T: ?Sized> {
-   |            ^^^^^^^^^^
+    --> $RUST/core/src/cell.rs
+     |
+     | pub struct UnsafeCell<T: ?Sized> {
+     |            ^^^^^^^^^^
 note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
-  --> src/util/alternating_cell.rs
-   |
-   | pub(crate) struct AlternatingCell<T: ?Sized> {
-   |                   ^^^^^^^^^^^^^^^
+    --> src/util/alternating_cell.rs
+     |
+  22 | pub(crate) struct AlternatingCell<T: ?Sized> {
+     |                   ^^^^^^^^^^^^^^^
 note: required because it appears within the type `fayalite::prelude::SimValue<()>`
-  --> src/sim/value.rs
-   |
-   | pub struct SimValue<T: Type> {
-   |            ^^^^^^^^
+    --> src/sim/value.rs
+     |
+ 160 | pub struct SimValue<T: Type> {
+     |            ^^^^^^^^
 note: required by a bound in `fayalite::intern::Interned`
-  --> src/intern.rs
-   |
-   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
-   |                                           ^^^^ required by this bound in `Interned`
+    --> src/intern.rs
+     |
+ 648 | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+     |                                           ^^^^ required by this bound in `Interned`

rocq-demo/.gitignore

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
+.CoqMakefile.d
+*.aux
+CoqMakefile
+CoqMakefile.conf
+*.glob
+*.vo*

rocq-demo/Makefile

@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
+#
+# Example Makefile wrapper as given on the Rocq documentation
+# https://rocq-prover.org/doc/V9.1.0/refman/practical-tools/utilities.html#building-a-rocq-project-with-rocq-makefile-details
+
+# KNOWNTARGETS will not be passed along to CoqMakefile
+KNOWNTARGETS := CoqMakefile
+# KNOWNFILES will not get implicit targets from the final rule, and so
+# depending on them won't invoke the submake
+# Warning: These files get declared as PHONY, so any targets depending
+# on them always get rebuilt
+KNOWNFILES   := Makefile _CoqProject
+
+.DEFAULT_GOAL := invoke-coq-makefile
+
+CoqMakefile: Makefile _CoqProject
+	$(COQBIN)rocq makefile -f _CoqProject -o CoqMakefile
+
+invoke-coq-makefile: CoqMakefile
+	$(MAKE) --no-print-directory -f CoqMakefile $(filter-out $(KNOWNTARGETS),$(MAKECMDGOALS))
+
+.PHONY: invoke-coq-makefile $(KNOWNFILES)
+
+####################################################################
+##                      Your targets here                         ##
+####################################################################
+
+# This should be the last rule, to handle any targets not declared above
+%: invoke-coq-makefile
+	@true

rocq-demo/_CoqProject

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
+
+-Q . RocqDemo
+.

scripts/check-copyright.sh

@@ -50,7 +50,7 @@ function main()
         /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt)
             # file that can't contain copyright header
             ;;
-        /.forgejo/workflows/*.yml|*/.gitignore|*.toml)
+        /.forgejo/workflows/*.yml|*/.gitignore|*.toml|*/Makefile|*/_CoqProject)
             check_file "$file" "${POUND_HEADER[@]}"
             ;;
         *.md)