programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:31:33 +00:00
040cefea21 add tx_only_uart example to readme
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:19:40 +00:00
e6dbeb2c85 add tx_only_uart example to readme
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:12:22 +00:00
3267cb38c4 build tx_only_uart in CI
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:11:11 +00:00
b3cc28e2b6 add transmit-only UART example
26840daf13 arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz
Compare 2 commits »
programmerjake created pull request libre-chip/fayalite#41 2025-10-22 12:08:27 +00:00
WIP: add transmit-only UART example
programmerjake created branch add-uart-example in programmerjake/fayalite 2025-10-22 12:07:26 +00:00
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-22 12:07:26 +00:00
671d83b186 WIP add transmit-only UART example
4d9e8d3b47 Add building blinky example to the readme
c6feea6d51 properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
2bdc8a7c72 WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it
Compare 10 commits »
programmerjake commented on issue libre-chip/grant-tracking#4 2025-10-22 06:15:57 +00:00
NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).

"Results" from request for payment for this and #6, since it's probably useful for others:

I rewrote the code for Fayalite's CLI to support being extensible from outside the Fayalite library,…

programmerjake pushed to master at libre-chip/fayalite 2025-10-22 06:11:43 +00:00
4d9e8d3b47 Add building blinky example to the readme
programmerjake deleted branch add-blinky-to-readme from programmerjake/fayalite 2025-10-22 06:11:43 +00:00
programmerjake merged pull request libre-chip/fayalite#40 2025-10-22 06:11:42 +00:00
Add building blinky example to the readme
programmerjake created pull request libre-chip/fayalite#40 2025-10-22 06:01:23 +00:00
Add building blinky example to the readme
programmerjake created branch add-blinky-to-readme in programmerjake/fayalite 2025-10-22 06:00:49 +00:00
programmerjake pushed to add-blinky-to-readme at programmerjake/fayalite 2025-10-22 06:00:49 +00:00
4d9e8d3b47 Add building blinky example to the readme
c6feea6d51 properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
2bdc8a7c72 WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it
477a1f2d29 Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!
Compare 10 commits »
programmerjake deleted branch fpga-support-and-arty-a7-100t from programmerjake/fayalite 2025-10-22 05:36:16 +00:00
programmerjake pushed to master at libre-chip/fayalite 2025-10-22 05:36:15 +00:00
c6feea6d51 properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
2bdc8a7c72 WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it
477a1f2d29 Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!
4d54f903be move vendor module to top level
Compare 20 commits »
programmerjake merged pull request libre-chip/fayalite#38 2025-10-22 05:36:13 +00:00
fpga support and arty a7 100t
programmerjake closed issue libre-chip/grant-tracking#4 2025-10-22 05:36:13 +00:00
NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).
programmerjake closed issue libre-chip/grant-tracking#6 2025-10-22 05:36:13 +00:00
NLnet 2024-12-324 Add support for the Arty A7 100T since that's what we're using for CI.
programmerjake commented on pull request libre-chip/fayalite#38 2025-10-22 05:29:35 +00:00
fpga support and arty a7 100t

@programmerjake wrote in libre-chip/fayalite#38 (comment):

also I need to adjust the generated xdc so the clock properly gets the frequency constraint…