programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to next-pc at programmerjake/cpu 2025-11-28 09:42:11 +00:00
dca59a24ec WIP adding next_pc: add call stack
programmerjake pushed to next-pc at programmerjake/cpu 2025-11-27 09:30:55 +00:00
cd769a958d WIP adding next_pc: added mock_fetch_decode_pipe
programmerjake pushed to next-pc at programmerjake/cpu 2025-11-26 06:50:14 +00:00
a927451f8c WIP adding next_pc: added mock_fetch_decode_pipe
programmerjake pushed to next-pc at programmerjake/cpu 2025-11-24 09:00:05 +00:00
e835a2f0f5 WIP adding next_pc
688732ec4c add Serialize/Deserialize impls for CpuConfig
f2af2d1859 update for new fayalite
28b1f1d728 update Fayalite to get new features and bug fixes
Compare 4 commits »
programmerjake pushed to master at libre-chip/fayalite 2025-11-24 08:22:51 +00:00
9e803223d0 support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
2a65aa2bd5 fix DynShr[SU]'s literal bits to properly shift right instead of left
Compare 2 commits »
programmerjake deleted branch adding-sim-ops-traits from programmerjake/fayalite 2025-11-24 08:22:51 +00:00
programmerjake merged pull request libre-chip/fayalite#55 2025-11-24 08:22:49 +00:00
support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
programmerjake created pull request libre-chip/fayalite#55 2025-11-24 08:18:19 +00:00
support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-24 08:17:39 +00:00
9e803223d0 support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-22 00:14:42 +00:00
5f1311b0cc WIP
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-21 11:47:26 +00:00
e2ab549eb9 WIP
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-20 11:28:16 +00:00
72ce76812e WIP
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-20 10:25:21 +00:00
77dd4c3420 WIP
2a65aa2bd5 fix DynShr[SU]'s literal bits to properly shift right instead of left
Compare 2 commits »
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-20 03:33:59 +00:00
9c198cdf55 WIP
programmerjake created branch adding-sim-ops-traits in programmerjake/fayalite 2025-11-19 09:51:08 +00:00
programmerjake pushed to adding-sim-ops-traits at programmerjake/fayalite 2025-11-19 09:51:08 +00:00
14816c8c63 WIP
2817cd3d58 support Rust's default binding modes when destructuring with #[hdl(sim)] let/match
053c1b2b10 implement Display for SimValue<T>
17b58e8edb add utility impls for SimValue<ArrayType<_, _>>
df020e9c9b add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled
Compare 10 commits »
programmerjake pushed to next-pc at programmerjake/cpu 2025-11-14 09:51:55 +00:00
0143e1253b WIP adding next_pc
579f7690ea add Serialize/Deserialize impls for CpuConfig
9f1652fb11 update Fayalite to get new features and bug fixes
Compare 3 commits »
programmerjake deleted branch support-destructuring-sim-values-default-binding-modes from programmerjake/fayalite 2025-11-14 08:27:18 +00:00
programmerjake automatically merged pull request libre-chip/fayalite#54 2025-11-14 08:27:17 +00:00
programmerjake pushed to master at libre-chip/fayalite 2025-11-14 08:27:17 +00:00
2817cd3d58 support Rust's default binding modes when destructuring with #[hdl(sim)] let/match
053c1b2b10 implement Display for SimValue<T>
Compare 2 commits »