programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-24 22:42:54 +00:00
52ab134673 increase rust version to support omitting match arms with uninhabited types
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-24 22:39:56 +00:00
698b8adc23 working on deduce_resets pass
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-24 11:44:54 +00:00
59be3bd645 WIP working on implementing deduce_resets pass
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-23 00:07:44 +00:00
913baa37e9 WIP adding deduce_resets pass
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-21 06:54:26 +00:00
11ddbc43c7 writing VCD for combinatorial circuits works!
c4b5d00419 WIP adding VCD output
09aa9fbc78 wire up simulator trace writing interface
288a6b71b9 WIP adding VCD output
0095570f19 simple combinatorial simulation works!
Compare 14 commits »
programmerjake pushed to master at libre-chip/fayalite 2024-11-21 06:52:55 +00:00
3ea0d98924 always write formal cache json
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-21 06:37:04 +00:00
e2653a3245 writing VCD for combinatorial circuits works!
f8b0ab45b0 WIP adding VCD output
01dafcea0f wire up simulator trace writing interface
18ddab26ba WIP adding VCD output
2842c2839f simple combinatorial simulation works!
Compare 14 commits »
programmerjake commented on pull request libre-chip/fayalite#2 2024-11-20 22:02:13 +00:00
Add test module exercising formal verification.

Thanks!

programmerjake pushed to master at libre-chip/fayalite 2024-11-20 21:40:37 +00:00
c1f1a8b749 Add test module exercising formal verification.
programmerjake merged pull request libre-chip/fayalite#2 2024-11-20 21:40:35 +00:00
Add test module exercising formal verification.
programmerjake created pull request libre-chip/fayalite#3 2024-11-20 21:27:13 +00:00
WIP: add a simulator
programmerjake commented on pull request libre-chip/fayalite#2 2024-11-20 21:23:21 +00:00
Add test module exercising formal verification.

it's more idiomatic to use a match statement here instead of a separate if let for each enum variant, that also ensures you've covered all enum variants. so like:

programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-18 11:04:22 +00:00
16ea6850c8 WIP adding VCD output
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-18 05:03:21 +00:00
904752fa0c wire up simulator trace writing interface
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-17 09:02:51 +00:00
6eef3c23b5 WIP adding VCD output
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-15 04:29:08 +00:00
414a2d74f1 simple combinatorial simulation works!
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-14 05:21:08 +00:00
2e9d5c1835 Simulation::settle_step() works for simple modules
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-13 12:15:02 +00:00
d7d8e2e7ce simulator WIP: use petgraph for topological sort over assignments
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-13 06:11:27 +00:00
f780e31622 working on simulator...
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-11-12 09:09:56 +00:00
5b2abd3fca working on simulator