programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to master at libre-chip/fayalite 2025-12-15 05:03:59 +00:00
c97b44d9d6 simplify SimValue Debug format, making complex structures much easier to read
programmerjake deleted branch simplify-simvalue-debug from programmerjake/fayalite 2025-12-15 05:03:59 +00:00
programmerjake pushed to simplify-simvalue-debug at programmerjake/fayalite 2025-12-15 05:00:00 +00:00
c97b44d9d6 simplify SimValue Debug format, making complex structures much easier to read
programmerjake created pull request libre-chip/fayalite#58 2025-12-15 04:42:52 +00:00
simplify SimValue Debug format, making complex structures much easier to read
programmerjake created branch simplify-simvalue-debug in programmerjake/fayalite 2025-12-15 04:42:16 +00:00
programmerjake pushed to simplify-simvalue-debug at programmerjake/fayalite 2025-12-15 04:42:16 +00:00
0f94dc6dcd simplify SimValue Debug format, making complex structures much easier to read
fbe4585578 add FillInDefaultedGenerics<Type = Self> bound for SizeType
e4210a672f Check copyright header in Rocq files.
e54558d848 Demonstrates state with multiple variables and hidden state.
46f3519c76 Demonstrate a preliminary mapping from HDL to Rocq.
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programmerjake pushed to next-pc at programmerjake/cpu 2025-12-15 04:39:59 +00:00
f39f40ce1f fix next_pc::Queue and add test
programmerjake pushed to next-pc at programmerjake/cpu 2025-12-14 09:26:42 +00:00
cbd52c60a8 WIP: next_pc test fails
c87a1b8e1e wrote out all of next_pc and tests/next_pc
Compare 2 commits »
programmerjake pushed to next-pc at programmerjake/cpu 2025-12-12 13:34:12 +00:00
6a4881ca25 WIP
programmerjake pushed to next-pc at programmerjake/cpu 2025-12-12 04:55:36 +00:00
398bbbebb5 WIP
programmerjake pushed to next-pc at programmerjake/cpu 2025-12-11 08:31:15 +00:00
f1d4e508cb WIP
cfd04469ce WIP linking next_pc stages together
231f5e72ec WIP: completed stages of next-pc logic, still need to combine them into a pipeline
033d5d4f34 WIP adding next_pc: add call stack
7a77c02cda WIP adding next_pc: added mock_fetch_decode_pipe
Compare 8 commits »
programmerjake deleted branch add-fill-in-defaulted-generics-for-size-type from programmerjake/fayalite 2025-12-11 04:27:59 +00:00
programmerjake pushed to master at libre-chip/fayalite 2025-12-11 04:27:58 +00:00
fbe4585578 add FillInDefaultedGenerics<Type = Self> bound for SizeType
programmerjake merged pull request libre-chip/fayalite#57 2025-12-11 04:27:55 +00:00
add FillInDefaultedGenerics<Type = Self> bound for SizeType
fbe4585578 add FillInDefaultedGenerics<Type = Self> bound for SizeType
e4210a672f Check copyright header in Rocq files.
e54558d848 Demonstrates state with multiple variables and hidden state.
46f3519c76 Demonstrate a preliminary mapping from HDL to Rocq.
Compare 4 commits »
programmerjake created pull request libre-chip/fayalite#57 2025-12-11 04:09:45 +00:00
add FillInDefaultedGenerics<Type = Self> bound for SizeType
0548c47496 add FillInDefaultedGenerics<Type = Self> bound for SizeType
9e803223d0 support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
2a65aa2bd5 fix DynShr[SU]'s literal bits to properly shift right instead of left
2817cd3d58 support Rust's default binding modes when destructuring with #[hdl(sim)] let/match
053c1b2b10 implement Display for SimValue<T>
Compare 10 commits »
programmerjake pushed to next-pc at programmerjake/cpu 2025-12-10 06:37:11 +00:00
1d8adba04c WIP linking next_pc stages together
programmerjake pushed to master at libre-chip/fayalite 2025-12-09 16:34:38 +00:00
e4210a672f Check copyright header in Rocq files.
e54558d848 Demonstrates state with multiple variables and hidden state.
46f3519c76 Demonstrate a preliminary mapping from HDL to Rocq.
Compare 3 commits »