programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to main at libre-chip/compile-qemu-for-decoder 2026-04-07 10:05:17 +00:00
b13cfd87f4 runs global constructors and part of qemu_init_subsystems
programmerjake pushed to main at libre-chip/compile-qemu-for-decoder 2026-04-04 02:08:37 +00:00
2fa256098d implement more instructions and functions
programmerjake pushed to main at libre-chip/compile-qemu-for-decoder 2026-04-02 11:15:09 +00:00
f64b5d7120 start running global constructors
programmerjake pushed to main at libre-chip/compile-qemu-for-decoder 2026-04-01 10:48:46 +00:00
9ed1b679c0 initial commit
programmerjake pushed to main at libre-chip/compile-qemu-for-decoder 2026-04-01 10:46:50 +00:00
861bf2c49c initial commit
programmerjake created branch main in libre-chip/compile-qemu-for-decoder 2026-04-01 10:46:49 +00:00
programmerjake created repository libre-chip/compile-qemu-for-decoder 2026-04-01 10:46:19 +00:00
programmerjake deleted branch make_vcd_modules_use_instance_names from programmerjake/cpu 2026-03-27 02:46:39 +00:00
programmerjake pushed to master at libre-chip/cpu 2026-03-27 02:46:36 +00:00
6ed04c809e update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
programmerjake automatically merged pull request libre-chip/cpu#11 2026-03-27 02:46:36 +00:00
programmerjake created pull request libre-chip/cpu#11 2026-03-27 02:24:32 +00:00
update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
programmerjake created branch make_vcd_modules_use_instance_names in programmerjake/cpu 2026-03-27 02:23:58 +00:00
6ed04c809e update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name
a1147f0f05 add sram and main_memory_and_io modules
5bdc71acc3 add memory_interface_adapter_no_split
a15367c37e add address_range to MemoryInterfaceConfig and add support to simple_uart
0d451e4e95 change MemoryInterface types to have their own config
Compare 10 commits »
programmerjake pushed to master at libre-chip/fayalite 2026-03-27 02:19:17 +00:00
80b92c7dd3 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
programmerjake deleted branch make_vcd_modules_use_instance_names from programmerjake/fayalite 2026-03-27 02:19:17 +00:00
programmerjake automatically merged pull request libre-chip/fayalite#68 2026-03-27 02:19:16 +00:00
programmerjake created pull request libre-chip/fayalite#68 2026-03-27 02:14:54 +00:00
change vcd output to have module contents under instance's name, more closely matching how it works in verilog
programmerjake created branch make_vcd_modules_use_instance_names in programmerjake/fayalite 2026-03-27 02:14:31 +00:00
80b92c7dd3 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
2aa41137d4 add simulator tests for queue()
a0b2dc085c add test that simulator handles last-connect semantics properly
a8a541b357 sim/compiler: fix registers so they properly retain their old value when not written
52c41bb5db display signals when panicking because not all inputs/outputs are written yet
Compare 10 commits »
programmerjake commented on issue libre-chip/grant-tracking#15 2026-03-26 09:28:28 +00:00
NLnet 2024-12-324 memory system: main memory and IO devices

Implemented in libre-chip/cpu#10