programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
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programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
2025-09-25 05:30:57 +00:00
programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
2025-09-24 07:41:32 +00:00
programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
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programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
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programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
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programmerjake
created branch fpga-support-and-arty-a7-100t in programmerjake/fayalite
2025-09-16 08:41:09 +00:00
programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
2025-09-16 08:41:09 +00:00
NLnet 2024-12-324 Add to the simulator in Fayalite the ability to transfer non-HDL data (e.g. HashMap) through the digital signalling mechanism, this allows using those data types when writing procedural models.
I also added this NLnet grant to Fayalite's readme: libre-chip/fayalite#36
@cesar Can you look this over before I submit a request for payment? Thanks!
programmerjake
deleted branch add-nlnet-grant-to-readme from programmerjake/fayalite
2025-09-09 06:14:24 +00:00
add NLnet grant 2024-12-324 to readme
programmerjake
created branch add-nlnet-grant-to-readme in programmerjake/fayalite
2025-09-09 06:08:59 +00:00
programmerjake
pushed to add-nlnet-grant-to-readme at programmerjake/fayalite
2025-09-09 06:08:59 +00:00
NLnet 2024-12-324 Add to the simulator in Fayalite the ability to transfer non-HDL data (e.g. HashMap) through the digital signalling mechanism, this allows using those data types when writing procedural models.
Implemented in: libre-chip/fayalite#35
programmerjake
deleted branch sim-non-hdl-data from programmerjake/fayalite
2025-09-09 05:35:26 +00:00
add support for simulator-only values