start debugging reg_alloc with simulator
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
8 changed files with 1211 additions and 37 deletions
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@ -16,8 +16,25 @@ pub struct CpuConfig {
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}
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impl CpuConfig {
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pub const DEFAULT_OUT_REG_NUM_WIDTH: usize = 4;
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pub const DEFAULT_FETCH_WIDTH: NonZeroUsize = {
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let Some(v) = NonZeroUsize::new(1) else {
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unreachable!();
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};
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v
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};
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pub fn new(unit_kinds: Vec<UnitKind>) -> Self {
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Self {
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unit_kinds,
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out_reg_num_width: Self::DEFAULT_OUT_REG_NUM_WIDTH,
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fetch_width: Self::DEFAULT_FETCH_WIDTH,
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}
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}
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pub fn non_const_unit_nums(&self) -> std::ops::Range<usize> {
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(CONST_ZERO_UNIT_NUM + 1)..(self.unit_kinds.len() + 1)
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}
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pub fn unit_num_width(&self) -> usize {
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UInt::range((CONST_ZERO_UNIT_NUM + 1)..self.unit_kinds.len()).width()
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UInt::range(self.non_const_unit_nums()).width()
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}
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pub fn unit_num(&self) -> UnitNum<DynSize> {
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UnitNum[self.unit_num_width()]
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use crate::unit::UnitMOp;
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use fayalite::prelude::*;
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use fayalite::{expr::ops::ArrayLiteral, intern::Interned, prelude::*};
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use std::marker::PhantomData;
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pub mod power_isa;
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@ -20,58 +20,138 @@ pub enum OutputIntegerMode {
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pub const MOP_IMM_WIDTH: usize = 34;
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pub const MOP_MIN_REG_WIDTH: usize = 8;
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pub const COMMON_MOP_OTHER_WIDTH: usize =
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MOP_IMM_WIDTH - (COMMON_MOP_SRC_REG_COUNT - COMMON_MOP_IMM_SRC_REG_COUNT) * MOP_MIN_REG_WIDTH;
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pub const COMMON_MOP_SRC_REG_COUNT: usize = 3;
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pub const COMMON_MOP_IMM_SRC_REG_COUNT: usize = 2;
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pub const COMMON_MOP_SRC_LEN: usize = 3;
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pub const COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM: usize = 2;
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pub const COMMON_MOP_IMM_LOW_WIDTH: usize = CommonMOpWithMaxSrcCount::IMM_WIDTH - 1;
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#[hdl]
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pub struct CommonMOp<PrefixPad: KnownSize, RegWidth: Size, SrcCount: KnownSize> {
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pub prefix_pad: UIntType<PrefixPad>,
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pub dest: UIntType<RegWidth>,
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pub src: Array<UIntType<RegWidth>, { COMMON_MOP_SRC_REG_COUNT }>,
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pub other: UInt<{ COMMON_MOP_OTHER_WIDTH }>,
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pub src: Array<UIntType<RegWidth>, { COMMON_MOP_SRC_LEN }>,
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pub imm_low: UInt<{ COMMON_MOP_IMM_LOW_WIDTH }>,
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pub imm_sign: SInt<1>,
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pub _phantom: PhantomData<SrcCount>,
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}
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#[hdl]
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pub struct CommonMOpImmParts<ImmInSrcCount: Size> {
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// fields must be in this exact order
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pub imm_low: UInt<{ COMMON_MOP_IMM_LOW_WIDTH }>,
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pub reversed_src: ArrayType<UInt<{ MOP_MIN_REG_WIDTH }>, ImmInSrcCount>,
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pub imm_sign: SInt<1>,
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}
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type CommonMOpWithMaxSrcCount = CommonMOpForImm<{ COMMON_MOP_SRC_LEN }>;
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type CommonMOpForImm<const SRC_COUNT: usize> =
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CommonMOp<ConstUsize<0>, ConstUsize<{ MOP_MIN_REG_WIDTH }>, ConstUsize<SRC_COUNT>>;
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pub const COMMON_MOP_0_IMM_WIDTH: usize = CommonMOpForImm::<0>::IMM_WIDTH;
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pub const COMMON_MOP_1_IMM_WIDTH: usize = CommonMOpForImm::<1>::IMM_WIDTH;
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pub const COMMON_MOP_2_IMM_WIDTH: usize = CommonMOpForImm::<2>::IMM_WIDTH;
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pub const COMMON_MOP_3_IMM_WIDTH: usize = CommonMOpForImm::<3>::IMM_WIDTH;
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const COMMON_MOP_0_IMM_IN_SRC_COUNT: usize = CommonMOpForImm::<0>::IMM_IN_SRC_COUNT;
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impl<PrefixPad: KnownSize, RegWidth: Size, SrcCount: KnownSize>
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CommonMOp<PrefixPad, RegWidth, SrcCount>
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{
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pub fn imm_ty(self) -> SInt {
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assert!(self.src.element().width() >= MOP_MIN_REG_WIDTH);
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assert!(SrcCount::VALUE <= COMMON_MOP_SRC_REG_COUNT);
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SInt[(COMMON_MOP_SRC_REG_COUNT - SrcCount::VALUE) * MOP_MIN_REG_WIDTH
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+ COMMON_MOP_OTHER_WIDTH]
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pub const IMM_IN_SRC_COUNT: usize = {
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assert!(SrcCount::VALUE <= COMMON_MOP_SRC_LEN, "too many sources");
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const _: () = assert!(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM <= COMMON_MOP_SRC_LEN);
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(COMMON_MOP_SRC_LEN - COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM)
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- SrcCount::VALUE.saturating_sub(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM)
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};
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pub const IMM_IN_SRC_RANGE: std::ops::Range<usize> =
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(COMMON_MOP_SRC_LEN - Self::IMM_IN_SRC_COUNT)..COMMON_MOP_SRC_LEN;
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pub const IMM_WIDTH: usize = {
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MOP_IMM_WIDTH - (COMMON_MOP_0_IMM_IN_SRC_COUNT - Self::IMM_IN_SRC_COUNT) * MOP_MIN_REG_WIDTH
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};
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pub fn imm_ty() -> SInt {
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SInt::new(Self::IMM_WIDTH)
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}
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pub fn imm_parts_ty() -> CommonMOpImmParts<DynSize> {
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let retval = CommonMOpImmParts[Self::IMM_IN_SRC_COUNT];
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assert_eq!(
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retval.canonical().bit_width(),
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Self::IMM_WIDTH,
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"{retval:#?}"
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);
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retval
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}
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#[hdl]
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pub fn new(
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prefix_pad: impl ToExpr<Type = UIntType<PrefixPad>>,
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dest: impl ToExpr<Type = UIntType<RegWidth>>,
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src: impl ToExpr<Type = ArrayType<UIntType<RegWidth>, SrcCount>>,
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imm: impl ToExpr<Type = SInt>,
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) -> Expr<Self> {
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let prefix_pad = prefix_pad.to_expr();
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let dest = dest.to_expr();
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let src_in = src.to_expr();
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let imm = imm.to_expr();
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assert_eq!(Expr::ty(imm), Self::imm_ty());
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let reg_ty = Expr::ty(dest);
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assert_eq!(reg_ty, Expr::ty(src_in).element());
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let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
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let mut src = [0_hdl_u0.cast_to(reg_ty); COMMON_MOP_SRC_LEN];
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for i in 0..SrcCount::VALUE {
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src[i] = src_in[i];
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}
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for (reversed_src_index, src_index) in Self::IMM_IN_SRC_RANGE.rev().enumerate() {
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src[src_index] = imm_parts.reversed_src[reversed_src_index].cast_to(reg_ty);
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}
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#[hdl]
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Self {
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prefix_pad,
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dest,
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src: ArrayLiteral::new(
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reg_ty,
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Interned::from_iter(src.iter().map(|v| Expr::canonical(*v))),
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)
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.to_expr(),
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imm_low: Expr::from_dyn_int(imm[..COMMON_MOP_IMM_LOW_WIDTH]),
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imm_sign: Expr::from_dyn_int(imm >> (Self::IMM_WIDTH - 1)),
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_phantom: PhantomData,
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}
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}
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#[hdl]
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pub fn imm(expr: impl ToExpr<Type = Self>) -> Expr<SInt> {
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let expr = expr.to_expr();
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assert!(Expr::ty(expr).src.element().width() >= MOP_MIN_REG_WIDTH);
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let mut acc = expr.other[..COMMON_MOP_OTHER_WIDTH - 1];
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for i in SrcCount::VALUE..COMMON_MOP_SRC_REG_COUNT {
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acc = (acc, expr.src[i][..MOP_MIN_REG_WIDTH]).cast_to_bits();
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}
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acc = (acc, expr.other[COMMON_MOP_OTHER_WIDTH - 1]).cast_to_bits();
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#[hdl]
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let imm = wire(Expr::ty(expr).imm_ty());
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debug_assert_eq!(Expr::ty(acc).width(), Expr::ty(imm).width());
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connect(imm, acc.cast_to(Expr::ty(imm)));
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imm
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let reversed_src = Vec::from_iter(
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Self::IMM_IN_SRC_RANGE
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.rev()
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.map(|src_index| expr.src[src_index].cast_to_static()),
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);
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let imm_parts = {
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#[hdl]
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CommonMOpImmParts {
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imm_low: expr.imm_low,
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reversed_src,
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imm_sign: expr.imm_sign,
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}
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};
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imm_parts.cast_to_bits().cast_bits_to(Self::imm_ty())
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}
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#[hdl]
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pub fn connect_to_imm(expr: impl ToExpr<Type = Self>, imm: impl ToExpr<Type = SInt>) {
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let expr = expr.to_expr();
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let reg_ty = Expr::ty(expr).dest;
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assert_eq!(reg_ty, Expr::ty(expr).src.element());
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let imm = imm.to_expr();
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let imm_ty = Expr::ty(expr).imm_ty();
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assert_eq!(Expr::ty(imm), imm_ty);
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let mut pos = COMMON_MOP_OTHER_WIDTH - 1;
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connect_any(
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expr.other,
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(imm[..pos], imm[imm_ty.width() - 1]).cast_to_bits(),
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);
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for i in SrcCount::VALUE..COMMON_MOP_SRC_REG_COUNT {
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connect_any(expr.src[i], imm[pos..pos + MOP_MIN_REG_WIDTH]);
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pos += MOP_MIN_REG_WIDTH;
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assert_eq!(Expr::ty(imm), Self::imm_ty());
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let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
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let mut src = [Some(0_hdl_u0.cast_to(reg_ty)); COMMON_MOP_SRC_LEN];
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for i in 0..SrcCount::VALUE {
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src[i] = None;
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}
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for (reversed_src_index, src_index) in Self::IMM_IN_SRC_RANGE.rev().enumerate() {
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src[src_index] = Some(imm_parts.reversed_src[reversed_src_index].cast_to(reg_ty));
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}
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for i in 0..COMMON_MOP_SRC_LEN {
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if let Some(v) = src[i] {
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connect(expr.src[i], v);
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}
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}
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}
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}
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@ -2,9 +2,9 @@
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// See Notices.txt for copyright information
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use crate::{
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config::CpuConfig,
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instruction::{MOp, UnitNum},
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instruction::MOp,
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unit::{TrapData, UnitTrait},
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util::tree_reduce::{tree_reduce, tree_reduce_with_state},
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util::tree_reduce::tree_reduce_with_state,
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};
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use fayalite::{module::instance_with_loc, prelude::*, util::ready_valid::ReadyValid};
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use std::num::NonZeroUsize;
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@ -124,5 +124,13 @@ pub fn reg_alloc(config: &CpuConfig) {
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);
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connect(unit_free_regs_tracker.cd, cd);
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// TODO: finish
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connect(
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unit_free_regs_tracker.free_in[0].data,
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HdlOption[UInt[config.out_reg_num_width]].uninit(), // FIXME: just for debugging
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);
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connect(
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unit_free_regs_tracker.alloc_out[0].ready,
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Bool.uninit(), // FIXME: just for debugging
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);
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}
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}
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@ -13,6 +13,8 @@ use fayalite::{
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util::ready_valid::ReadyValid,
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};
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pub mod alu_branch;
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macro_rules! all_units {
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(
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#[hdl_unit_kind = $HdlUnitKind:ident]
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@ -107,7 +109,7 @@ all_units! {
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#[unit_kind = UnitKind]
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#[hdl]
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pub enum UnitMOp<RegWidth: Size> {
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#[create_dyn_unit_fn = |config| todo!()]
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#[create_dyn_unit_fn = |config| alu_branch::AluBranch::new(config).to_dyn()]
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AluBranch(AluBranchMOp<RegWidth>),
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#[create_dyn_unit_fn = |config| todo!()]
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L2RegisterFile(L2RegisterFileMOp<RegWidth>),
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83
crates/cpu/src/unit/alu_branch.rs
Normal file
83
crates/cpu/src/unit/alu_branch.rs
Normal file
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@ -0,0 +1,83 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use crate::{
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config::CpuConfig,
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instruction::AluBranchMOp,
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unit::{DynUnit, DynUnitWrapper, UnitCancelInput, UnitKind, UnitOutput, UnitTrait},
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};
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use fayalite::{
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intern::{Intern, Interned},
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prelude::*,
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util::ready_valid::ReadyValid,
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};
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#[hdl_module]
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pub fn alu_branch(config: &CpuConfig) {
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#[hdl]
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let cd: ClockDomain = m.input();
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// TODO: finish
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
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pub struct AluBranch {
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config: Interned<CpuConfig>,
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module: Interned<Module<alu_branch>>,
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}
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impl AluBranch {
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pub fn new(config: &CpuConfig) -> Self {
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Self {
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config: config.intern(),
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module: alu_branch(config),
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}
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}
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}
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impl UnitTrait for AluBranch {
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type Type = alu_branch;
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type ExtraOut = ();
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type MOp = AluBranchMOp<DynSize>;
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fn ty(&self) -> Self::Type {
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self.module.io_ty()
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}
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fn extra_out_ty(&self) -> Self::ExtraOut {
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()
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}
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fn mop_ty(&self) -> Self::MOp {
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AluBranchMOp[self.config.p_reg_num().canonical().bit_width()]
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}
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fn unit_kind(&self) -> UnitKind {
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UnitKind::AluBranch
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}
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fn make_module(&self) -> Interned<Module<Self::Type>> {
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self.module
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}
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fn cancel_input(
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&self,
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this: Expr<Self::Type>,
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) -> Expr<ReadyValid<UnitCancelInput<DynSize, DynSize>>> {
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todo!()
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}
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fn output(
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&self,
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this: Expr<Self::Type>,
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) -> Expr<ReadyValid<UnitOutput<DynSize, DynSize, Self::ExtraOut>>> {
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todo!()
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}
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fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
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this.cd
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}
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fn to_dyn(&self) -> DynUnit {
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DynUnitWrapper(*self).to_dyn()
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}
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}
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880
crates/cpu/tests/expected/reg_alloc.vcd
Normal file
880
crates/cpu/tests/expected/reg_alloc.vcd
Normal file
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@ -0,0 +1,880 @@
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$timescale 1 ps $end
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$scope module reg_alloc $end
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$scope struct cd $end
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$var wire 1 ! clk $end
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$var wire 1 " rst $end
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$upscope $end
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$scope struct fetch_decode_interface $end
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$scope struct decoded_insns $end
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$scope struct [0] $end
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$scope struct data $end
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$var string 1 # \$tag $end
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$scope struct HdlSome $end
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$scope struct uop $end
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$var string 1 $ \$tag $end
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$scope struct AluBranch $end
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$var string 1 % \$tag $end
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$scope struct AddSub $end
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$scope struct alu_common $end
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$scope struct common $end
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$var string 0 & prefix_pad $end
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$var wire 8 ' dest $end
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$scope struct src $end
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$var wire 8 ( \[0] $end
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$var wire 8 ) \[1] $end
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$var wire 8 * \[2] $end
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$upscope $end
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$var wire 25 + imm_low $end
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$var wire 1 , imm_sign $end
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$scope struct _phantom $end
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$upscope $end
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$upscope $end
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$var string 1 - output_integer_mode $end
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$upscope $end
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$var wire 1 . invert_src0 $end
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$var wire 1 / invert_carry_in $end
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$var wire 1 0 invert_carry_out $end
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$var wire 1 1 add_pc $end
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$upscope $end
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$scope struct AddSubI $end
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$scope struct alu_common $end
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$scope struct common $end
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$var string 0 2 prefix_pad $end
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$var wire 8 3 dest $end
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$scope struct src $end
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$var wire 8 4 \[0] $end
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$var wire 8 5 \[1] $end
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$var wire 8 6 \[2] $end
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$upscope $end
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$var wire 25 7 imm_low $end
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$var wire 1 8 imm_sign $end
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$scope struct _phantom $end
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$upscope $end
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$upscope $end
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$var string 1 9 output_integer_mode $end
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$upscope $end
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$var wire 1 : invert_src0 $end
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$var wire 1 ; invert_carry_in $end
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$var wire 1 < invert_carry_out $end
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$var wire 1 = add_pc $end
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$upscope $end
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$scope struct Logical $end
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$scope struct alu_common $end
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$scope struct common $end
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$var string 0 > prefix_pad $end
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$var wire 8 ? dest $end
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$scope struct src $end
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$var wire 8 @ \[0] $end
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$var wire 8 A \[1] $end
|
||||
$var wire 8 B \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 C imm_low $end
|
||||
$var wire 1 D imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 E output_integer_mode $end
|
||||
$upscope $end
|
||||
$var wire 4 F lut $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct L2RegisterFile $end
|
||||
$var string 1 G \$tag $end
|
||||
$scope struct ReadL2Reg $end
|
||||
$scope struct common $end
|
||||
$var wire 1 H prefix_pad $end
|
||||
$var wire 8 I dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 J \[0] $end
|
||||
$var wire 8 K \[1] $end
|
||||
$var wire 8 L \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 M imm_low $end
|
||||
$var wire 1 N imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct WriteL2Reg $end
|
||||
$scope struct common $end
|
||||
$var wire 1 O prefix_pad $end
|
||||
$var wire 8 P dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 Q \[0] $end
|
||||
$var wire 8 R \[1] $end
|
||||
$var wire 8 S \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 T imm_low $end
|
||||
$var wire 1 U imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct LoadStore $end
|
||||
$var string 1 V \$tag $end
|
||||
$scope struct Load $end
|
||||
$var wire 1 W prefix_pad $end
|
||||
$var wire 8 X dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 Y \[0] $end
|
||||
$var wire 8 Z \[1] $end
|
||||
$var wire 8 [ \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 \ imm_low $end
|
||||
$var wire 1 ] imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct Store $end
|
||||
$var wire 1 ^ prefix_pad $end
|
||||
$var wire 8 _ dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 ` \[0] $end
|
||||
$var wire 8 a \[1] $end
|
||||
$var wire 8 b \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 c imm_low $end
|
||||
$var wire 1 d imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 1 e is_unrelated_pc $end
|
||||
$var wire 64 f pc $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 1 g ready $end
|
||||
$upscope $end
|
||||
$scope struct [1] $end
|
||||
$scope struct data $end
|
||||
$var string 1 h \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$scope struct uop $end
|
||||
$var string 1 i \$tag $end
|
||||
$scope struct AluBranch $end
|
||||
$var string 1 j \$tag $end
|
||||
$scope struct AddSub $end
|
||||
$scope struct alu_common $end
|
||||
$scope struct common $end
|
||||
$var string 0 k prefix_pad $end
|
||||
$var wire 8 l dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 m \[0] $end
|
||||
$var wire 8 n \[1] $end
|
||||
$var wire 8 o \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 p imm_low $end
|
||||
$var wire 1 q imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 r output_integer_mode $end
|
||||
$upscope $end
|
||||
$var wire 1 s invert_src0 $end
|
||||
$var wire 1 t invert_carry_in $end
|
||||
$var wire 1 u invert_carry_out $end
|
||||
$var wire 1 v add_pc $end
|
||||
$upscope $end
|
||||
$scope struct AddSubI $end
|
||||
$scope struct alu_common $end
|
||||
$scope struct common $end
|
||||
$var string 0 w prefix_pad $end
|
||||
$var wire 8 x dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 y \[0] $end
|
||||
$var wire 8 z \[1] $end
|
||||
$var wire 8 { \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 | imm_low $end
|
||||
$var wire 1 } imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ~ output_integer_mode $end
|
||||
$upscope $end
|
||||
$var wire 1 !" invert_src0 $end
|
||||
$var wire 1 "" invert_carry_in $end
|
||||
$var wire 1 #" invert_carry_out $end
|
||||
$var wire 1 $" add_pc $end
|
||||
$upscope $end
|
||||
$scope struct Logical $end
|
||||
$scope struct alu_common $end
|
||||
$scope struct common $end
|
||||
$var string 0 %" prefix_pad $end
|
||||
$var wire 8 &" dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 '" \[0] $end
|
||||
$var wire 8 (" \[1] $end
|
||||
$var wire 8 )" \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 *" imm_low $end
|
||||
$var wire 1 +" imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 ," output_integer_mode $end
|
||||
$upscope $end
|
||||
$var wire 4 -" lut $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct L2RegisterFile $end
|
||||
$var string 1 ." \$tag $end
|
||||
$scope struct ReadL2Reg $end
|
||||
$scope struct common $end
|
||||
$var wire 1 /" prefix_pad $end
|
||||
$var wire 8 0" dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 1" \[0] $end
|
||||
$var wire 8 2" \[1] $end
|
||||
$var wire 8 3" \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 4" imm_low $end
|
||||
$var wire 1 5" imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct WriteL2Reg $end
|
||||
$scope struct common $end
|
||||
$var wire 1 6" prefix_pad $end
|
||||
$var wire 8 7" dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 8" \[0] $end
|
||||
$var wire 8 9" \[1] $end
|
||||
$var wire 8 :" \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 ;" imm_low $end
|
||||
$var wire 1 <" imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct LoadStore $end
|
||||
$var string 1 =" \$tag $end
|
||||
$scope struct Load $end
|
||||
$var wire 1 >" prefix_pad $end
|
||||
$var wire 8 ?" dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 @" \[0] $end
|
||||
$var wire 8 A" \[1] $end
|
||||
$var wire 8 B" \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 C" imm_low $end
|
||||
$var wire 1 D" imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct Store $end
|
||||
$var wire 1 E" prefix_pad $end
|
||||
$var wire 8 F" dest $end
|
||||
$scope struct src $end
|
||||
$var wire 8 G" \[0] $end
|
||||
$var wire 8 H" \[1] $end
|
||||
$var wire 8 I" \[2] $end
|
||||
$upscope $end
|
||||
$var wire 25 J" imm_low $end
|
||||
$var wire 1 K" imm_sign $end
|
||||
$scope struct _phantom $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 1 L" is_unrelated_pc $end
|
||||
$var wire 64 M" pc $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 1 N" ready $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct fetch_decode_special_op $end
|
||||
$scope struct data $end
|
||||
$var string 1 O" \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var string 1 P" \$tag $end
|
||||
$scope struct Trap $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var wire 1 Q" ready $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct available_units $end
|
||||
$scope struct [0] $end
|
||||
$var wire 1 R" \[0] $end
|
||||
$upscope $end
|
||||
$scope struct [1] $end
|
||||
$var wire 1 S" \[0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct selected_unit_nums $end
|
||||
$scope struct [0] $end
|
||||
$var string 1 T" \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 1 U" value $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct [1] $end
|
||||
$var string 1 V" \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 1 W" value $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var string 1 X" unit_kind $end
|
||||
$scope struct available_units_for_kind $end
|
||||
$var wire 1 Y" \[0] $end
|
||||
$upscope $end
|
||||
$scope struct selected_unit_leaf $end
|
||||
$var string 1 Z" \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 1 [" value $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct unit_num $end
|
||||
$var wire 1 \" value $end
|
||||
$upscope $end
|
||||
$var string 1 ]" unit_kind $end
|
||||
$scope struct available_units_for_kind $end
|
||||
$var wire 1 ^" \[0] $end
|
||||
$upscope $end
|
||||
$scope struct selected_unit_leaf $end
|
||||
$var string 1 _" \$tag $end
|
||||
$scope struct HdlSome $end
|
||||
$var wire 1 `" value $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct unit_num $end
|
||||
$var wire 1 a" value $end
|
||||
$upscope $end
|
||||
$scope struct unit_0 $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 d" clk $end
|
||||
$var wire 1 e" rst $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module alu_branch $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 b" clk $end
|
||||
$var wire 1 c" rst $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct unit_0_free_regs_tracker $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 Q# clk $end
|
||||
$var wire 1 R# rst $end
|
||||
$upscope $end
|
||||
$scope struct free_in $end
|
||||
$scope struct [0] $end
|
||||
$scope struct data $end
|
||||
$var string 1 S# \$tag $end
|
||||
$var wire 4 T# HdlSome $end
|
||||
$upscope $end
|
||||
$var wire 1 U# ready $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct alloc_out $end
|
||||
$scope struct [0] $end
|
||||
$scope struct data $end
|
||||
$var string 1 V# \$tag $end
|
||||
$var wire 4 W# HdlSome $end
|
||||
$upscope $end
|
||||
$var wire 1 X# ready $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module unit_free_regs_tracker $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 f" clk $end
|
||||
$var wire 1 g" rst $end
|
||||
$upscope $end
|
||||
$scope struct free_in $end
|
||||
$scope struct [0] $end
|
||||
$scope struct data $end
|
||||
$var string 1 h" \$tag $end
|
||||
$var wire 4 i" HdlSome $end
|
||||
$upscope $end
|
||||
$var wire 1 j" ready $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct alloc_out $end
|
||||
$scope struct [0] $end
|
||||
$scope struct data $end
|
||||
$var string 1 k" \$tag $end
|
||||
$var wire 4 l" HdlSome $end
|
||||
$upscope $end
|
||||
$var wire 1 m" ready $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct allocated_reg $end
|
||||
$var reg 1 n" \[0] $end
|
||||
$var reg 1 o" \[1] $end
|
||||
$var reg 1 p" \[2] $end
|
||||
$var reg 1 q" \[3] $end
|
||||
$var reg 1 r" \[4] $end
|
||||
$var reg 1 s" \[5] $end
|
||||
$var reg 1 t" \[6] $end
|
||||
$var reg 1 u" \[7] $end
|
||||
$var reg 1 v" \[8] $end
|
||||
$var reg 1 w" \[9] $end
|
||||
$var reg 1 x" \[10] $end
|
||||
$var reg 1 y" \[11] $end
|
||||
$var reg 1 z" \[12] $end
|
||||
$var reg 1 {" \[13] $end
|
||||
$var reg 1 |" \[14] $end
|
||||
$var reg 1 }" \[15] $end
|
||||
$upscope $end
|
||||
$scope struct firing_data $end
|
||||
$var string 1 ~" \$tag $end
|
||||
$var wire 4 !# HdlSome $end
|
||||
$upscope $end
|
||||
$var wire 1 "# reduced_count_0_2 $end
|
||||
$var wire 1 ## reduced_count_overflowed_0_2 $end
|
||||
$scope struct reduced_alloc_nums_0_2 $end
|
||||
$var wire 1 $# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 %# reduced_count_2_4 $end
|
||||
$var wire 1 &# reduced_count_overflowed_2_4 $end
|
||||
$scope struct reduced_alloc_nums_2_4 $end
|
||||
$var wire 1 '# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 (# reduced_count_0_4 $end
|
||||
$var wire 1 )# reduced_count_overflowed_0_4 $end
|
||||
$scope struct reduced_alloc_nums_0_4 $end
|
||||
$var wire 2 *# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 +# reduced_count_4_6 $end
|
||||
$var wire 1 ,# reduced_count_overflowed_4_6 $end
|
||||
$scope struct reduced_alloc_nums_4_6 $end
|
||||
$var wire 1 -# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 .# reduced_count_6_8 $end
|
||||
$var wire 1 /# reduced_count_overflowed_6_8 $end
|
||||
$scope struct reduced_alloc_nums_6_8 $end
|
||||
$var wire 1 0# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 1# reduced_count_4_8 $end
|
||||
$var wire 1 2# reduced_count_overflowed_4_8 $end
|
||||
$scope struct reduced_alloc_nums_4_8 $end
|
||||
$var wire 2 3# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 4# reduced_count_0_8 $end
|
||||
$var wire 1 5# reduced_count_overflowed_0_8 $end
|
||||
$scope struct reduced_alloc_nums_0_8 $end
|
||||
$var wire 3 6# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 7# reduced_count_8_10 $end
|
||||
$var wire 1 8# reduced_count_overflowed_8_10 $end
|
||||
$scope struct reduced_alloc_nums_8_10 $end
|
||||
$var wire 1 9# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 :# reduced_count_10_12 $end
|
||||
$var wire 1 ;# reduced_count_overflowed_10_12 $end
|
||||
$scope struct reduced_alloc_nums_10_12 $end
|
||||
$var wire 1 <# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 =# reduced_count_8_12 $end
|
||||
$var wire 1 ># reduced_count_overflowed_8_12 $end
|
||||
$scope struct reduced_alloc_nums_8_12 $end
|
||||
$var wire 2 ?# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 @# reduced_count_12_14 $end
|
||||
$var wire 1 A# reduced_count_overflowed_12_14 $end
|
||||
$scope struct reduced_alloc_nums_12_14 $end
|
||||
$var wire 1 B# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 C# reduced_count_14_16 $end
|
||||
$var wire 1 D# reduced_count_overflowed_14_16 $end
|
||||
$scope struct reduced_alloc_nums_14_16 $end
|
||||
$var wire 1 E# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 F# reduced_count_12_16 $end
|
||||
$var wire 1 G# reduced_count_overflowed_12_16 $end
|
||||
$scope struct reduced_alloc_nums_12_16 $end
|
||||
$var wire 2 H# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 I# reduced_count_8_16 $end
|
||||
$var wire 1 J# reduced_count_overflowed_8_16 $end
|
||||
$scope struct reduced_alloc_nums_8_16 $end
|
||||
$var wire 3 K# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 L# reduced_count_0_16 $end
|
||||
$var wire 1 M# reduced_count_overflowed_0_16 $end
|
||||
$scope struct reduced_alloc_nums_0_16 $end
|
||||
$var wire 4 N# \[0] $end
|
||||
$upscope $end
|
||||
$scope struct firing_data $end
|
||||
$var string 1 O# \$tag $end
|
||||
$var wire 4 P# HdlSome $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
0!
|
||||
1"
|
||||
sHdlSome\x20(1) #
|
||||
sAluBranch\x20(0) $
|
||||
sAddSub\x20(0) %
|
||||
s0 &
|
||||
b1 '
|
||||
b10 (
|
||||
b11 )
|
||||
b100 *
|
||||
b1001000110100 +
|
||||
0,
|
||||
sFull64\x20(0) -
|
||||
1.
|
||||
1/
|
||||
10
|
||||
11
|
||||
s0 2
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||||
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||||
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||||
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|
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#10000000
|
||||
101
crates/cpu/tests/reg_alloc.rs
Normal file
101
crates/cpu/tests/reg_alloc.rs
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
// See Notices.txt for copyright information
|
||||
|
||||
use cpu::{
|
||||
config::CpuConfig,
|
||||
instruction::{
|
||||
AddSubMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOp, OutputIntegerMode,
|
||||
COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH,
|
||||
},
|
||||
reg_alloc::{reg_alloc, FetchedDecodedMOp},
|
||||
unit::UnitKind,
|
||||
};
|
||||
use fayalite::{
|
||||
prelude::*,
|
||||
sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
|
||||
util::RcWriter,
|
||||
};
|
||||
use std::num::NonZeroUsize;
|
||||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_reg_alloc() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let mut config = CpuConfig::new(vec![UnitKind::AluBranch]);
|
||||
config.fetch_width = NonZeroUsize::new(2).unwrap();
|
||||
let mut sim = Simulation::new(reg_alloc(&config));
|
||||
let mut writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
let fetch_decode_interface = sim.io().fetch_decode_interface;
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, true);
|
||||
sim.write_bool(fetch_decode_interface.fetch_decode_special_op.ready, true);
|
||||
sim.write(
|
||||
fetch_decode_interface.decoded_insns[0].data,
|
||||
HdlSome(
|
||||
#[hdl]
|
||||
FetchedDecodedMOp {
|
||||
uop: MOp.AluBranch(MOp.AluBranch.AddSub(
|
||||
#[hdl]
|
||||
AddSubMOp {
|
||||
alu_common: #[hdl]
|
||||
AluCommonMOp {
|
||||
common: CommonMOp::new(
|
||||
0_hdl_u0,
|
||||
1u8,
|
||||
[2u8, 3u8, 4u8],
|
||||
0x1234.cast_to(SInt[COMMON_MOP_3_IMM_WIDTH]),
|
||||
),
|
||||
output_integer_mode: OutputIntegerMode.Full64(),
|
||||
},
|
||||
invert_src0: true,
|
||||
invert_carry_in: true,
|
||||
invert_carry_out: true,
|
||||
add_pc: true,
|
||||
},
|
||||
)),
|
||||
is_unrelated_pc: true,
|
||||
pc: 0x1000_hdl_u64,
|
||||
},
|
||||
),
|
||||
);
|
||||
sim.write(
|
||||
fetch_decode_interface.decoded_insns[1].data,
|
||||
HdlSome(
|
||||
#[hdl]
|
||||
FetchedDecodedMOp {
|
||||
uop: MOp.AluBranch(MOp.AluBranch.Logical(
|
||||
#[hdl]
|
||||
LogicalMOp {
|
||||
alu_common: #[hdl]
|
||||
AluCommonMOp {
|
||||
common: CommonMOp::new(
|
||||
0_hdl_u0,
|
||||
2u8,
|
||||
[3u8, 4u8],
|
||||
SInt[COMMON_MOP_2_IMM_WIDTH].zero(),
|
||||
),
|
||||
output_integer_mode: OutputIntegerMode.Full64(),
|
||||
},
|
||||
lut: 0b0110_hdl_u4,
|
||||
},
|
||||
)),
|
||||
is_unrelated_pc: false,
|
||||
pc: 0x1004_hdl_u64,
|
||||
},
|
||||
),
|
||||
);
|
||||
for cycle in 0..10 {
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, true);
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, false);
|
||||
}
|
||||
// FIXME: vcd is just whatever reg_alloc does now, which isn't known to be correct
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/reg_alloc.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
|
|
@ -45,6 +45,9 @@ function main()
|
|||
*/LICENSE.md|*/Notices.txt)
|
||||
# copyright file
|
||||
;;
|
||||
/crates/cpu/tests/expected/*.vcd)
|
||||
# file that can't contain copyright header
|
||||
;;
|
||||
/.forgejo/workflows/*.yml|*/.gitignore|*.toml)
|
||||
check_file "$file" "${POUND_HEADER[@]}"
|
||||
;;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue