programmerjake/website
1
0
Fork 0
forked from libre-chip/website
Code Pull requests Activity

add Cesar as requested in https://forum.libre-chip.org/t/starting-working-on-a-nlnet-grant-proposal/29/4

Browse source
This commit is contained in:
Jacob Lifshay 2024-11-30 16:23:03 -08:00
parent 4af662dea8
commit 80c7463550
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 5 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/grants/nlnet-first.md
View file

@ -16,6 +16,11 @@ We are working towards building a high-performance superscalar CPU with speculat
* Jacob Lifshay -- Worked on designing PowerISA CPUs with Libre-SOC for 5yr, built a simple OoO Superscalar CPU simulator <https://salsa.debian.org/Kazan-team/power-cpu-sim>, built a RV32I CPU with VGA output in a few weeks that runs a 2.5D maze game <https://github.com/programmerjake/rv32>. Also is the main author of the [Fayalite](https://git.libre-chip.org/libre-chip/fayalite) HDL library * Jacob Lifshay -- Worked on designing PowerISA CPUs with Libre-SOC for 5yr, built a simple OoO Superscalar CPU simulator <https://salsa.debian.org/Kazan-team/power-cpu-sim>, built a RV32I CPU with VGA output in a few weeks that runs a 2.5D maze game <https://github.com/programmerjake/rv32>. Also is the main author of the [Fayalite](https://git.libre-chip.org/libre-chip/fayalite) HDL library
* Cesar Strauss - Contributed to the Libre-SOC project, mostly on digital
design and formal verification. Presented the talk "An introduction to
Formal Verification of Digital Circuits" on FOSDEM 2024
(<https://archive.fosdem.org/2024/schedule/event/fosdem-2024-2215-an-introduction-to-formal-verification-of-digital-circuits/>).
* Others... TODO * Others... TODO
# Requested support # Requested support