From 80c7463550aa660f95598563dc151de10ee0fb1d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sat, 30 Nov 2024 16:23:03 -0800 Subject: [PATCH] add Cesar as requested in https://forum.libre-chip.org/t/starting-working-on-a-nlnet-grant-proposal/29/4 --- src/grants/nlnet-first.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/grants/nlnet-first.md b/src/grants/nlnet-first.md index 6a94b9f..cacfb59 100644 --- a/src/grants/nlnet-first.md +++ b/src/grants/nlnet-first.md @@ -16,6 +16,11 @@ We are working towards building a high-performance superscalar CPU with speculat * Jacob Lifshay -- Worked on designing PowerISA CPUs with Libre-SOC for 5yr, built a simple OoO Superscalar CPU simulator , built a RV32I CPU with VGA output in a few weeks that runs a 2.5D maze game . Also is the main author of the [Fayalite](https://git.libre-chip.org/libre-chip/fayalite) HDL library +* Cesar Strauss - Contributed to the Libre-SOC project, mostly on digital +design and formal verification. Presented the talk "An introduction to +Formal Verification of Digital Circuits" on FOSDEM 2024 +(). + * Others... TODO # Requested support