12 commits

Author	SHA1	Message	Date
Jacob Lifshay	e4cf66adf8	sim: implement memories, still needs testing	2024-12-09 23:03:01 -08:00
Jacob Lifshay	259bee39c2	tests/sim: split expected output text into separate files	2024-12-05 18:17:13 -08:00
Jacob Lifshay	42afd2da0e	sim: implement enums (except for connecting unequal enum types)	2024-12-04 20:58:39 -08:00
Jacob Lifshay	fd45465d35	sim: add support for registers	2024-12-01 20:14:13 -08:00
Jacob Lifshay	5e0548db26	vcd: single bit signals have no spaces in their value changes	2024-12-01 20:12:43 -08:00
Jacob Lifshay	3abba7f9eb	simulating circuits with deduced resets works	2024-11-27 23:52:07 -08:00
Jacob Lifshay	11ddbc43c7	writing VCD for combinatorial circuits works!	2024-11-20 22:53:54 -08:00
Jacob Lifshay	c4b5d00419	WIP adding VCD output	2024-11-20 22:53:54 -08:00
Jacob Lifshay	09aa9fbc78	wire up simulator trace writing interface	2024-11-20 22:53:54 -08:00
Jacob Lifshay	288a6b71b9	WIP adding VCD output	2024-11-20 22:53:54 -08:00
Jacob Lifshay	0095570f19	simple combinatorial simulation works!	2024-11-20 22:53:54 -08:00
Jacob Lifshay	f54e55a143	Simulation::settle_step() works for simple modules	2024-11-20 22:53:54 -08:00