WIP linking next_pc stages together

Cargo.lock

@@ -210,6 +210,8 @@ name = "cpu"
 version = "0.1.0"
 dependencies = [
  "fayalite",
+ "serde",
+ "simple-mermaid",
 ]
 
 [[package]]
@@ -303,7 +305,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
 [[package]]
 name = "fayalite"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f"
 dependencies = [
  "base64",
  "bitvec",
@@ -330,7 +332,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
@@ -338,7 +340,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros-impl"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -353,7 +355,7 @@ dependencies = [
 [[package]]
 name = "fayalite-visit-gen"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f"
 dependencies = [
  "indexmap",
  "prettyplease",
@@ -689,6 +691,12 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
 
+[[package]]
+name = "simple-mermaid"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "589144a964b4b30fe3a83b4bb1a09e2475aac194ec832a046a23e75bddf9eb29"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"

Cargo.toml

@@ -15,6 +15,8 @@ rust-version = "1.89.0"
 
 [workspace.dependencies]
 fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" }
+serde = { version = "1.0.202", features = ["derive"] }
+simple-mermaid = "0.2.0"
 
 [profile.dev]
 opt-level = 1

crates/cpu/Cargo.toml

@@ -16,3 +16,5 @@ version.workspace = true
 
 [dependencies]
 fayalite.workspace = true
+serde.workspace = true
+simple-mermaid.workspace = true

crates/cpu/src/config.rs

@@ -8,9 +8,10 @@ use crate::{
     },
 };
 use fayalite::prelude::*;
+use serde::{Deserialize, Serialize};
 use std::num::NonZeroUsize;
 
-#[derive(Clone, Eq, PartialEq, Hash, Debug)]
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
 #[non_exhaustive]
 pub struct UnitConfig {
     pub kind: UnitKind,
@@ -27,12 +28,15 @@ impl UnitConfig {
     }
 }
 
-#[derive(Clone, Eq, PartialEq, Hash, Debug)]
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
 #[non_exhaustive]
 pub struct CpuConfig {
     pub units: Vec<UnitConfig>,
     pub out_reg_num_width: usize,
     pub fetch_width: NonZeroUsize,
+    pub max_branches_per_fetch: NonZeroUsize,
+    pub max_fetches_in_flight: NonZeroUsize,
+    pub log2_fetch_width_in_bytes: u8,
     /// default value for [`UnitConfig::max_in_flight`]
     pub default_unit_max_in_flight: NonZeroUsize,
     pub rob_size: NonZeroUsize,
@@ -46,6 +50,19 @@ impl CpuConfig {
         };
         v
     };
+    pub const DEFAULT_MAX_BRANCHES_PER_FETCH: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(1) else {
+            unreachable!();
+        };
+        v
+    };
+    pub const DEFAULT_MAX_FETCHES_IN_FLIGHT: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(16) else {
+            unreachable!();
+        };
+        v
+    };
+    pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3;
     pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = {
         let Some(v) = NonZeroUsize::new(8) else {
             unreachable!();
@@ -57,6 +74,9 @@ impl CpuConfig {
             units,
             out_reg_num_width: Self::DEFAULT_OUT_REG_NUM_WIDTH,
             fetch_width: Self::DEFAULT_FETCH_WIDTH,
+            max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH,
+            max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT,
+            log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES,
             default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT,
             rob_size,
         }
@@ -116,4 +136,27 @@ impl CpuConfig {
         UnitToRegAlloc[mop_ty][extra_out_ty][self.unit_num_width()][self.out_reg_num_width]
             [self.non_const_unit_nums().len()]
     }
+    pub fn fetch_width_in_bytes(&self) -> usize {
+        1usize
+            .checked_shl(self.log2_fetch_width_in_bytes.into())
+            .expect("log2_fetch_width_in_bytes is too big")
+    }
 }
+
+#[hdl(get(|c| c.fetch_width.get()))]
+pub type CpuConfigFetchWidth<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetch_width.get() * 2))]
+pub type TwiceCpuConfigFetchWidth<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.max_branches_per_fetch.get()))]
+pub type CpuConfigMaxBranchesPerFetch<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.max_fetches_in_flight.get()))]
+pub type CpuConfigMaxFetchesInFlight<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_fetch_width_in_bytes.into()))]
+pub type CpuConfigLog2FetchWidthInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetch_width_in_bytes()))]
+pub type CpuConfigFetchWidthInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;

crates/cpu/src/instruction.rs

@@ -2,12 +2,11 @@
 // See Notices.txt for copyright information
 use crate::{unit::UnitMOp, util::range_u32_len};
 use fayalite::{
-    expr::ops::{ArrayLiteral, ExprPartialEq},
+    expr::{HdlPartialEqImpl, ops::ArrayLiteral},
     intern::Interned,
     prelude::*,
-    sim::value::SimValuePartialEq,
 };
-use std::{fmt, marker::PhantomData, ops::Range};
+use std::{borrow::Cow, fmt, marker::PhantomData, ops::Range};
 
 pub mod power_isa;
 
@@ -172,20 +171,38 @@ pub enum OutputIntegerMode {
     SignExt8,
 }
 
-impl ExprPartialEq<Self> for OutputIntegerMode {
-    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+impl HdlPartialEqImpl<Self> for OutputIntegerMode {
+    #[track_caller]
+    fn cmp_value_eq(
+        lhs: Self,
+        lhs_value: Cow<'_, Self::SimValue>,
+        rhs: Self,
+        rhs_value: Cow<'_, Self::SimValue>,
+    ) -> bool {
+        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
+            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_eq(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_ne(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
         lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
     }
-
-    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
-    }
-}
-
-impl SimValuePartialEq<Self> for OutputIntegerMode {
-    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
-        SimValue::opaque(this) == SimValue::opaque(other)
-    }
 }
 
 pub const MOP_IMM_WIDTH: usize = 34;
@@ -296,8 +313,8 @@ impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize
         let dest = dest.to_expr();
         let src_in = src.to_expr();
         let imm = imm.to_expr();
-        assert_eq!(Expr::ty(imm), Self::imm_ty());
-        let src_reg_ty = Expr::ty(src_in).element();
+        assert_eq!(imm.ty(), Self::imm_ty());
+        let src_reg_ty = src_in.ty().element();
         let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
         let mut src = [0_hdl_u0.cast_to(src_reg_ty); COMMON_MOP_SRC_LEN];
         for i in 0..SrcCount::VALUE {
@@ -341,9 +358,9 @@ impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize
     #[hdl]
     pub fn connect_to_imm(expr: impl ToExpr<Type = Self>, imm: impl ToExpr<Type = SInt>) {
         let expr = expr.to_expr();
-        let src_reg_ty = Expr::ty(expr).src.element();
+        let src_reg_ty = expr.ty().src.element();
         let imm = imm.to_expr();
-        assert_eq!(Expr::ty(imm), Self::imm_ty());
+        assert_eq!(imm.ty(), Self::imm_ty());
         let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
         let mut src = [Some(0_hdl_u0.cast_to(src_reg_ty)); COMMON_MOP_SRC_LEN];
         for i in 0..SrcCount::VALUE {
@@ -496,7 +513,7 @@ macro_rules! mop_enum {
             fn dest_reg(input: impl ToExpr<Type = Self>) -> Expr<Self::DestReg> {
                 let input = input.to_expr();
                 #[hdl]
-                let dest_reg = wire(Expr::ty(input).dest_reg_ty());
+                let dest_reg = wire(input.ty().dest_reg_ty());
                 #[hdl]
                 match input {
                     Self::$FirstVariant(v) => connect(dest_reg, <$first_ty as MOpTrait>::dest_reg(v)),
@@ -537,7 +554,7 @@ macro_rules! mop_enum {
             ) -> Expr<Self::Mapped<NewDestReg, NewSrcRegWidth>> {
                 let input = input.to_expr();
                 let new_dest = new_dest.to_expr();
-                let mapped_ty = Expr::ty(input).mapped_ty(Expr::ty(new_dest), new_src_reg_width);
+                let mapped_ty = input.ty().mapped_ty(new_dest.ty(), new_src_reg_width);
                 #[hdl]
                 let mapped_regs = wire(mapped_ty);
                 #[hdl]
@@ -584,7 +601,7 @@ macro_rules! mop_enum {
                 MOpInto::mop_into_ty($MOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]$([$sizes_get_size(self)])*)
             }
             fn mop_into(this: Expr<Self>) -> Expr<Target> {
-                MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>>::mop_into_ty(Expr::ty(this)).$Variant(this))
+                MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>>::mop_into_ty(this.ty()).$Variant(this))
             }
         }
     };
@@ -833,22 +850,19 @@ impl<Width: Size> UnitNum<Width> {
     }
     pub fn is_index(expr: impl ToExpr<Type = Self>, index: usize) -> Expr<Bool> {
         let expr = expr.to_expr();
-        Expr::ty(expr)
-            .from_index(index)
-            .adj_value
-            .cmp_eq(expr.adj_value)
+        expr.ty().from_index(index).adj_value.cmp_eq(expr.adj_value)
     }
     #[hdl]
     pub fn as_index(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<UIntType<Width>>> {
         let expr = expr.to_expr();
         #[hdl]
-        let unit_index = wire(HdlOption[Expr::ty(expr).adj_value]);
-        connect(unit_index, Expr::ty(unit_index).HdlNone());
+        let unit_index = wire(HdlOption[expr.ty().adj_value]);
+        connect(unit_index, unit_index.ty().HdlNone());
         #[hdl]
         if expr.adj_value.cmp_ne(0u8) {
             connect(
                 unit_index,
-                HdlSome((expr.adj_value - 1u8).cast_to(Expr::ty(expr).adj_value)),
+                HdlSome((expr.adj_value - 1u8).cast_to(expr.ty().adj_value)),
             );
         }
         unit_index
@@ -900,7 +914,7 @@ impl MOpRegNum {
     pub fn const_zero() -> Expr<Self> {
         #[hdl]
         MOpRegNum {
-            value: Self::CONST_ZERO_REG_NUM.cast_to_static(),
+            value: Self::CONST_ZERO_REG_NUM.cast_to_static::<UInt<_>>(),
         }
     }
     /// a lot of instructions write to flag registers that we want
@@ -1077,7 +1091,7 @@ impl MOpDestReg {
                         flag_reg,
                         #[hdl]
                         MOpRegNum {
-                            value: reg_num.cast_to_static(),
+                            value: reg_num.cast_to_static::<UInt<_>>(),
                         },
                     );
                 }

crates/cpu/src/lib.rs

@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 pub mod config;
 pub mod instruction;
+pub mod next_pc;
 pub mod reg_alloc;
 pub mod register;
 pub mod unit;

crates/cpu/src/next_pc/next_pc.mermaid

@@ -0,0 +1,25 @@
+stateDiagram-v2
+    direction LR
+
+    state "Next PC" as next_pc
+    [*] --> next_pc
+
+    state "Fetch/Decode" as fetch_decode
+    next_pc --> fetch_decode
+
+    state "Branch Predictor" as br_pred
+    next_pc --> br_pred
+    br_pred --> next_pc: cancel following
+
+    state "Post-decode" as post_decode
+    fetch_decode --> post_decode
+    br_pred --> post_decode
+    post_decode --> next_pc: cancel following
+
+    state "Rename\nDispatch\nExecute" as execute
+    post_decode --> execute
+
+    state "Retire" as retire
+    execute --> retire
+    retire --> [*]
+    retire --> next_pc: cancel following

crates/cpu/src/reg_alloc.rs

@@ -241,7 +241,7 @@ pub fn reg_alloc(config: &CpuConfig) {
         // TODO: finish
         connect(
             rob.renamed_insns_in[fetch_index].data,
-            Expr::ty(rob).renamed_insns_in.element().data.HdlNone(),
+            rob.ty().renamed_insns_in.element().data.HdlNone(),
         );
         // TODO: finish
         connect(
@@ -263,7 +263,7 @@ pub fn reg_alloc(config: &CpuConfig) {
         );
         connect(
             renamed_mops[fetch_index],
-            Expr::ty(renamed_mops).element().HdlNone(),
+            renamed_mops.ty().element().HdlNone(),
         );
         #[hdl]
         struct RenameTableReadPort<T> {
@@ -332,7 +332,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                 let write_port = wire_with_loc(
                     &format!("{table_name}_{fetch_index}_{}", reg_kind.reg_name()),
                     SourceLocation::caller(),
-                    Expr::ty(write_port_),
+                    write_port_.ty(),
                 );
                 connect(write_port_, write_port);
                 write_ports.push_back(write_port);
@@ -343,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                         addr: 0_hdl_u0,
                         en: false,
                         clk: cd.clk,
-                        data: Expr::ty(write_port.data).uninit(),
+                        data: write_port.data.ty().uninit(),
                         mask: splat_mask(config.p_reg_num(), true.to_expr()),
                     },
                 );
@@ -375,7 +375,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                     config.renamed_mop_in_unit().TransformedMove,
                     |renamed_mop, renamed_move_op: Expr<MoveRegMOp<_, _>>| {
                         // TODO: finish handling MoveRegMOp
-                        connect(renamed_mop, Expr::ty(renamed_mop).HdlNone());
+                        connect(renamed_mop, renamed_mop.ty().HdlNone());
                     },
                 );
                 connect(
@@ -429,7 +429,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                     );
                     connect(
                         selected_unit_index_leaf,
-                        Expr::ty(selected_unit_index_leaf).HdlNone(),
+                        selected_unit_index_leaf.ty().HdlNone(),
                     );
                     let unit_index_wire = wire_with_loc(
                         &format!("unit_index_{fetch_index}_{unit_index}"),
@@ -447,7 +447,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                     let selected_unit_index_node = wire_with_loc(
                         &format!("selected_unit_index_node_{fetch_index}_{state}"),
                         SourceLocation::caller(),
-                        Expr::ty(l),
+                        l.ty(),
                     );
                     *state += 1;
                     connect(selected_unit_index_node, l);
@@ -516,7 +516,7 @@ pub fn reg_alloc(config: &CpuConfig) {
         connect(unit_free_regs_tracker.alloc_out[0].ready, false);
         connect(
             unit_to_reg_alloc.input.data,
-            Expr::ty(unit_to_reg_alloc.input).data.HdlNone(),
+            unit_to_reg_alloc.input.ty().data.HdlNone(),
         );
         for fetch_index in 0..config.fetch_width.get() {
             #[hdl]
@@ -550,7 +550,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                     } else {
                         connect(
                             unit_to_reg_alloc.input.data,
-                            HdlSome(Expr::ty(unit_to_reg_alloc.input).data.HdlSome.uninit()),
+                            HdlSome(unit_to_reg_alloc.input.ty().data.HdlSome.uninit()),
                         );
                         // FIXME: add hdl_assert(cd.clk, false.to_expr(), "");
                     }
@@ -578,7 +578,8 @@ pub fn reg_alloc(config: &CpuConfig) {
         connect(unit_to_reg_alloc.unit_forwarding_info, unit_forwarding_info);
         connect(
             unit_forwarding_info.unit_output_writes[unit_index],
-            Expr::ty(unit_forwarding_info)
+            unit_forwarding_info
+                .ty()
                 .unit_output_writes
                 .element()
                 .HdlNone(),

crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs

@@ -73,7 +73,7 @@ pub fn unit_free_regs_tracker(
             let reduced_alloc_nums = wire_with_loc(
                 &format!("reduced_alloc_nums_{}_{}", range.start, range.end),
                 SourceLocation::caller(),
-                Array[UInt[Expr::ty(l.alloc_nums).element().width() + 1]][alloc_at_once.get()],
+                Array[UInt[l.alloc_nums.ty().element().width() + 1]][alloc_at_once.get()],
             );
             for alloc_index in 0..alloc_at_once.get() {
                 #[hdl]
@@ -195,7 +195,7 @@ mod tests {
                 }
             }
             #[hdl]
-            let free_before_alloc_array = wire(Array[Expr::ty(free_reg)][alloc_at_once.get() + 1]);
+            let free_before_alloc_array = wire(Array[free_reg.ty()][alloc_at_once.get() + 1]);
             connect(free_before_alloc_array[0], free_reg);
             #[hdl]
             let expected_alloc = wire(Array[HdlOption[reg_num_ty]][alloc_at_once.get()]);

crates/cpu/src/unit.rs

@@ -15,6 +15,7 @@ use fayalite::{
     intern::{Intern, Interned},
     prelude::*,
 };
+use serde::{Deserialize, Serialize};
 
 pub mod alu_branch;
 pub mod unit_base;
@@ -36,7 +37,7 @@ macro_rules! all_units {
         }
     ) => {
         $(#[$enum_meta])*
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug, Serialize, Deserialize)]
         $vis enum $UnitKind {
             $(
                 $(#[$variant_meta])*
@@ -52,9 +53,16 @@ macro_rules! all_units {
             }
         }
 
-        impl ToExpr for $UnitKind {
+        impl ValueType for $UnitKind {
             type Type = $HdlUnitKind;
+            type ValueCategory = fayalite::expr::value_category::ValueCategoryExpr;
 
+            fn ty(&self) -> Self::Type {
+                $HdlUnitKind
+            }
+        }
+
+        impl ToExpr for $UnitKind {
             fn to_expr(&self) -> Expr<Self::Type> {
                 match self {
                     $($UnitKind::$Unit => $HdlUnitKind.$Unit(),)*
@@ -98,7 +106,7 @@ macro_rules! all_units {
                 #[hdl]
                 $vis fn $extract(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<$Op>> {
                     let expr = expr.to_expr();
-                    let ty = Expr::ty(expr);
+                    let ty = expr.ty();
                     #[hdl]
                     let $extract = wire(HdlOption[ty.$Unit]);
                     connect($extract, HdlOption[ty.$Unit].HdlNone());
@@ -164,10 +172,10 @@ macro_rules! all_units {
                 $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
             {
                 let this = this.to_expr();
-                let new_ty = Expr::ty(this).with_transformed_move_op_ty(new_transformed_move_op_ty);
+                let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty);
                 #[hdl]
                 let with_transformed_move_op = wire(HdlOption[new_ty]);
-                connect(with_transformed_move_op, Expr::ty(with_transformed_move_op).HdlNone());
+                connect(with_transformed_move_op, with_transformed_move_op.ty().HdlNone());
                 // workaround #[hdl] match expanding to a loop, so you can't move variables in it
                 let mut connect_transformed_move_op = Some(connect_transformed_move_op);
                 #[hdl]
@@ -209,7 +217,7 @@ macro_rules! all_units {
                 RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
             }
             fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
-                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$BeforeUnit(this)
+                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$BeforeUnit(this)
             }
         })*
 
@@ -218,7 +226,7 @@ macro_rules! all_units {
                 RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
             }
             fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
-                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$AfterUnit(this)
+                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$AfterUnit(this)
             }
         })*
     };

crates/cpu/src/unit/alu_branch.rs

@@ -266,16 +266,13 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
     let unit_base = instance(unit_base(
         config,
         unit_index,
-        Expr::ty(unit_to_reg_alloc).input.data.HdlSome.mop,
+        unit_to_reg_alloc.ty().input.data.HdlSome.mop,
         (),
     ));
     connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc);
     connect(unit_base.cd, cd);
     connect(unit_base.execute_start.ready, true);
-    connect(
-        unit_base.execute_end,
-        Expr::ty(unit_base.execute_end).HdlNone(),
-    );
+    connect(unit_base.execute_end, unit_base.execute_end.ty().HdlNone());
     #[hdl]
     if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) {
         #[hdl]

crates/cpu/src/unit/unit_base.rs

@@ -227,7 +227,7 @@ impl InFlightOpsSummary<DynSize> {
         in_flight_ops: impl ToExpr<Type = ArrayType<HdlOption<InFlightOp<MOp>>, MaxInFlight>>,
     ) -> Expr<Self> {
         let in_flight_ops = in_flight_ops.to_expr();
-        let max_in_flight = Expr::ty(in_flight_ops).len();
+        let max_in_flight = in_flight_ops.ty().len();
         let index_range = 0..max_in_flight;
         let index_ty = UInt::range(index_range.clone());
         tree_reduce(
@@ -259,7 +259,7 @@ pub fn unit_base<
     let execute_end: HdlOption<ExecuteEnd<DynSize, ExtraOut>> =
         m.input(HdlOption[ExecuteEnd[config.out_reg_num_width][extra_out_ty]]);
 
-    connect(execute_start.data, Expr::ty(execute_start).data.HdlNone());
+    connect(execute_start.data, execute_start.ty().data.HdlNone());
 
     let max_in_flight = config.unit_max_in_flight(unit_index).get();
     let in_flight_op_ty = InFlightOp[mop_ty];
@@ -270,7 +270,7 @@ pub fn unit_base<
 
     let in_flight_ops_summary_value = InFlightOpsSummary::summarize(in_flight_ops);
     #[hdl]
-    let in_flight_ops_summary = wire(Expr::ty(in_flight_ops_summary_value));
+    let in_flight_ops_summary = wire(in_flight_ops_summary_value.ty());
     connect(in_flight_ops_summary, in_flight_ops_summary_value);
 
     connect(
@@ -302,7 +302,7 @@ pub fn unit_base<
     #[hdl]
     let input_src_regs_valid = wire();
     connect(input_src_regs_valid, [true; COMMON_MOP_SRC_LEN]);
-    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..Expr::ty(unit_output_writes).len())
+    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..unit_output_writes.ty().len())
         .map(|unit_index| {
             let mut mem = memory_with_loc(
                 &format!("unit_{unit_index}_output_regs_valid"),
@@ -313,7 +313,7 @@ pub fn unit_base<
             mem
         })
         .collect();
-    for unit_index in 0..Expr::ty(unit_output_writes).len() {
+    for unit_index in 0..unit_output_writes.ty().len() {
         let mut unit_output_regs = memory_with_loc(
             &format!("unit_{unit_index}_output_regs"),
             PRegValue,
@@ -411,7 +411,7 @@ pub fn unit_base<
 
     connect(
         unit_to_reg_alloc.output,
-        Expr::ty(unit_to_reg_alloc.output).HdlNone(),
+        unit_to_reg_alloc.output.ty().HdlNone(),
     );
 
     #[hdl]
@@ -503,7 +503,7 @@ pub fn unit_base<
 
             #[hdl]
             if in_flight_ops_summary.ready_op_index.cmp_eq(HdlSome(
-                in_flight_op_index.cast_to(Expr::ty(in_flight_ops_summary).ready_op_index.HdlSome),
+                in_flight_op_index.cast_to(in_flight_ops_summary.ty().ready_op_index.HdlSome),
             )) {
                 connect(read_src_regs, src_regs);
             }
@@ -512,7 +512,7 @@ pub fn unit_base<
                 in_flight_op_next_src_ready_flags[in_flight_op_index],
                 src_ready_flags,
             );
-            for unit_index in 0..Expr::ty(unit_output_writes).len() {
+            for unit_index in 0..unit_output_writes.ty().len() {
                 #[hdl]
                 if let HdlSome(unit_output_write) = unit_output_writes[unit_index] {
                     #[hdl]

crates/cpu/src/util/array_vec.rs

@@ -22,6 +22,30 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
             len: 0u8.cast_to(self.len),
         }
     }
+    #[hdl]
+    pub fn new_sim(self, uninit_element: impl ToSimValueWithType<T>) -> SimValue<Self> {
+        let uninit_element = uninit_element.into_sim_value_with_type(self.element());
+        #[hdl(sim)]
+        ArrayVec::<_, _> {
+            elements: SimValue::from_array_elements(
+                self.elements,
+                (0..self.elements.len()).map(|_| uninit_element.clone()),
+            ),
+            len: 0u8.cast_to(self.len),
+        }
+    }
+    #[hdl]
+    pub fn new_full_sim(
+        self,
+        elements: impl ToSimValueWithType<ArrayType<T, N>>,
+    ) -> SimValue<Self> {
+        let elements = elements.to_sim_value_with_type(self.elements);
+        #[hdl(sim)]
+        Self {
+            elements,
+            len: self.elements.len().to_sim_value_with_type(self.len),
+        }
+    }
     pub fn element(self) -> T {
         self.elements.element()
     }
@@ -39,8 +63,8 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
         let elements = elements.to_expr();
         let len = len.to_expr();
         assert_eq!(
-            Length[N::from_usize(Expr::ty(elements).len())],
-            Expr::ty(len),
+            Length[N::from_usize(elements.ty().len())],
+            len.ty(),
             "len type mismatch",
         );
         #[hdl]
@@ -52,6 +76,9 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
     pub fn len(this: impl ToExpr<Type = Self>) -> Expr<Length<N>> {
         this.to_expr().len
     }
+    pub fn len_sim(this: &SimValue<Self>) -> &SimValue<Length<N>> {
+        &this.len
+    }
     pub fn is_empty(this: impl ToExpr<Type = Self>) -> Expr<Bool> {
         let len = Self::len(this);
         len.cmp_eq(0u8)
@@ -75,6 +102,72 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
             }
         }
     }
+    pub fn elements_sim_ref(this: &SimValue<Self>) -> &[SimValue<T>] {
+        &this.elements[..*this.len]
+    }
+    pub fn elements_sim_mut(this: &mut SimValue<Self>) -> &mut [SimValue<T>] {
+        let len = *this.len;
+        &mut this.elements[..len]
+    }
+    #[hdl]
+    pub async fn async_for_each_sim(
+        this: impl ToSimValue<Type = Self>,
+        mut f: impl AsyncFnMut(usize, SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this.into_sim_value();
+        for (index, element) in elements.into_iter().enumerate() {
+            if index.cmp_lt(*len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub async fn async_for_each_sim_ref<'a>(
+        this: &'a SimValue<Self>,
+        mut f: impl AsyncFnMut(usize, &'a SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        for (index, element) in elements.iter().enumerate() {
+            if index.cmp_lt(**len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub async fn async_for_each_sim_mut<'a>(
+        this: &'a mut SimValue<Self>,
+        mut f: impl AsyncFnMut(usize, &'a mut SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        for (index, element) in elements.iter_mut().enumerate() {
+            if index.cmp_lt(**len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub fn try_push_sim(
+        this: &mut SimValue<Self>,
+        value: impl ToSimValueWithType<T>,
+    ) -> Result<(), SimValue<T>> {
+        let value = value.into_sim_value_with_type(this.ty().element());
+        let capacity = this.ty().capacity();
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        if **len < capacity {
+            elements[**len] = value;
+            **len += 1;
+            Ok(())
+        } else {
+            Err(value)
+        }
+    }
+    pub fn truncate_sim(this: &mut SimValue<Self>, len: usize) {
+        *this.len = len.min(*this.len);
+    }
     pub fn mapped_ty<U: Type>(self, new_element_ty: U) -> ArrayVec<U, N> {
         ArrayVec {
             elements: ArrayType[new_element_ty][N::from_usize(self.elements.len())],
@@ -89,7 +182,7 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
     ) -> Expr<ArrayVec<U, N>> {
         let this = this.to_expr();
         #[hdl]
-        let mapped_array_vec = wire(Expr::ty(this).mapped_ty(new_element_ty));
+        let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty));
         connect(mapped_array_vec.len, this.len);
         Self::for_each(this, |index, element| {
             connect(mapped_array_vec[index], f(index, element));
@@ -100,12 +193,10 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
     pub fn as_array_of_options(this: impl ToExpr<Type = Self>) -> Expr<ArrayType<HdlOption<T>, N>> {
         let this = this.to_expr();
         #[hdl]
-        let array_vec_as_array_of_options = wire(
-            ArrayType[HdlOption[Expr::ty(this).element()]]
-                [N::from_usize(Expr::ty(this).capacity())],
-        );
+        let array_vec_as_array_of_options =
+            wire(ArrayType[HdlOption[this.ty().element()]][N::from_usize(this.ty().capacity())]);
         for element in array_vec_as_array_of_options {
-            connect(element, Expr::ty(element).HdlNone());
+            connect(element, element.ty().HdlNone());
         }
         Self::for_each(this, |index, element| {
             connect(array_vec_as_array_of_options[index], HdlSome(element))

crates/cpu/tests/next_pc.rs

@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use cpu::{
+    config::{CpuConfig, UnitConfig},
+    next_pc::{
+        DecodeToPostDecodeInterface, DecodeToPostDecodeInterfaceInner, FETCH_BLOCK_ID_WIDTH,
+        NextPcToFetchInterface, NextPcToFetchInterfaceInner, WipDecodedInsn, WipDecodedInsnKind,
+        next_pc,
+    },
+    unit::UnitKind,
+    util::array_vec::ArrayVec,
+};
+use fayalite::{prelude::*, sim::vcd::VcdWriterDecls, util::RcWriter};
+use std::{
+    cell::Cell,
+    collections::{BTreeMap, VecDeque},
+    num::NonZeroUsize,
+};
+
+#[derive(Copy, Clone, Debug)]
+enum MockInsn {
+    Nop4,
+    Jump { target: u64 },
+    CondBranch { target: u64 },
+    Call { target: u64 },
+    Ret,
+}
+
+impl MockInsn {
+    fn byte_len(self) -> u64 {
+        match self {
+            MockInsn::Nop4 => 4,
+            MockInsn::Jump { .. } => 4,
+            MockInsn::CondBranch { .. } => 4,
+            MockInsn::Call { .. } => 4,
+            MockInsn::Ret => 4,
+        }
+    }
+}
+
+#[derive(Debug)]
+struct MockInsns {
+    insns: BTreeMap<u64, MockInsn>,
+}
+
+impl MockInsns {
+    fn new() -> Self {
+        Self {
+            insns: BTreeMap::from_iter([
+                (0x0, MockInsn::Nop4),
+                (0x4, MockInsn::Nop4),
+                (0x8, MockInsn::CondBranch { target: 0x4 }),
+                (0xC, MockInsn::Call { target: 0x18 }),
+                (0x10, MockInsn::Jump { target: 0x10 }),
+                (0x14, MockInsn::Jump { target: 0x10 }),
+                (0x18, MockInsn::Jump { target: 0x1C }),
+                (0x1C, MockInsn::Ret),
+            ]),
+        }
+    }
+    fn fetch_block(&self, pc_range: std::ops::Range<u64>) -> impl Iterator<Item = (u64, MockInsn)> {
+        self.insns
+            .range(pc_range.clone())
+            .filter_map(move |(&pc, &insn)| {
+                if pc_range.end >= pc + insn.byte_len() {
+                    Some((pc, insn))
+                } else {
+                    None
+                }
+            })
+    }
+}
+
+const FETCH_PIPE_QUEUE_SIZE: usize = 5;
+
+const DEMO_ILLEGAL_INSN_TRAP: u64 = 0xFF000000u64;
+
+#[hdl]
+struct FetchPipeQueueEntry {
+    fetch_pc: UInt<64>,
+    cycles_left: UInt<8>,
+    fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>,
+}
+
+impl FetchPipeQueueEntry {
+    #[hdl]
+    fn default_sim(self) -> SimValue<Self> {
+        #[hdl(sim)]
+        FetchPipeQueueEntry {
+            fetch_pc: 0u64,
+            cycles_left: 0u8,
+            fetch_block_id: 0u8,
+        }
+    }
+    fn get_next_delay(delay_sequence_index: &Cell<u64>) -> u8 {
+        let index = delay_sequence_index.get();
+        delay_sequence_index.set(delay_sequence_index.get().wrapping_add(1));
+        // make a pseudo-random number deterministically based on index
+        let random = index
+            .wrapping_add(1)
+            .wrapping_mul(0x18C49126EABE7A0D) // random prime
+            .rotate_left(32)
+            .wrapping_mul(0x92B38C197608A6B) // random prime
+            .rotate_right(60);
+        (random % 8) as u8
+    }
+}
+
+#[hdl_module(extern)]
+fn mock_fetch_pipe(config: PhantomConst<CpuConfig>) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let from_fetch: NextPcToFetchInterface<PhantomConst<CpuConfig>> =
+        m.input(NextPcToFetchInterface[config]);
+    #[hdl]
+    let to_post_decode: DecodeToPostDecodeInterface<PhantomConst<CpuConfig>> =
+        m.output(DecodeToPostDecodeInterface[config]);
+    #[hdl]
+    let queue_debug: ArrayVec<FetchPipeQueueEntry, ConstUsize<{ FETCH_PIPE_QUEUE_SIZE }>> =
+        m.output();
+    m.register_clock_for_past(cd.clk);
+    m.extern_module_simulation_fn(
+        (cd, from_fetch, to_post_decode, queue_debug),
+        |(cd, from_fetch, to_post_decode, queue_debug), mut sim| async move {
+            // intentionally have a different sequence each time we're reset
+            let delay_sequence_index = Cell::new(0);
+            sim.resettable(
+                cd,
+                async |mut sim| {
+                    sim.write(from_fetch.inner.ready, false).await;
+                    sim.write(
+                        to_post_decode.inner.data,
+                        to_post_decode.ty().inner.data.HdlNone(),
+                    )
+                    .await;
+                    sim.write(
+                        queue_debug,
+                        queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim()),
+                    )
+                    .await;
+                },
+                |sim, ()| {
+                    run_fn(
+                        cd,
+                        from_fetch,
+                        to_post_decode,
+                        queue_debug,
+                        &delay_sequence_index,
+                        sim,
+                    )
+                },
+            )
+            .await;
+        },
+    );
+    #[hdl]
+    async fn run_fn(
+        cd: Expr<ClockDomain>,
+        from_fetch: Expr<NextPcToFetchInterface<PhantomConst<CpuConfig>>>,
+        to_post_decode: Expr<DecodeToPostDecodeInterface<PhantomConst<CpuConfig>>>,
+        queue_debug: Expr<ArrayVec<FetchPipeQueueEntry, ConstUsize<{ FETCH_PIPE_QUEUE_SIZE }>>>,
+        delay_sequence_index: &Cell<u64>,
+        mut sim: ExternModuleSimulationState,
+    ) {
+        let config = from_fetch.config.ty();
+        let mock_insns = MockInsns::new();
+        let mut queue: VecDeque<SimValue<FetchPipeQueueEntry>> = VecDeque::new();
+        let mut next_id = 0u32;
+        loop {
+            let mut sim_queue = queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim());
+            for entry in &queue {
+                ArrayVec::try_push_sim(&mut sim_queue, entry)
+                    .ok()
+                    .expect("queue is known to be small enough");
+            }
+            sim.write(queue_debug, sim_queue).await;
+            if let Some(front) = queue.front().filter(|v| v.cycles_left.as_int() == 0) {
+                #[hdl(sim)]
+                let FetchPipeQueueEntry {
+                    fetch_pc,
+                    cycles_left: _,
+                    fetch_block_id,
+                } = front;
+                let fetch_pc = fetch_pc.as_int();
+                let fetch_end =
+                    (fetch_pc + 1).next_multiple_of(config.get().fetch_width_in_bytes() as u64);
+                let insns = to_post_decode.ty().inner.data.HdlSome.insns;
+                let zeroed_insn = UInt[insns.element().canonical().bit_width()]
+                    .zero()
+                    .cast_bits_to(insns.element());
+                let mut insns = insns.new_sim(zeroed_insn);
+                let mut expected_pc = fetch_pc;
+                // TODO: handle instructions that go past the end of a fetch block
+                for (pc, insn) in mock_insns.fetch_block(fetch_pc..fetch_end) {
+                    let next_pc = pc + insn.byte_len();
+                    if pc != expected_pc {
+                        break;
+                    }
+                    expected_pc = next_pc;
+                    let kind = match insn {
+                        MockInsn::Nop4 => WipDecodedInsnKind.NonBranch(),
+                        MockInsn::Jump { target } => WipDecodedInsnKind.Branch(target),
+                        MockInsn::CondBranch { target } => WipDecodedInsnKind.BranchCond(target),
+                        MockInsn::Call { target } => WipDecodedInsnKind.Call(target),
+                        MockInsn::Ret => WipDecodedInsnKind.Ret(),
+                    };
+                    let insn = #[hdl(sim)]
+                    WipDecodedInsn {
+                        fetch_block_id,
+                        id: next_id.cast_to_static::<UInt<_>>(),
+                        pc,
+                        size_in_bytes: insn.byte_len().cast_to_static::<UInt<_>>(),
+                        kind,
+                    };
+                    match ArrayVec::try_push_sim(&mut insns, insn) {
+                        Ok(()) => next_id = next_id.wrapping_add(1),
+                        Err(_) => break,
+                    }
+                }
+                if **ArrayVec::len_sim(&insns) == 0 {
+                    let Ok(()) = ArrayVec::try_push_sim(
+                        &mut insns,
+                        #[hdl(sim)]
+                        WipDecodedInsn {
+                            fetch_block_id,
+                            id: next_id.cast_to_static::<UInt<_>>(),
+                            pc: fetch_pc,
+                            size_in_bytes: 0u8.cast_to_static::<UInt<_>>(),
+                            kind: WipDecodedInsnKind.Interrupt(DEMO_ILLEGAL_INSN_TRAP),
+                        },
+                    ) else {
+                        unreachable!();
+                    };
+                    next_id = next_id.wrapping_add(1);
+                }
+                sim.write(
+                    to_post_decode.inner.data,
+                    HdlSome(
+                        #[hdl(sim)]
+                        DecodeToPostDecodeInterfaceInner::<_> { insns, config },
+                    ),
+                )
+                .await;
+            } else {
+                sim.write(
+                    to_post_decode.inner.data,
+                    to_post_decode.ty().inner.data.HdlNone(),
+                )
+                .await;
+            }
+            sim.write(from_fetch.inner.ready, queue.len() < FETCH_PIPE_QUEUE_SIZE)
+                .await;
+            sim.wait_for_clock_edge(cd.clk).await;
+            if sim.read_past_bool(to_post_decode.inner.ready, cd.clk).await {
+                #[hdl(sim)]
+                if let HdlSome(_) = sim.read_past(to_post_decode.inner.data, cd.clk).await {
+                    queue.pop_front();
+                }
+            }
+            for entry in &mut queue {
+                if entry.cycles_left.as_int() > 0 {
+                    entry.cycles_left = (entry.cycles_left.as_int() - 1u8).to_sim_value();
+                }
+            }
+            if !sim.read_past_bool(from_fetch.inner.ready, cd.clk).await {
+                continue;
+            }
+            #[hdl(sim)]
+            if let HdlSome(inner) = sim.read_past(from_fetch.inner.data, cd.clk).await {
+                #[hdl(sim)]
+                let NextPcToFetchInterfaceInner {
+                    next_fetch_pc,
+                    fetch_block_id,
+                    in_progress_fetches_to_cancel,
+                } = &inner;
+                // cancel in-progress fetches from newest to oldest
+                for _ in 0..in_progress_fetches_to_cancel.as_int() {
+                    let _ = queue.pop_back();
+                }
+                queue.push_back(
+                    #[hdl(sim)]
+                    FetchPipeQueueEntry {
+                        fetch_pc: next_fetch_pc,
+                        cycles_left: FetchPipeQueueEntry::get_next_delay(delay_sequence_index),
+                        fetch_block_id,
+                    },
+                );
+            }
+        }
+    }
+}
+
+#[hdl_module]
+fn dut(config: PhantomConst<CpuConfig>) {
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let next_pc = instance(next_pc(config));
+    connect(next_pc.cd, cd);
+    #[hdl]
+    let mock_fetch_pipe = instance(mock_fetch_pipe(config));
+    connect(mock_fetch_pipe.cd, cd);
+    connect(mock_fetch_pipe.from_fetch, next_pc.to_fetch);
+    connect(next_pc.from_decode, mock_fetch_pipe.to_post_decode);
+}
+
+#[hdl]
+#[test]
+fn test_next_pc() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut config = CpuConfig::new(
+        vec![
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+        ],
+        NonZeroUsize::new(20).unwrap(),
+    );
+    config.fetch_width = NonZeroUsize::new(2).unwrap();
+    let m = dut(PhantomConst::new_sized(config));
+    let mut sim = Simulation::new(m);
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    for _cycle in 0..300 {
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    // FIXME: vcd is just whatever next_pc does now, which isn't known to be correct
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/next_pc.vcd") {
+        panic!();
+    }
+}

crates/cpu/tests/reg_alloc.rs

@@ -59,7 +59,7 @@ fn test_reg_alloc() {
                 [HdlSome(()), HdlNone()],
             },
             [0u8; 2],
-            0x12345678u32.cast_to_static(),
+            0x12345678u32.cast_to_static::<SInt<_>>(),
             OutputIntegerMode.DupLow32(),
             false,
             false,
@@ -81,7 +81,7 @@ fn test_reg_alloc() {
                 [HdlSome(()), HdlNone()],
             },
             [1u8, 0, 0],
-            1.cast_to_static(),
+            1.cast_to_static::<SInt<_>>(),
             OutputIntegerMode.Full64(),
             false,
             false,
@@ -99,7 +99,7 @@ fn test_reg_alloc() {
                 flag_regs: [HdlNone(), HdlSome(())],
             },
             [2u8, 4u8],
-            0.cast_to_static(),
+            0.cast_to_static::<SInt<_>>(),
             OutputIntegerMode.Full64(),
             0b0110_hdl_u4,
         ),