diff --git a/Cargo.lock b/Cargo.lock index f417853..90538a8 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -210,6 +210,8 @@ name = "cpu" version = "0.1.0" dependencies = [ "fayalite", + "serde", + "simple-mermaid", ] [[package]] @@ -303,7 +305,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6" [[package]] name = "fayalite" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57" +source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f" dependencies = [ "base64", "bitvec", @@ -330,7 +332,7 @@ dependencies = [ [[package]] name = "fayalite-proc-macros" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57" +source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f" dependencies = [ "fayalite-proc-macros-impl", ] @@ -338,7 +340,7 @@ dependencies = [ [[package]] name = "fayalite-proc-macros-impl" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57" +source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f" dependencies = [ "base16ct", "num-bigint", @@ -353,7 +355,7 @@ dependencies = [ [[package]] name = "fayalite-visit-gen" version = "0.3.0" -source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#edcc5927a5f9ebca6df5720bb1f5931e50095a57" +source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#9e803223d0f08c3398182cbabbff28cda7853b0f" dependencies = [ "indexmap", "prettyplease", @@ -689,6 +691,12 @@ version = "1.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64" +[[package]] +name = "simple-mermaid" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "589144a964b4b30fe3a83b4bb1a09e2475aac194ec832a046a23e75bddf9eb29" + [[package]] name = "strsim" version = "0.11.1" diff --git a/Cargo.toml b/Cargo.toml index 57ca631..00f2e67 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -15,6 +15,8 @@ rust-version = "1.89.0" [workspace.dependencies] fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" } +serde = { version = "1.0.202", features = ["derive"] } +simple-mermaid = "0.2.0" [profile.dev] opt-level = 1 diff --git a/crates/cpu/Cargo.toml b/crates/cpu/Cargo.toml index 16ec0b9..2f5f84c 100644 --- a/crates/cpu/Cargo.toml +++ b/crates/cpu/Cargo.toml @@ -16,3 +16,5 @@ version.workspace = true [dependencies] fayalite.workspace = true +serde.workspace = true +simple-mermaid.workspace = true diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs index 4e66010..acbec47 100644 --- a/crates/cpu/src/config.rs +++ b/crates/cpu/src/config.rs @@ -8,9 +8,10 @@ use crate::{ }, }; use fayalite::prelude::*; +use serde::{Deserialize, Serialize}; use std::num::NonZeroUsize; -#[derive(Clone, Eq, PartialEq, Hash, Debug)] +#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] #[non_exhaustive] pub struct UnitConfig { pub kind: UnitKind, @@ -27,12 +28,15 @@ impl UnitConfig { } } -#[derive(Clone, Eq, PartialEq, Hash, Debug)] +#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)] #[non_exhaustive] pub struct CpuConfig { pub units: Vec, pub out_reg_num_width: usize, pub fetch_width: NonZeroUsize, + pub max_branches_per_fetch: NonZeroUsize, + pub max_fetches_in_flight: NonZeroUsize, + pub log2_fetch_width_in_bytes: u8, /// default value for [`UnitConfig::max_in_flight`] pub default_unit_max_in_flight: NonZeroUsize, pub rob_size: NonZeroUsize, @@ -46,6 +50,19 @@ impl CpuConfig { }; v }; + pub const DEFAULT_MAX_BRANCHES_PER_FETCH: NonZeroUsize = { + let Some(v) = NonZeroUsize::new(1) else { + unreachable!(); + }; + v + }; + pub const DEFAULT_MAX_FETCHES_IN_FLIGHT: NonZeroUsize = { + let Some(v) = NonZeroUsize::new(16) else { + unreachable!(); + }; + v + }; + pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = { let Some(v) = NonZeroUsize::new(8) else { unreachable!(); @@ -57,6 +74,9 @@ impl CpuConfig { units, out_reg_num_width: Self::DEFAULT_OUT_REG_NUM_WIDTH, fetch_width: Self::DEFAULT_FETCH_WIDTH, + max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH, + max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT, + log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES, default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT, rob_size, } @@ -116,4 +136,27 @@ impl CpuConfig { UnitToRegAlloc[mop_ty][extra_out_ty][self.unit_num_width()][self.out_reg_num_width] [self.non_const_unit_nums().len()] } + pub fn fetch_width_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_fetch_width_in_bytes.into()) + .expect("log2_fetch_width_in_bytes is too big") + } } + +#[hdl(get(|c| c.fetch_width.get()))] +pub type CpuConfigFetchWidth> = DynSize; + +#[hdl(get(|c| c.fetch_width.get() * 2))] +pub type TwiceCpuConfigFetchWidth> = DynSize; + +#[hdl(get(|c| c.max_branches_per_fetch.get()))] +pub type CpuConfigMaxBranchesPerFetch> = DynSize; + +#[hdl(get(|c| c.max_fetches_in_flight.get()))] +pub type CpuConfigMaxFetchesInFlight> = DynSize; + +#[hdl(get(|c| c.log2_fetch_width_in_bytes.into()))] +pub type CpuConfigLog2FetchWidthInBytes> = DynSize; + +#[hdl(get(|c| c.fetch_width_in_bytes()))] +pub type CpuConfigFetchWidthInBytes> = DynSize; diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs index c410b56..1610750 100644 --- a/crates/cpu/src/instruction.rs +++ b/crates/cpu/src/instruction.rs @@ -2,12 +2,11 @@ // See Notices.txt for copyright information use crate::{unit::UnitMOp, util::range_u32_len}; use fayalite::{ - expr::ops::{ArrayLiteral, ExprPartialEq}, + expr::{HdlPartialEqImpl, ops::ArrayLiteral}, intern::Interned, prelude::*, - sim::value::SimValuePartialEq, }; -use std::{fmt, marker::PhantomData, ops::Range}; +use std::{borrow::Cow, fmt, marker::PhantomData, ops::Range}; pub mod power_isa; @@ -172,20 +171,38 @@ pub enum OutputIntegerMode { SignExt8, } -impl ExprPartialEq for OutputIntegerMode { - fn cmp_eq(lhs: Expr, rhs: Expr) -> Expr { +impl HdlPartialEqImpl for OutputIntegerMode { + #[track_caller] + fn cmp_value_eq( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: Self, + rhs_value: Cow<'_, Self::SimValue>, + ) -> bool { + SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned())) + == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned())) + } + + #[track_caller] + fn cmp_sim_value_eq( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>, + ) -> SimValue { + (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value() + } + + #[track_caller] + fn cmp_sim_value_ne( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>, + ) -> SimValue { + (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value() + } + + #[track_caller] + fn cmp_expr_eq(lhs: Expr, rhs: Expr) -> Expr { lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits()) } - - fn cmp_ne(lhs: Expr, rhs: Expr) -> Expr { - lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits()) - } -} - -impl SimValuePartialEq for OutputIntegerMode { - fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { - SimValue::opaque(this) == SimValue::opaque(other) - } } pub const MOP_IMM_WIDTH: usize = 34; @@ -296,8 +313,8 @@ impl, imm: impl ToExpr) { let expr = expr.to_expr(); - let src_reg_ty = Expr::ty(expr).src.element(); + let src_reg_ty = expr.ty().src.element(); let imm = imm.to_expr(); - assert_eq!(Expr::ty(imm), Self::imm_ty()); + assert_eq!(imm.ty(), Self::imm_ty()); let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty()); let mut src = [Some(0_hdl_u0.cast_to(src_reg_ty)); COMMON_MOP_SRC_LEN]; for i in 0..SrcCount::VALUE { @@ -496,7 +513,7 @@ macro_rules! mop_enum { fn dest_reg(input: impl ToExpr) -> Expr { let input = input.to_expr(); #[hdl] - let dest_reg = wire(Expr::ty(input).dest_reg_ty()); + let dest_reg = wire(input.ty().dest_reg_ty()); #[hdl] match input { Self::$FirstVariant(v) => connect(dest_reg, <$first_ty as MOpTrait>::dest_reg(v)), @@ -537,7 +554,7 @@ macro_rules! mop_enum { ) -> Expr> { let input = input.to_expr(); let new_dest = new_dest.to_expr(); - let mapped_ty = Expr::ty(input).mapped_ty(Expr::ty(new_dest), new_src_reg_width); + let mapped_ty = input.ty().mapped_ty(new_dest.ty(), new_src_reg_width); #[hdl] let mapped_regs = wire(mapped_ty); #[hdl] @@ -584,7 +601,7 @@ macro_rules! mop_enum { MOpInto::mop_into_ty($MOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]$([$sizes_get_size(self)])*) } fn mop_into(this: Expr) -> Expr { - MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>>::mop_into_ty(Expr::ty(this)).$Variant(this)) + MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>>::mop_into_ty(this.ty()).$Variant(this)) } } }; @@ -833,22 +850,19 @@ impl UnitNum { } pub fn is_index(expr: impl ToExpr, index: usize) -> Expr { let expr = expr.to_expr(); - Expr::ty(expr) - .from_index(index) - .adj_value - .cmp_eq(expr.adj_value) + expr.ty().from_index(index).adj_value.cmp_eq(expr.adj_value) } #[hdl] pub fn as_index(expr: impl ToExpr) -> Expr>> { let expr = expr.to_expr(); #[hdl] - let unit_index = wire(HdlOption[Expr::ty(expr).adj_value]); - connect(unit_index, Expr::ty(unit_index).HdlNone()); + let unit_index = wire(HdlOption[expr.ty().adj_value]); + connect(unit_index, unit_index.ty().HdlNone()); #[hdl] if expr.adj_value.cmp_ne(0u8) { connect( unit_index, - HdlSome((expr.adj_value - 1u8).cast_to(Expr::ty(expr).adj_value)), + HdlSome((expr.adj_value - 1u8).cast_to(expr.ty().adj_value)), ); } unit_index @@ -900,7 +914,7 @@ impl MOpRegNum { pub fn const_zero() -> Expr { #[hdl] MOpRegNum { - value: Self::CONST_ZERO_REG_NUM.cast_to_static(), + value: Self::CONST_ZERO_REG_NUM.cast_to_static::>(), } } /// a lot of instructions write to flag registers that we want @@ -1077,7 +1091,7 @@ impl MOpDestReg { flag_reg, #[hdl] MOpRegNum { - value: reg_num.cast_to_static(), + value: reg_num.cast_to_static::>(), }, ); } diff --git a/crates/cpu/src/lib.rs b/crates/cpu/src/lib.rs index bae3720..a00b668 100644 --- a/crates/cpu/src/lib.rs +++ b/crates/cpu/src/lib.rs @@ -2,6 +2,7 @@ // See Notices.txt for copyright information pub mod config; pub mod instruction; +pub mod next_pc; pub mod reg_alloc; pub mod register; pub mod unit; diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs new file mode 100644 index 0000000..97d2f33 --- /dev/null +++ b/crates/cpu/src/next_pc.rs @@ -0,0 +1,2821 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +//! [Next-Instruction Logic](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10) +//! +//! The basic idea here is that there's a `next_pc` stage that sends predicted fetch PCs to the `fetch` stage, +//! the `fetch` stage's outputs eventually end up in the `decode` stage, +//! after the `decode` stage there's a `post_decode` stage (that may run in the same clock cycle as `decode`) +//! that checks that the fetched instructions' kinds match the predicted instruction kinds and that feeds +//! information back to the `fetch` stage to cancel fetches that need to be predicted differently. +//! +#![doc = simple_mermaid::mermaid!("next_pc/next_pc.mermaid")] + +use crate::{ + config::{CpuConfig, CpuConfigFetchWidth, CpuConfigMaxFetchesInFlight}, + util::array_vec::ArrayVec, +}; +use fayalite::{ + expr::HdlPartialEqImpl, + int::{UIntInRange, UIntInRangeInclusive, UIntInRangeInclusiveType, UIntInRangeType}, + prelude::*, + sim::value::SimOnlyValueTrait, + ty::StaticType, + util::ready_valid::ReadyValid, +}; +use std::borrow::Cow; + +pub const FETCH_BLOCK_ID_WIDTH: usize = FetchBlockIdInt::BITS as usize; +type FetchBlockIdInt = u8; + +#[hdl] +pub struct NextPcToFetchInterfaceInner { + pub start_pc: UInt<64>, + pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, +} + +#[hdl(no_static)] +pub struct NextPcToFetchInterface> { + pub fetch: ReadyValid, + pub cancel: ReadyValid, CpuConfigMaxFetchesInFlight>>, + pub config: C, +} + +#[hdl] +/// WIP version of decoded instruction just good enough to represent stuff needed for [`next_pc()`] +/// since the actual instruction definition isn't finalized yet. +/// This will be replaced at a later point. +pub enum WipDecodedInsnKind { + NonBranch, + Branch(UInt<64>), + BranchCond(UInt<64>), + IndirectBranch, + Call(UInt<64>), + CallCond(UInt<64>), + IndirectCall, + Ret, + RetCond, + /// not actually an instruction read from memory, covers stuff like external interrupts, + /// page faults, memory errors, and so on. + Interrupt(UInt<64>), +} + +impl WipDecodedInsnKind { + /// if this instruction should behave like [`Self::Interrupt`], return the target PC. + #[hdl] + pub fn interrupt_target_pc_sim(this: &SimValue) -> Option<&SimValue>> { + #[hdl(sim)] + match this { + Self::NonBranch + | Self::Branch(_) + | Self::BranchCond(_) + | Self::IndirectBranch + | Self::Call(_) + | Self::CallCond(_) + | Self::IndirectCall + | Self::Ret + | Self::RetCond + | Self::Unknown => None, + Self::Interrupt(target_pc) => Some(target_pc), + } + } +} + +#[hdl] +/// WIP version of decoded instruction just good enough to represent stuff needed for [`next_pc()`] +/// since the actual instruction definition isn't finalized yet. +/// This will be replaced at a later point. +pub struct WipDecodedInsn { + pub fetch_block_id: UInt<8>, + pub id: UInt<12>, + pub pc: UInt<64>, + pub size_in_bytes: UInt<4>, + pub kind: WipDecodedInsnKind, +} + +#[hdl] +pub enum CallStackOp { + None, + Push(UInt<64>), + Pop, +} + +#[hdl(no_static)] +pub struct RetireToNextPcInterfacePerInsn> { + pub id: UInt<12>, + /// the pc after running this instruction. + pub next_pc: UInt<64>, + pub call_stack_op: CallStackOp, + /// should be `HdlSome(taken)` for any conditional control-flow instruction + /// with an immediate target that can be predicted as taken/not-taken (branch/call/return). + pub cond_br_taken: HdlOption, + pub config: C, +} + +impl SimValueDefault for RetireToNextPcInterfacePerInsn> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + id, + next_pc: _, + call_stack_op: _, + cond_br_taken: _, + config, + } = self; + #[hdl(sim)] + Self { + id: id.zero(), + next_pc: 0u64, + call_stack_op: #[hdl(sim)] + CallStackOp::None(), + cond_br_taken: #[hdl(sim)] + HdlNone(), + config, + } + } +} + +#[hdl(no_static)] +pub struct RetireToNextPcInterfaceInner> { + pub insns: ArrayVec, CpuConfigFetchWidth>, + pub config: C, +} + +#[hdl(no_static)] +/// handles updating speculative branch predictor state (e.g. branch histories) +/// when instructions retire, as well as updating state when a +/// branch instruction is mis-speculated. +pub struct RetireToNextPcInterface> { + pub inner: ReadyValid>, +} + +#[hdl(no_static)] +pub struct DecodeToPostDecodeInterfaceInner> { + pub insns: ArrayVec>, + // TODO: add needed fields + pub config: C, +} + +impl SimValueDefault for DecodeToPostDecodeInterfaceInner> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { insns, config } = self; + #[hdl(sim)] + Self { + insns: insns.sim_value_default(), + config, + } + } +} + +#[hdl(no_static)] +pub struct DecodeToPostDecodeInterface> { + pub inner: ReadyValid>, +} + +#[hdl(no_static)] +pub struct PostDecodeOutputInterface> { + pub insns: ArrayVec>, + #[hdl(flip)] + pub ready: UIntInRangeInclusiveType, CpuConfigFetchWidth>, + pub config: C, +} + +#[hdl] +struct TrainBranchPredictor { + branch_predictor_index: UIntInRange<0, { BRANCH_PREDICTOR_SIZE }>, + taken: Bool, +} + +#[hdl(no_static)] +struct Cancel> { + call_stack: CallStack, + start_pc: UInt<64>, + new_btb_entry: HdlOption, + btb_entry_index: HdlOption>, + branch_history: UInt<6>, + config: C, +} + +/// the output of [`Stage::run`]. +/// when cancelling operations, the returned [`StageOutput.cancel`] should be the state after +/// running all operations returned in [`StageOutput.output`]. +#[hdl(no_static)] +struct StageOutput> { + outputs: ArrayVec, + /// when set to [`HdlSome`], [`Stage::cancel`] is called on all previous stages + cancel: HdlOption>, +} + +trait Stage: Type + SimValueDefault + ResetSteps { + type Inputs: Type; + type Output: Type; + type MaxOutputCount: Size; + + fn output_ty(config: PhantomConst) -> Self::Output; + fn max_output_count( + config: PhantomConst, + ) -> ::SizeType; + fn stage_output_ty( + config: PhantomConst, + ) -> StageOutput> { + StageOutput[Self::output_ty(config)][Self::max_output_count(config)][config] + } + /// see [`StageOutput`] for docs on output + fn run( + state: &mut SimValue, + inputs: &SimValue, + ) -> SimValue>>; + /// changes state to match `cancel` + fn cancel(state: &mut SimValue, cancel: &SimValue>>); +} + +#[hdl(no_static)] +struct NextPcStageOutput> { + start_pc: UInt<64>, + next_start_pc: UInt<64>, + btb_entry: HdlOption<( + UIntInRange<0, { BranchTargetBuffer::SIZE }>, + BTBEntryWithoutStartPc, + )>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + start_call_stack: CallStack, + config: C, +} + +impl SimValueDefault for NextPcStageOutput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + start_pc: _, + next_start_pc: _, + btb_entry, + fetch_block_id: _, + start_call_stack, + config, + } = self; + #[hdl(sim)] + Self { + start_pc: 0u64, + next_start_pc: 0u64, + btb_entry: #[hdl(sim)] + btb_entry.HdlNone(), + fetch_block_id: 0u8, + start_call_stack: start_call_stack.sim_value_default(), + config, + } + } +} + +#[hdl(no_static)] +struct NextPcStageState> { + call_stack: CallStack, + branch_target_buffer: BranchTargetBuffer, + next_pc: UInt<64>, + next_fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + config: C, +} + +impl SimValueDefault for NextPcStageState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + call_stack, + branch_target_buffer, + next_pc: _, + next_fetch_block_id: _, + config, + } = self; + #[hdl(sim)] + Self { + call_stack: call_stack.sim_value_default(), + branch_target_buffer: branch_target_buffer.sim_value_default(), + // use something other than the default so you can see the reset progress + next_pc: !0u64, + // use something other than the default so you can see the reset progress + next_fetch_block_id: !0u8, + config, + } + } +} + +impl ResetSteps for NextPcStageState> { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + call_stack, + branch_target_buffer, + next_pc, + next_fetch_block_id, + config: _, + } = this; + **next_pc = 0u64.into(); // match Microwatt's reset PC + **next_fetch_block_id = 0u8.into(); + let call_stack = ResetSteps::reset_step(call_stack, step); + let branch_target_buffer = ResetSteps::reset_step(branch_target_buffer, step); + call_stack.and(branch_target_buffer) + } +} + +impl Stage for NextPcStageState> { + type Inputs = (); + type Output = NextPcStageOutput>; + type MaxOutputCount = ConstUsize<1>; + + fn output_ty(config: PhantomConst) -> Self::Output { + NextPcStageOutput[config] + } + + fn max_output_count( + _config: PhantomConst, + ) -> ::SizeType { + ConstUsize + } + + #[hdl] + fn run( + state: &mut SimValue, + _inputs: &SimValue, + ) -> SimValue>> { + let config = state.config.ty(); + let start_call_stack = state.call_stack.clone(); + let fetch_block_id = state.next_fetch_block_id.as_int(); + *state.next_fetch_block_id = state.next_fetch_block_id.as_int().wrapping_add(1).into(); + let start_pc = state.next_pc.as_int(); + let fetch_pc = start_pc & (!0u64 << config.get().log2_fetch_width_in_bytes); + + let btb_entry_index = state + .branch_target_buffer + .branch_pc_to_target_map + .iter() + .position(|entry| { + #[hdl(sim)] + match entry { + HdlNone => false, + HdlSome(entry) => entry.start_pc.as_int() == start_pc, + } + }); + let (next_start_pc, btb_entry) = if let Some(btb_entry_index) = btb_entry_index { + #[hdl(sim)] + let Self { + call_stack, + branch_target_buffer, + .. + } = state; + let entry = #[hdl(sim)] + match &branch_target_buffer.branch_pc_to_target_map[btb_entry_index] { + HdlSome(entry) => entry, + _ => unreachable!(), + }; + let next_start_pc = #[hdl(sim)] + match &entry.rest.insn_kind { + BTBEntryInsnKind::Branch => { + if BTBEntryAddrKind::taken(&entry.rest.addr_kind) { + BTBEntry::taken_pc(entry) + } else { + BTBEntry::not_taken_start_pc(entry) + } + } + BTBEntryInsnKind::Call => { + if BTBEntryAddrKind::taken(&entry.rest.addr_kind) { + CallStack::push(call_stack, BTBEntry::after_call_pc(entry)); + BTBEntry::taken_pc(entry) + } else { + BTBEntry::not_taken_start_pc(entry) + } + } + BTBEntryInsnKind::Ret => { + if BTBEntryAddrKind::taken(&entry.rest.addr_kind) { + CallStack::pop(call_stack).unwrap_or(BTBEntry::taken_pc(entry)) + } else { + BTBEntry::not_taken_start_pc(entry) + } + } + BTBEntryInsnKind::Unknown => unreachable!(), + }; + ( + next_start_pc, + #[hdl(sim)] + HdlSome((btb_entry_index, &entry.rest)), + ) + } else { + ( + fetch_pc.wrapping_add(config.get().fetch_width_in_bytes() as u64), + #[hdl(sim)] + HdlNone(), + ) + }; + let output = #[hdl(sim)] + NextPcStageOutput::<_> { + start_pc, + next_start_pc, + btb_entry, + fetch_block_id, + start_call_stack, + config, + }; + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: Self::stage_output_ty(config).outputs.new_full_sim([output]), + cancel: #[hdl(sim)] + (HdlOption[Cancel[config]]).HdlNone(), + } + } + + #[hdl] + fn cancel(state: &mut SimValue, cancel: &SimValue>>) { + #[hdl(sim)] + let Self { + call_stack, + branch_target_buffer, + next_pc, + next_fetch_block_id: _, + config: _, + } = state; + #[hdl(sim)] + let Cancel::<_> { + call_stack: new_call_stack, + start_pc, + new_btb_entry, + btb_entry_index, + branch_history: _, + config: _, + } = cancel; + call_stack.clone_from(new_call_stack); + next_pc.clone_from(start_pc); + #[hdl(sim)] + if let HdlSome(new_btb_entry) = new_btb_entry { + // add/update btb entry + + // get old entry if it's still there + let btb_entry_index = #[hdl(sim)] + if let HdlSome(btb_entry_index) = btb_entry_index { + #[hdl(sim)] + if let HdlSome(entry) = + &branch_target_buffer.branch_pc_to_target_map[**btb_entry_index] + { + if entry.start_pc == *start_pc { + // found the old entry + Some(**btb_entry_index) + } else { + None + } + } else { + None + } + } else { + None + }; + + let btb_entry_index = btb_entry_index.unwrap_or_else(|| { + // old entry isn't there, pick an entry to replace + BranchTargetBuffer::next_index_to_replace(branch_target_buffer) + }); + + // replace with new entry + branch_target_buffer.branch_pc_to_target_map[btb_entry_index] = #[hdl(sim)] + HdlSome( + #[hdl(sim)] + BTBEntry { + start_pc, + rest: new_btb_entry, + }, + ); + } else if let HdlSome(btb_entry_index) = btb_entry_index { + // remove btb entry if it's still there + let entry_mut = &mut branch_target_buffer.branch_pc_to_target_map[**btb_entry_index]; + #[hdl(sim)] + if let HdlSome(entry) = &entry_mut { + if entry.start_pc == *start_pc { + // we found it, remove it + *entry_mut = #[hdl(sim)] + HdlNone(); + } + } + } + } +} + +#[hdl(no_static)] +struct BrPredStageOutput> { + start_branch_history: UInt<6>, + branch_predictor_index: HdlOption>, + config: C, +} + +impl SimValueDefault for BrPredStageOutput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + Self { + start_branch_history: self.start_branch_history.zero(), + branch_predictor_index: #[hdl(sim)] + HdlNone(), + config: self.config, + } + } +} + +#[hdl(no_static)] +struct BrPredStageState> { + branch_history: UInt<6>, + branch_predictor: Array, + config: C, +} + +fn step_branch_history(branch_history: &mut SimValue>, taken: bool) { + **branch_history = + ((&**branch_history << 1) | taken.cast_to_static::>()).cast_to_static::>(); +} + +impl BrPredStageState> { + fn branch_predictor_index(this: &SimValue, branch_pc: u64) -> usize { + let mut t = this.branch_history.cast_to_static::>().as_int(); + t ^= t.rotate_left(5) & !branch_pc.rotate_right(3); + t ^= branch_pc; + t ^= !t.rotate_left(2) & t.rotate_left(4); + let mut retval = 0; + for i in (0..BRANCH_PREDICTOR_LOG2_SIZE).step_by(BRANCH_PREDICTOR_LOG2_SIZE) { + retval ^= t >> i; + } + retval as usize % BRANCH_PREDICTOR_SIZE + } +} + +impl SimValueDefault for BrPredStageState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + branch_history: _, + branch_predictor: _, + config, + } = self; + #[hdl(sim)] + Self { + // use something other than the default so you can see the reset progress + branch_history: (-1i8).cast_to_static::>(), + // use something other than the default so you can see the reset progress + branch_predictor: std::array::from_fn(|_| { + BranchPredictionState::towards_not_taken(&BranchPredictionState.sim_value_default()) + }), + config, + } + } +} + +impl ResetSteps for BrPredStageState> { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + branch_history, + branch_predictor, + config: _, + } = this; + **branch_history = 0u8.cast_to_static::>(); + ResetSteps::reset_step(branch_predictor, step) + } +} + +impl Stage for BrPredStageState> { + type Inputs = NextPcStageOutput>; + type Output = BrPredStageOutput>; + type MaxOutputCount = ConstUsize<1>; + + fn output_ty(config: PhantomConst) -> Self::Output { + BrPredStageOutput[config] + } + + fn max_output_count( + _config: PhantomConst, + ) -> ::SizeType { + ConstUsize + } + + #[hdl] + fn run( + state: &mut SimValue, + inputs: &SimValue, + ) -> SimValue>> { + let config = state.config.ty(); + #[hdl(sim)] + let NextPcStageOutput::<_> { + start_pc, + next_start_pc: _, + btb_entry, + fetch_block_id: _, + start_call_stack, + config: _, + } = inputs; + let start_branch_history = state.branch_history.clone(); + let mut branch_predictor_index = #[hdl(sim)] + HdlNone(); + #[hdl(sim)] + if let HdlSome(btb_entry) = btb_entry { + let taken_and_opposite_addr_kind = #[hdl(sim)] + match &btb_entry.1.addr_kind { + BTBEntryAddrKind::Unconditional | BTBEntryAddrKind::Indirect => None, + BTBEntryAddrKind::CondTaken => Some(( + true, + #[hdl(sim)] + BTBEntryAddrKind::CondNotTaken(), + )), + BTBEntryAddrKind::CondNotTaken => Some(( + false, + #[hdl(sim)] + BTBEntryAddrKind::CondTaken(), + )), + }; + if let Some((taken, opposite_addr_kind)) = taken_and_opposite_addr_kind { + let index = Self::branch_predictor_index( + state, + BTBEntry::branch_pc( + &#[hdl(sim)] + BTBEntry { + start_pc, + rest: &btb_entry.1, + }, + ), + ); + if taken != BranchPredictionState::is_taken(&state.branch_predictor[index]) { + let btb_entry_index = &btb_entry.0; + let mut btb_entry = btb_entry.1.clone(); + btb_entry.addr_kind = opposite_addr_kind; + let StageOutput { outputs, cancel } = Self::stage_output_ty(config); + let retval = #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: outputs.sim_value_default(), + cancel: #[hdl(sim)] + cancel.HdlSome( + #[hdl(sim)] + Cancel::<_> { + call_stack: start_call_stack, + start_pc, + new_btb_entry: #[hdl(sim)] + HdlSome(btb_entry), + btb_entry_index: #[hdl(sim)] + HdlSome(btb_entry_index), + branch_history: start_branch_history, + config, + }, + ), + }; + return retval; + } + branch_predictor_index = #[hdl(sim)] + HdlSome(index.cast_to_static::>()); + step_branch_history(&mut state.branch_history, taken); + } + } + let output = #[hdl(sim)] + BrPredStageOutput::<_> { + start_branch_history, + branch_predictor_index, + config, + }; + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: Self::stage_output_ty(config).outputs.new_full_sim([output]), + cancel: #[hdl(sim)] + (HdlOption[Cancel[config]]).HdlNone(), + } + } + + #[hdl] + fn cancel(state: &mut SimValue, cancel: &SimValue>>) { + #[hdl(sim)] + let Cancel::<_> { + call_stack: _, + start_pc: _, + new_btb_entry: _, + btb_entry_index: _, + branch_history, + config: _, + } = cancel; + state.branch_history.clone_from(branch_history); + } +} + +impl BrPredStageState> { + #[hdl] + fn train_branch_predictor( + this: &mut SimValue, + train_branch_predictor: &SimValue, + ) { + #[hdl(sim)] + let TrainBranchPredictor { + branch_predictor_index, + taken, + } = train_branch_predictor; + let branch_prediction_state = &mut this.branch_predictor[**branch_predictor_index]; + if **taken { + *branch_prediction_state = + BranchPredictionState::towards_taken(branch_prediction_state); + } else { + *branch_prediction_state = + BranchPredictionState::towards_not_taken(branch_prediction_state); + } + } +} + +#[hdl(no_static)] +struct FetchDecodeStageState> { + config: C, +} + +impl SimValueDefault for FetchDecodeStageState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + Self { + config: self.config, + } + } +} + +impl ResetSteps for FetchDecodeStageState> { + #[hdl] + fn reset_step(this: &mut SimValue, _step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { config: _ } = this; + ResetStatus::Done + } +} + +#[hdl(no_static)] +struct FetchDecodeStageOutput> { + next_pc_stage_output: NextPcStageOutput, + decode_output: DecodeToPostDecodeInterfaceInner, +} + +impl SimValueDefault for FetchDecodeStageOutput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + next_pc_stage_output, + decode_output, + } = self; + #[hdl(sim)] + Self { + next_pc_stage_output: next_pc_stage_output.sim_value_default(), + decode_output: decode_output.sim_value_default(), + } + } +} + +impl Stage for FetchDecodeStageState> { + type Inputs = FetchDecodeStageOutput>; + type Output = FetchDecodeStageOutput>; + type MaxOutputCount = ConstUsize<1>; + + fn output_ty(config: PhantomConst) -> Self::Output { + FetchDecodeStageOutput[config] + } + + fn max_output_count( + _config: PhantomConst, + ) -> ::SizeType { + ConstUsize + } + + #[hdl] + fn run( + state: &mut SimValue, + inputs: &SimValue, + ) -> SimValue>> { + #[hdl(sim)] + let Self { config } = state; + let config = config.ty(); + let StageOutput { outputs, cancel } = Self::stage_output_ty(config); + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: outputs.new_full_sim([inputs]), + cancel: #[hdl(sim)] + cancel.HdlNone(), + } + } + + #[hdl] + fn cancel(state: &mut SimValue, _cancel: &SimValue>>) { + #[hdl(sim)] + let Self { config: _ } = state; + } +} + +#[hdl(no_static)] +struct PostDecodeStageState> { + config: C, +} + +#[hdl(no_static)] +struct PostDecodeStageInput> { + fetch_decode_stage_output: FetchDecodeStageOutput, + br_pred_stage_output: BrPredStageOutput, +} + +impl SimValueDefault for PostDecodeStageInput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + Self { + fetch_decode_stage_output: self.fetch_decode_stage_output.sim_value_default(), + br_pred_stage_output: self.br_pred_stage_output.sim_value_default(), + } + } +} + +#[hdl(no_static)] +struct PostDecodeStageOutput> { + insn: WipDecodedInsn, + next_pc: UInt<64>, + btb_entry_index: HdlOption>, + start_branch_history: UInt<6>, + start_call_stack: CallStack, + branch_predictor_index: HdlOption>, + config: C, +} + +impl SimValueDefault for PostDecodeStageOutput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + Self { + insn: self.insn.sim_value_default(), + next_pc: 0u64, + btb_entry_index: #[hdl(sim)] + HdlNone(), + start_branch_history: self.start_branch_history.zero(), + start_call_stack: self.start_call_stack.sim_value_default(), + branch_predictor_index: #[hdl(sim)] + HdlNone(), + config: self.config, + } + } +} + +impl SimValueDefault for PostDecodeStageState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + Self { + config: self.config, + } + } +} + +impl ResetSteps for PostDecodeStageState> { + #[hdl] + fn reset_step(this: &mut SimValue, _step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { config: _ } = this; + ResetStatus::Done + } +} + +impl Stage for PostDecodeStageState> { + type Inputs = PostDecodeStageInput>; + type Output = PostDecodeStageOutput>; + type MaxOutputCount = CpuConfigFetchWidth>; + + fn output_ty(config: PhantomConst) -> Self::Output { + PostDecodeStageOutput[config] + } + + fn max_output_count( + config: PhantomConst, + ) -> ::SizeType { + CpuConfigFetchWidth[config] + } + + #[hdl] + fn run( + state: &mut SimValue, + inputs: &SimValue, + ) -> SimValue>> { + #[hdl(sim)] + let Self { config } = state; + let config = config.ty(); + #[hdl(sim)] + let PostDecodeStageInput::<_> { + fetch_decode_stage_output, + br_pred_stage_output, + } = inputs; + #[hdl(sim)] + let FetchDecodeStageOutput::<_> { + next_pc_stage_output, + decode_output, + } = fetch_decode_stage_output; + #[hdl(sim)] + let NextPcStageOutput::<_> { + start_pc, + next_start_pc: predicted_next_start_pc, + btb_entry: predicted_btb_entry, + fetch_block_id, + start_call_stack, + config: _, + } = next_pc_stage_output; + #[hdl(sim)] + let DecodeToPostDecodeInterfaceInner::<_> { insns, config: _ } = decode_output; + #[hdl(sim)] + let BrPredStageOutput::<_> { + start_branch_history, + branch_predictor_index, + config: _, + } = br_pred_stage_output; + assert_ne!( + **ArrayVec::len_sim(&insns), + 0, + "fetch/decode must always return at least one instruction \ + -- either the decoded instructions or a WipDecodedInsnKind::Interrupt", + ); + let insns = ArrayVec::elements_sim_ref(&insns); + let StageOutput { + outputs: outputs_ty, + cancel: cancel_ty, + } = Self::stage_output_ty(config); + assert_eq!(outputs_ty.capacity(), decode_output.insns.ty().capacity()); + let mut outputs = outputs_ty.sim_value_default(); + let mut add_output_insn = |insn: &SimValue, + next_pc: Option, + can_train_cond_branch_predictor: bool, + fallthrough_offset: &mut u8| { + ArrayVec::try_push_sim( + &mut outputs, + #[hdl(sim)] + PostDecodeStageOutput::<_> { + insn, + next_pc: next_pc.unwrap_or_else(|| { + insn.pc + .as_int() + .wrapping_add(insn.size_in_bytes.cast_to_static::>().as_int()) + }), + btb_entry_index: #[hdl(sim)] + match predicted_btb_entry { + HdlSome(predicted_btb_entry) => + { + #[hdl(sim)] + HdlSome(&predicted_btb_entry.0) + } + HdlNone => + { + #[hdl(sim)] + HdlNone() + } + }, + start_branch_history, + start_call_stack, + branch_predictor_index: if can_train_cond_branch_predictor { + branch_predictor_index.clone() + } else { + #[hdl(sim)] + HdlNone() + }, + config, + }, + ) + .expect("known to be in bounds"); + *fallthrough_offset += insn.size_in_bytes.cast_to_static::>().as_int(); + }; + if let Some(target_pc) = WipDecodedInsnKind::interrupt_target_pc_sim(&insns[0].kind) { + add_output_insn(&insns[0], Some(target_pc.as_int()), false, &mut 0); + let mut call_stack = start_call_stack.clone(); + CallStack::push(&mut call_stack, start_pc); + let retval = #[hdl(sim)] + StageOutput::<_, _, _> { + outputs, + cancel: #[hdl(sim)] + cancel_ty.HdlSome( + #[hdl(sim)] + Cancel::<_> { + call_stack, + start_pc: target_pc, + new_btb_entry: #[hdl(sim)] + HdlNone(), + btb_entry_index: #[hdl(sim)] + HdlNone(), + branch_history: start_branch_history, + config, + }, + ), + }; + return retval; + } + let mut fallthrough_offset = 0u8; + let mut branch_offset = 0u8; + let mut after_call_offset = 0u8; + let mut btb_entry_fields = None; + for insn in insns { + #[hdl(sim)] + let WipDecodedInsn { + fetch_block_id: insn_fetch_block_id, + id: _, + pc, + size_in_bytes: _, + kind, + } = insn; + assert_eq!( + insn_fetch_block_id, fetch_block_id, + "fetch decode pipeline's output isn't in-sync with fetching_queue", + ); + let guess_branch_addr_kind = |fallback_taken| { + #[hdl(sim)] + if let HdlSome(entry) = predicted_btb_entry { + let addr_kind = &entry.1.addr_kind; + #[hdl(sim)] + match addr_kind { + BTBEntryAddrKind::Unconditional | BTBEntryAddrKind::Indirect => {} + BTBEntryAddrKind::CondTaken | BTBEntryAddrKind::CondNotTaken => { + return addr_kind.clone(); + } + } + } + if fallback_taken { + #[hdl(sim)] + BTBEntryAddrKind::CondTaken() + } else { + #[hdl(sim)] + BTBEntryAddrKind::CondNotTaken() + } + }; + let insn_kind; + let addr_kind; + let can_train_cond_branch_predictor; + let target_pc = #[hdl(sim)] + match kind { + WipDecodedInsnKind::NonBranch => { + add_output_insn(insn, None, false, &mut fallthrough_offset); + continue; + } + WipDecodedInsnKind::Branch(target_pc) => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Branch(); + addr_kind = #[hdl(sim)] + BTBEntryAddrKind::Unconditional(); + can_train_cond_branch_predictor = false; + Some(target_pc.as_int()) + } + WipDecodedInsnKind::BranchCond(target_pc) => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Branch(); + // guess backwards branches are taken and forwards branches are not + addr_kind = guess_branch_addr_kind(target_pc.as_int() <= pc.as_int()); + can_train_cond_branch_predictor = true; + Some(target_pc.as_int()) + } + WipDecodedInsnKind::IndirectBranch => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Branch(); + addr_kind = #[hdl(sim)] + BTBEntryAddrKind::Indirect(); + can_train_cond_branch_predictor = false; + None + } + WipDecodedInsnKind::Call(target_pc) => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Call(); + addr_kind = #[hdl(sim)] + BTBEntryAddrKind::Unconditional(); + can_train_cond_branch_predictor = false; + Some(target_pc.as_int()) + } + WipDecodedInsnKind::CallCond(target_pc) => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Call(); + // guess conditional calls are taken + addr_kind = guess_branch_addr_kind(true); + can_train_cond_branch_predictor = true; + Some(target_pc.as_int()) + } + WipDecodedInsnKind::IndirectCall => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Call(); + addr_kind = #[hdl(sim)] + BTBEntryAddrKind::Indirect(); + can_train_cond_branch_predictor = false; + None + } + WipDecodedInsnKind::Ret => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Ret(); + addr_kind = #[hdl(sim)] + BTBEntryAddrKind::Unconditional(); + can_train_cond_branch_predictor = false; + None + } + WipDecodedInsnKind::RetCond => { + insn_kind = #[hdl(sim)] + BTBEntryInsnKind::Ret(); + // guess conditional returns are taken + addr_kind = guess_branch_addr_kind(true); + can_train_cond_branch_predictor = true; + None + } + WipDecodedInsnKind::Interrupt(_) => { + // interrupt after other instructions, + // just truncate the fetch block before the interrupt + break; + } + WipDecodedInsnKind::Unknown => unreachable!(), + }; + + // all branches/calls/returns end up here + + if btb_entry_fields.is_some() { + // TODO: maybe implement handling multiple ctrl transfer insns in the same fetch block, + // for now we just truncate the fetch block right before the second ctrl transfer insn. + break; + } + branch_offset = fallthrough_offset; + let target_pc = target_pc.unwrap_or_else(|| predicted_next_start_pc.as_int()); + add_output_insn( + insn, + Some(target_pc), + can_train_cond_branch_predictor, + &mut fallthrough_offset, + ); + #[hdl(sim)] + match &insn_kind { + BTBEntryInsnKind::Call => after_call_offset = fallthrough_offset, + BTBEntryInsnKind::Branch | BTBEntryInsnKind::Ret | BTBEntryInsnKind::Unknown => {} + } + btb_entry_fields = Some((insn_kind, addr_kind, target_pc)); + } + let new_btb_entry = if let Some((insn_kind, addr_kind, target_pc)) = btb_entry_fields { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + BTBEntryWithoutStartPc { + target_pc, + fallthrough_offset, + branch_offset, + after_call_offset, + insn_kind, + addr_kind, + }, + ) + } else { + #[hdl(sim)] + HdlNone() + }; + let (btb_entry_index, predicted_btb_entry) = #[hdl(sim)] + match predicted_btb_entry { + HdlSome(predicted_btb_entry) => { + #[hdl(sim)] + let (btb_entry_index, predicted_btb_entry) = predicted_btb_entry; + ( + #[hdl(sim)] + HdlSome(btb_entry_index), + #[hdl(sim)] + HdlSome(predicted_btb_entry), + ) + } + HdlNone => ( + #[hdl(sim)] + HdlNone(), + #[hdl(sim)] + HdlNone(), + ), + }; + if *new_btb_entry.cmp_ne(predicted_btb_entry) { + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: outputs_ty.sim_value_default(), + cancel: #[hdl(sim)] + cancel_ty.HdlSome( + #[hdl(sim)] + Cancel::<_> { + call_stack: start_call_stack, + start_pc, + new_btb_entry, + btb_entry_index, + branch_history: start_branch_history, + config, + }, + ), + } + } else { + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs, + cancel: #[hdl(sim)] + cancel_ty.HdlNone(), + } + } + } + + #[hdl] + fn cancel(state: &mut SimValue, _cancel: &SimValue>>) { + #[hdl(sim)] + let Self { config: _ } = state; + } +} + +#[hdl(no_static)] +struct RenameDispatchExecuteStageState> { + config: C, +} + +#[hdl(no_static)] +struct RenameDispatchExecuteStageOutput> { + post_decode_stage_output: PostDecodeStageOutput, +} + +impl SimValueDefault for RenameDispatchExecuteStageOutput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + post_decode_stage_output, + } = self; + #[hdl(sim)] + Self { + post_decode_stage_output: post_decode_stage_output.sim_value_default(), + } + } +} + +impl SimValueDefault for RenameDispatchExecuteStageState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { config } = self; + #[hdl(sim)] + Self { config } + } +} + +impl ResetSteps for RenameDispatchExecuteStageState> { + #[hdl] + fn reset_step(this: &mut SimValue, _step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { config: _ } = this; + ResetStatus::Done + } +} + +impl Stage for RenameDispatchExecuteStageState> { + type Inputs = RenameDispatchExecuteStageOutput>; + type Output = RenameDispatchExecuteStageOutput>; + type MaxOutputCount = ConstUsize<1>; + + fn output_ty(config: PhantomConst) -> Self::Output { + RenameDispatchExecuteStageOutput[config] + } + + fn max_output_count( + _config: PhantomConst, + ) -> ::SizeType { + ConstUsize + } + + #[hdl] + fn run( + state: &mut SimValue, + inputs: &SimValue, + ) -> SimValue>> { + #[hdl(sim)] + let Self { config } = state; + let config = config.ty(); + let StageOutput { outputs, cancel } = Self::stage_output_ty(config); + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: outputs.new_full_sim([inputs]), + cancel: #[hdl(sim)] + cancel.HdlNone(), + } + } + + #[hdl] + fn cancel(state: &mut SimValue, _cancel: &SimValue>>) { + #[hdl(sim)] + let Self { config: _ } = state; + } +} + +#[hdl(no_static)] +struct RetireStageInput> { + rename_dispatch_execute_stage_output: RenameDispatchExecuteStageOutput, + retire_interface_per_insn: RetireToNextPcInterfacePerInsn, +} + +impl SimValueDefault for RetireStageInput> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + rename_dispatch_execute_stage_output, + retire_interface_per_insn, + } = self; + #[hdl(sim)] + Self { + rename_dispatch_execute_stage_output: rename_dispatch_execute_stage_output + .sim_value_default(), + retire_interface_per_insn: retire_interface_per_insn.sim_value_default(), + } + } +} + +#[hdl(no_static)] +struct RetireStageState> { + config: C, +} + +#[hdl(no_static)] +struct RetireStageOutput> { + train_branch_predictor: HdlOption, + config: C, +} + +impl SimValueDefault for RetireStageState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { config } = self; + #[hdl(sim)] + Self { config } + } +} + +impl ResetSteps for RetireStageState> { + #[hdl] + fn reset_step(this: &mut SimValue, _step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { config: _ } = this; + ResetStatus::Done + } +} + +impl Stage for RetireStageState> { + type Inputs = RetireStageInput>; + type Output = RetireStageOutput>; + type MaxOutputCount = ConstUsize<1>; + + fn output_ty(config: PhantomConst) -> Self::Output { + RetireStageOutput[config] + } + + fn max_output_count( + _config: PhantomConst, + ) -> ::SizeType { + ConstUsize + } + + #[hdl] + fn run( + state: &mut SimValue, + inputs: &SimValue, + ) -> SimValue>> { + #[hdl(sim)] + let Self { config } = state; + let config = config.ty(); + #[hdl(sim)] + let RetireStageInput::<_> { + rename_dispatch_execute_stage_output, + retire_interface_per_insn, + } = inputs; + #[hdl(sim)] + let RetireToNextPcInterfacePerInsn::<_> { + id, + next_pc, + call_stack_op, + cond_br_taken, + config: _, + } = retire_interface_per_insn; + #[hdl(sim)] + let RenameDispatchExecuteStageOutput::<_> { + post_decode_stage_output, + } = rename_dispatch_execute_stage_output; + #[hdl(sim)] + let PostDecodeStageOutput::<_> { + insn, + next_pc: predicted_next_pc, + btb_entry_index, + start_branch_history, + start_call_stack, + branch_predictor_index, + config: _, + } = post_decode_stage_output; + assert_eq!(*id, insn.id, "instruction queuing out of sync"); + let StageOutput { + outputs: outputs_ty, + cancel: cancel_ty, + } = Self::stage_output_ty(config); + let mut branch_history = start_branch_history.clone(); + let train_branch_predictor = #[hdl(sim)] + if let HdlSome(taken) = cond_br_taken { + step_branch_history(&mut branch_history, **taken); + #[hdl(sim)] + if let HdlSome(branch_predictor_index) = branch_predictor_index { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + TrainBranchPredictor { + branch_predictor_index, + taken, + }, + ) + } else { + unreachable!() + } + } else { + #[hdl(sim)] + HdlNone() + }; + if next_pc != predicted_next_pc { + let cond_addr_kind = || { + #[hdl(sim)] + if let HdlSome(cond_br_taken) = cond_br_taken { + if **cond_br_taken { + #[hdl(sim)] + BTBEntryAddrKind::CondTaken() + } else { + #[hdl(sim)] + BTBEntryAddrKind::CondNotTaken() + } + } else { + unreachable!(); + } + }; + let make_btb_entry = + |after_call_offset: u8, + insn_kind: SimValue, + addr_kind: SimValue| { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + BTBEntryWithoutStartPc { + target_pc: next_pc, + fallthrough_offset: insn.size_in_bytes.cast_to_static::>(), + branch_offset: 0u8, + after_call_offset, + insn_kind, + addr_kind, + }, + ) + }; + let new_btb_entry = #[hdl(sim)] + match &insn.kind { + WipDecodedInsnKind::Branch(_) => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Branch(), + #[hdl(sim)] + BTBEntryAddrKind::Unconditional(), + ), + WipDecodedInsnKind::BranchCond(_) => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Branch(), + cond_addr_kind(), + ), + WipDecodedInsnKind::IndirectBranch => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Branch(), + #[hdl(sim)] + BTBEntryAddrKind::Indirect(), + ), + WipDecodedInsnKind::Call(_) => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Call(), + #[hdl(sim)] + BTBEntryAddrKind::Unconditional(), + ), + WipDecodedInsnKind::CallCond(_) => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Call(), + cond_addr_kind(), + ), + WipDecodedInsnKind::IndirectCall => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Call(), + #[hdl(sim)] + BTBEntryAddrKind::Indirect(), + ), + WipDecodedInsnKind::Ret => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Ret(), + #[hdl(sim)] + BTBEntryAddrKind::Unconditional(), + ), + WipDecodedInsnKind::RetCond => make_btb_entry( + 0, + #[hdl(sim)] + BTBEntryInsnKind::Ret(), + cond_addr_kind(), + ), + WipDecodedInsnKind::NonBranch | WipDecodedInsnKind::Interrupt(_) => + { + #[hdl(sim)] + HdlNone() + } + WipDecodedInsnKind::Unknown => unreachable!(), + }; + let mut call_stack = start_call_stack.clone(); + #[hdl(sim)] + match call_stack_op { + CallStackOp::None => {} + CallStackOp::Push(pc) => CallStack::push(&mut call_stack, pc), + CallStackOp::Pop => { + CallStack::pop(&mut call_stack); + } + CallStackOp::Unknown => unreachable!(), + } + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: outputs_ty.new_sim( + #[hdl(sim)] + RetireStageOutput::<_> { + train_branch_predictor, + config, + }, + ), + cancel: #[hdl(sim)] + cancel_ty.HdlSome( + #[hdl(sim)] + Cancel::<_> { + call_stack, + start_pc: next_pc, + new_btb_entry, + btb_entry_index, + branch_history, + config, + }, + ), + } + } else { + #[hdl(sim)] + StageOutput::<_, _, _> { + outputs: outputs_ty.new_full_sim([ + #[hdl(sim)] + RetireStageOutput::<_> { + train_branch_predictor, + config, + }, + ]), + cancel: #[hdl(sim)] + cancel_ty.HdlNone(), + } + } + } + + #[hdl] + fn cancel(state: &mut SimValue, _cancel: &SimValue>>) { + #[hdl(sim)] + let Self { config: _ } = state; + } +} + +#[hdl] +enum BranchPredictionState { + StronglyNotTaken, + WeaklyNotTaken, + WeaklyTaken, + StronglyTaken, +} + +impl BranchPredictionState { + #[must_use] + #[hdl] + fn is_taken(this: &SimValue) -> bool { + #[hdl(sim)] + match this { + Self::StronglyNotTaken => false, + Self::WeaklyNotTaken => false, + Self::WeaklyTaken => true, + Self::StronglyTaken => true, + } + } + #[must_use] + #[hdl] + fn towards_taken(this: &SimValue) -> SimValue { + (#[hdl(sim)] + match this { + Self::StronglyNotTaken => BranchPredictionState.WeaklyNotTaken(), + Self::WeaklyNotTaken => BranchPredictionState.WeaklyTaken(), + Self::WeaklyTaken => BranchPredictionState.StronglyTaken(), + Self::StronglyTaken => BranchPredictionState.StronglyTaken(), + }) + .to_sim_value() + } + #[must_use] + #[hdl] + fn towards_not_taken(this: &SimValue) -> SimValue { + (#[hdl(sim)] + match this { + Self::StronglyNotTaken => BranchPredictionState.StronglyNotTaken(), + Self::WeaklyNotTaken => BranchPredictionState.StronglyNotTaken(), + Self::WeaklyTaken => BranchPredictionState.WeaklyNotTaken(), + Self::StronglyTaken => BranchPredictionState.WeaklyTaken(), + }) + .to_sim_value() + } +} + +impl SimValueDefault for BranchPredictionState { + fn sim_value_default(self) -> SimValue { + self.WeaklyNotTaken().to_sim_value() + } +} + +#[derive(Copy, Clone, Debug)] +#[must_use] +enum ResetStatus { + Done, + Working, +} + +impl ResetStatus { + fn and(self, other: Self) -> Self { + match (self, other) { + (ResetStatus::Done, ResetStatus::Done) => ResetStatus::Done, + (ResetStatus::Done | ResetStatus::Working, ResetStatus::Working) + | (ResetStatus::Working, ResetStatus::Done) => ResetStatus::Working, + } + } +} + +trait SimValueDefault: Type { + fn sim_value_default(self) -> SimValue; +} + +impl SimValueDefault for SimOnly { + fn sim_value_default(self) -> SimValue { + SimOnlyValue::::default().to_sim_value_with_type(self) + } +} + +impl SimValueDefault for ArrayVec { + fn sim_value_default(self) -> SimValue { + self.new_sim(self.element().sim_value_default()) + } +} + +impl SimValueDefault for HdlOption { + fn sim_value_default(self) -> SimValue { + self.HdlNone().to_sim_value_with_type(self) + } +} + +impl SimValueDefault for Bool { + fn sim_value_default(self) -> SimValue { + false.to_sim_value() + } +} + +impl SimValueDefault for UIntType { + fn sim_value_default(self) -> SimValue { + self.zero().to_sim_value() + } +} + +impl SimValueDefault for WipDecodedInsnKind { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + WipDecodedInsnKind::NonBranch() + } +} + +impl SimValueDefault for WipDecodedInsn { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + fetch_block_id, + id, + pc, + size_in_bytes, + kind, + } = self; + #[hdl(sim)] + WipDecodedInsn { + fetch_block_id: fetch_block_id.sim_value_default(), + id: id.sim_value_default(), + pc: pc.sim_value_default(), + size_in_bytes: size_in_bytes.sim_value_default(), + kind: kind.sim_value_default(), + } + } +} + +trait ResetSteps: Type { + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus; +} + +impl ResetSteps for ArrayType { + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + let element = this.ty().element(); + let len = this.ty().len(); + if step < len { + this[step] = element.sim_value_default(); + } + if step.saturating_add(1) >= len { + ResetStatus::Done + } else { + ResetStatus::Working + } + } +} + +#[hdl] +struct CallStack { + return_addresses: Array, { CallStack::SIZE }>, + len: UIntInRangeInclusive<0, { CallStack::SIZE }>, + top: UIntInRange<0, { CallStack::SIZE }>, +} + +impl CallStack { + const SIZE: usize = 16; + fn push(this: &mut SimValue, value: impl ToSimValue>) { + let new_len = *this.len + 1; + *this.len = if new_len > Self::SIZE { + Self::SIZE + } else { + new_len + }; + let top = *this.top; + this.return_addresses[top] = value.into_sim_value(); + *this.top = (top + 1) % Self::SIZE; + } + fn pop(this: &mut SimValue) -> Option { + if *this.len == 0 { + None + } else { + *this.len -= 1; + let top = *this.top; + let top = (top + Self::SIZE - 1) % Self::SIZE; + *this.top = top; + Some(this.return_addresses[top].as_int()) + } + } +} + +impl SimValueDefault for CallStack { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + CallStack { + // something other than zero so you can see the values getting reset + return_addresses: [!0u64; Self::SIZE], + len: 0usize.to_sim_value_with_type(self.len), + top: 0usize.to_sim_value_with_type(self.top), + } + } +} + +impl ResetSteps for CallStack { + #[hdl] + fn reset_step(this: &mut SimValue, _step: usize) -> ResetStatus { + #[hdl(sim)] + let CallStack { + return_addresses, + len, + top, + } = this; + // return_addresses is implemented as a shift register, so it can be all reset at once + return_addresses.fill(0u64.to_sim_value()); + **len = 0; + **top = 0; + ResetStatus::Done + } +} + +#[hdl] +enum BTBEntryInsnKind { + Branch, + Call, + Ret, +} + +// TODO: replace with #[hdl(cmp_eq)] when that's implemented for enums +impl HdlPartialEqImpl for BTBEntryInsnKind { + #[track_caller] + fn cmp_value_eq( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: Self, + rhs_value: Cow<'_, Self::SimValue>, + ) -> bool { + *Self::cmp_sim_value_eq( + Cow::Owned(SimValue::from_value(lhs, lhs_value.into_owned())), + Cow::Owned(SimValue::from_value(rhs, rhs_value.into_owned())), + ) + } + + #[track_caller] + fn cmp_sim_value_eq( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>, + ) -> SimValue { + (SimValue::bits(&*lhs) == SimValue::bits(&*rhs)).to_sim_value() + } + + #[track_caller] + fn cmp_sim_value_ne( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>, + ) -> SimValue { + (SimValue::bits(&*lhs) != SimValue::bits(&*rhs)).to_sim_value() + } + + #[track_caller] + fn cmp_expr_eq(lhs: Expr, rhs: Expr) -> Expr { + lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits()) + } +} + +impl BTBEntryInsnKind { + #[hdl] + fn try_from_decoded_insn_kind(kind: &SimValue) -> Option> { + #[hdl(sim)] + match kind { + WipDecodedInsnKind::NonBranch => None, + WipDecodedInsnKind::Branch(_) + | WipDecodedInsnKind::BranchCond(_) + | WipDecodedInsnKind::IndirectBranch => Some( + #[hdl(sim)] + BTBEntryInsnKind::Branch(), + ), + WipDecodedInsnKind::Call(_) + | WipDecodedInsnKind::CallCond(_) + | WipDecodedInsnKind::IndirectCall => Some( + #[hdl(sim)] + BTBEntryInsnKind::Call(), + ), + WipDecodedInsnKind::Ret | WipDecodedInsnKind::RetCond => Some( + #[hdl(sim)] + BTBEntryInsnKind::Ret(), + ), + WipDecodedInsnKind::Interrupt(_) => None, + WipDecodedInsnKind::Unknown => None, + } + } +} + +#[hdl] +enum BTBEntryAddrKind { + Unconditional, + Indirect, + CondTaken, + CondNotTaken, +} + +// TODO: replace with #[hdl(cmp_eq)] when that's implemented for enums +impl HdlPartialEqImpl for BTBEntryAddrKind { + #[track_caller] + fn cmp_value_eq( + lhs: Self, + lhs_value: Cow<'_, Self::SimValue>, + rhs: Self, + rhs_value: Cow<'_, Self::SimValue>, + ) -> bool { + *Self::cmp_sim_value_eq( + Cow::Owned(SimValue::from_value(lhs, lhs_value.into_owned())), + Cow::Owned(SimValue::from_value(rhs, rhs_value.into_owned())), + ) + } + + #[track_caller] + fn cmp_sim_value_eq( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>, + ) -> SimValue { + (SimValue::bits(&*lhs) == SimValue::bits(&*rhs)).to_sim_value() + } + + #[track_caller] + fn cmp_sim_value_ne( + lhs: Cow<'_, SimValue>, + rhs: Cow<'_, SimValue>, + ) -> SimValue { + (SimValue::bits(&*lhs) != SimValue::bits(&*rhs)).to_sim_value() + } + + #[track_caller] + fn cmp_expr_eq(lhs: Expr, rhs: Expr) -> Expr { + lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits()) + } +} + +impl BTBEntryAddrKind { + #[hdl] + fn taken(this: &SimValue) -> bool { + #[hdl(sim)] + match this { + Self::Unconditional | Self::Indirect | Self::CondTaken => true, + Self::CondNotTaken => false, + } + } + /// `taken` is only called when choosing between [`Self::CondTaken`] and [`Self::CondNotTaken`] + #[hdl] + fn try_from_decoded_insn_kind( + kind: &SimValue, + taken: impl FnOnce() -> Option, + ) -> Option> { + let cond = || { + Some(if taken()? { + #[hdl(sim)] + Self::CondTaken() + } else { + #[hdl(sim)] + Self::CondNotTaken() + }) + }; + #[hdl(sim)] + match kind { + WipDecodedInsnKind::NonBranch => None, + WipDecodedInsnKind::Branch(_) + | WipDecodedInsnKind::Call(_) + | WipDecodedInsnKind::Ret => Some( + #[hdl(sim)] + Self::Unconditional(), + ), + WipDecodedInsnKind::BranchCond(_) + | WipDecodedInsnKind::CallCond(_) + | WipDecodedInsnKind::RetCond => cond(), + WipDecodedInsnKind::IndirectBranch | WipDecodedInsnKind::IndirectCall => Some( + #[hdl(sim)] + Self::Indirect(), + ), + WipDecodedInsnKind::Interrupt(_) => None, + WipDecodedInsnKind::Unknown => None, + } + } +} + +#[hdl(cmp_eq)] +struct BTBEntryWithoutStartPc { + target_pc: UInt<64>, + /// when branch is not taken, the next pc to fetch from is `start_pc + fallthrough_offset`. + /// needed because there may be more than one branch in a fetch block + fallthrough_offset: UInt<8>, + /// the pc to use for branch prediction is `start_pc + branch_offset` + branch_offset: UInt<8>, + /// when a call is made, the return address is `start_pc + after_call_offset` + after_call_offset: UInt<8>, + insn_kind: BTBEntryInsnKind, + addr_kind: BTBEntryAddrKind, +} + +#[hdl] +struct BTBEntry { + /// address of first instruction to run in this fetch block + start_pc: UInt<64>, + rest: BTBEntryWithoutStartPc, +} + +impl BTBEntry { + fn taken_pc(this: &SimValue) -> u64 { + this.rest.target_pc.as_int() + } + fn not_taken_start_pc(this: &SimValue) -> u64 { + Self::fallthrough_pc(this) + } + /// when branch is not taken, this returns the next pc to fetch from. + /// needed because there may be more than one branch in a fetch block + fn fallthrough_pc(this: &SimValue) -> u64 { + this.start_pc + .as_int() + .wrapping_add(this.rest.fallthrough_offset.as_int().into()) + } + /// the pc to use for branch prediction + fn branch_pc(this: &SimValue) -> u64 { + this.start_pc + .as_int() + .wrapping_add(this.rest.branch_offset.as_int().into()) + } + /// when a call is made, this gives the return address + fn after_call_pc(this: &SimValue) -> u64 { + this.start_pc + .as_int() + .wrapping_add(this.rest.after_call_offset.as_int().into()) + } +} + +#[hdl] +struct LFSR31 { + // MSB is always zero, 32 bits makes it easier to manipulate + state: UInt<32>, +} + +impl SimValueDefault for LFSR31 { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + Self { state: 1u32 } + } +} + +impl LFSR31 { + fn next(this: &mut SimValue) -> u32 { + let state = this.state.as_int(); + let state = if state == 0 { + 1u32 + } else { + // a maximal-length 31-bit LFSR + let lsb = ((state >> 30) ^ (state >> 27)) & 1; + let msb = (state << 1) & ((1 << 31) - 1); + lsb | msb + }; + *this.state = state.into(); + state + } +} + +#[hdl] +struct BranchTargetBuffer { + branch_pc_to_target_map: Array, { BranchTargetBuffer::SIZE }>, + next_index_to_replace_lfsr: LFSR31, +} + +impl BranchTargetBuffer { + const LOG2_SIZE: usize = 4; + const SIZE: usize = 1 << Self::LOG2_SIZE; + fn next_index_to_replace(this: &mut SimValue) -> usize { + LFSR31::next(&mut this.next_index_to_replace_lfsr) as usize % Self::SIZE + } +} + +impl SimValueDefault for BranchTargetBuffer { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + BranchTargetBuffer { + // something other than zero so you can see the values getting reset + branch_pc_to_target_map: [HdlSome( + #[hdl(sim)] + BTBEntry { + start_pc: !0u64, + rest: #[hdl(sim)] + BTBEntryWithoutStartPc { + target_pc: !0u64, + fallthrough_offset: !0u8, + branch_offset: !0u8, + after_call_offset: !0u8, + insn_kind: BTBEntryInsnKind.Call(), + addr_kind: BTBEntryAddrKind.CondNotTaken(), + }, + }, + ); Self::SIZE], + next_index_to_replace_lfsr: LFSR31.sim_value_default(), + } + } +} + +impl ResetSteps for BranchTargetBuffer { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let BranchTargetBuffer { + branch_pc_to_target_map, + next_index_to_replace_lfsr, + } = this; + *next_index_to_replace_lfsr = LFSR31.sim_value_default(); + ResetSteps::reset_step(branch_pc_to_target_map, step) + } +} + +#[hdl] +struct Queue { + data: ArrayType, + /// inclusive + head: UIntInRangeType, Capacity>, + /// exclusive + tail: UIntInRangeType, Capacity>, +} + +impl Queue { + fn capacity(self) -> usize { + self.data.len() + } + fn next_pos(self, pos: usize) -> usize { + assert_ne!(self.capacity(), 0); + (pos + 1) % self.capacity() + } + fn prev_pos(self, pos: usize) -> usize { + assert_ne!(self.capacity(), 0); + (pos + self.capacity() - 1) % self.capacity() + } + fn is_empty(this: &SimValue) -> bool { + this.head == this.tail + } + fn is_full(this: &SimValue) -> bool { + let head = *this.head; + let tail = *this.tail; + this.ty().next_pos(head) == tail + } + fn len(this: &SimValue) -> usize { + let capacity = this.ty().capacity(); + (*this.tail + capacity - *this.head) % capacity + } + fn space_left(this: &SimValue) -> usize { + this.ty().capacity() - Self::len(this) + } + fn clear(this: &mut SimValue) { + *this.head = 0; + *this.tail = 0; + } + fn try_push(this: &mut SimValue, value: impl ToSimValueWithType) -> Result<(), ()> { + if Self::is_full(this) { + Err(()) + } else { + let head = *this.head; + let head = this.ty().next_pos(head); + *this.head = head; + let data = &mut this.data[head]; + *data = value.to_sim_value_with_type(data.ty()); + Ok(()) + } + } + fn undo_push(this: &mut SimValue) -> Option> { + if Self::is_empty(this) { + None + } else { + let head = *this.head; + let data = this.data[head].clone(); + let head = this.ty().prev_pos(head); + *this.head = head; + Some(data) + } + } + fn peek(this: &SimValue) -> Option> { + if Self::is_empty(this) { + None + } else { + Some(this.data[*this.tail].clone()) + } + } + fn pop(this: &mut SimValue) -> Option> { + if Self::is_empty(this) { + None + } else { + let tail = *this.tail; + let data = this.data[tail].clone(); + *this.tail = this.ty().next_pos(tail); + Some(data) + } + } +} + +impl SimValueDefault for Queue { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { data, head, tail } = self; + #[hdl(sim)] + Queue:: { + data: repeat( + data.element().sim_value_default(), + Capacity::from_usize(data.len()), + ), + head: 0usize.to_sim_value_with_type(head), + tail: 0usize.to_sim_value_with_type(tail), + } + } +} + +impl ResetSteps for Queue { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Queue:: { data, head, tail } = this; + **head = 0; + **tail = 0; + ResetSteps::reset_step(data, step) + } +} + +#[hdl] +struct FetchQueueEntry { + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + btb_entry: HdlOption, + btb_entry_index: UIntInRange<0, { BranchTargetBuffer::SIZE }>, + next_pc: UInt<64>, +} + +impl SimValueDefault for FetchQueueEntry { + #[hdl] + fn sim_value_default(self) -> SimValue { + #[hdl(sim)] + FetchQueueEntry { + fetch_block_id: 0 as FetchBlockIdInt, + btb_entry: #[hdl(sim)] + HdlNone(), + btb_entry_index: 0usize.to_sim_value_with_type(FetchQueueEntry.btb_entry_index), + next_pc: 0u64, + } + } +} + +const BRANCH_PREDICTOR_LOG2_SIZE: usize = 8; +const BRANCH_PREDICTOR_SIZE: usize = 1 << BRANCH_PREDICTOR_LOG2_SIZE; + +#[hdl(no_static)] +struct CancelInProgress> { + cancel: Cancel, + br_pred_stage_inputs_to_cancel: UIntInRangeInclusive<0, 32>, + br_pred_stage_cancel: Bool, + fetch_decode_stage_inputs_to_cancel: + UIntInRangeInclusiveType, CpuConfigMaxFetchesInFlight>, + fetch_decode_stage_cancel: Bool, + post_decode_stage_inputs_to_cancel: UIntInRangeInclusive<0, 1>, + post_decode_stage_cancel: Bool, + post_decode_stage_outputs_to_cancel: + UIntInRangeInclusiveType, TwiceCpuConfigFetchWidth>, + rename_dispatch_execute_stage_inputs_to_cancel: UIntInRangeInclusive<0, 256>, + rename_dispatch_execute_stage_cancel: Bool, + retire_stage_inputs_to_cancel: UIntInRangeInclusive<0, 1>, + retire_stage_cancel: Bool, + config: C, +} + +impl CancelInProgress> { + #[hdl] + fn to_fetch_cancel_data( + this: &SimValue, + ) -> SimValue< + HdlOption< + UIntInRangeInclusiveType, CpuConfigMaxFetchesInFlight>>, + >, + > { + let NextPcStateOutputs { + to_fetch_cancel_data, + .. + } = NextPcStateOutputs[this.config.ty()]; + if *this.fetch_decode_stage_inputs_to_cancel > 0 { + #[hdl(sim)] + to_fetch_cancel_data.HdlSome(*this.fetch_decode_stage_inputs_to_cancel) + } else { + #[hdl(sim)] + to_fetch_cancel_data.HdlNone() + } + } +} + +#[hdl(no_static)] +pub struct StatesAndQueues> { + next_pc_stage_state: NextPcStageState, + br_pred_stage_inputs: Queue, ConstUsize<32>>, + br_pred_stage_state: BrPredStageState, + fetch_decode_stage_inputs: Queue, CpuConfigMaxFetchesInFlight>, + fetch_decode_stage_state: FetchDecodeStageState, + post_decode_stage_inputs: Queue, ConstUsize<1>>, + post_decode_stage_state: PostDecodeStageState, + post_decode_stage_outputs: Queue, CpuConfigFetchWidth>, + rename_dispatch_execute_stage_inputs: Queue, ConstUsize<256>>, + rename_dispatch_execute_stage_state: RenameDispatchExecuteStageState, + retire_stage_inputs: Queue, ConstUsize<1>>, + retire_stage_state: RetireStageState, + config: C, +} + +impl SimValueDefault for StatesAndQueues> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + next_pc_stage_state, + br_pred_stage_inputs, + br_pred_stage_state, + fetch_decode_stage_inputs, + fetch_decode_stage_state, + post_decode_stage_inputs, + post_decode_stage_state, + post_decode_stage_outputs, + rename_dispatch_execute_stage_inputs, + rename_dispatch_execute_stage_state, + retire_stage_inputs, + retire_stage_state, + config, + } = self; + #[hdl(sim)] + Self { + next_pc_stage_state: next_pc_stage_state.sim_value_default(), + br_pred_stage_inputs: br_pred_stage_inputs.sim_value_default(), + br_pred_stage_state: br_pred_stage_state.sim_value_default(), + fetch_decode_stage_inputs: fetch_decode_stage_inputs.sim_value_default(), + fetch_decode_stage_state: fetch_decode_stage_state.sim_value_default(), + post_decode_stage_inputs: post_decode_stage_inputs.sim_value_default(), + post_decode_stage_state: post_decode_stage_state.sim_value_default(), + post_decode_stage_outputs: post_decode_stage_outputs.sim_value_default(), + rename_dispatch_execute_stage_inputs: rename_dispatch_execute_stage_inputs + .sim_value_default(), + rename_dispatch_execute_stage_state: rename_dispatch_execute_stage_state + .sim_value_default(), + retire_stage_inputs: retire_stage_inputs.sim_value_default(), + retire_stage_state: retire_stage_state.sim_value_default(), + config, + } + } +} + +impl ResetSteps for StatesAndQueues> { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + next_pc_stage_state, + br_pred_stage_inputs, + br_pred_stage_state, + fetch_decode_stage_inputs, + fetch_decode_stage_state, + post_decode_stage_inputs, + post_decode_stage_state, + post_decode_stage_outputs, + rename_dispatch_execute_stage_inputs, + rename_dispatch_execute_stage_state, + retire_stage_inputs, + retire_stage_state, + config: _, + } = this; + let next_pc_stage_state = ResetSteps::reset_step(next_pc_stage_state, step); + let br_pred_stage_inputs = ResetSteps::reset_step(br_pred_stage_inputs, step); + let br_pred_stage_state = ResetSteps::reset_step(br_pred_stage_state, step); + let fetch_decode_stage_inputs = ResetSteps::reset_step(fetch_decode_stage_inputs, step); + let fetch_decode_stage_state = ResetSteps::reset_step(fetch_decode_stage_state, step); + let post_decode_stage_inputs = ResetSteps::reset_step(post_decode_stage_inputs, step); + let post_decode_stage_state = ResetSteps::reset_step(post_decode_stage_state, step); + let post_decode_stage_outputs = ResetSteps::reset_step(post_decode_stage_outputs, step); + let rename_dispatch_execute_stage_inputs = + ResetSteps::reset_step(rename_dispatch_execute_stage_inputs, step); + let rename_dispatch_execute_stage_state = + ResetSteps::reset_step(rename_dispatch_execute_stage_state, step); + let retire_stage_inputs = ResetSteps::reset_step(retire_stage_inputs, step); + let retire_stage_state = ResetSteps::reset_step(retire_stage_state, step); + next_pc_stage_state + .and(br_pred_stage_inputs) + .and(br_pred_stage_state) + .and(fetch_decode_stage_inputs) + .and(fetch_decode_stage_state) + .and(post_decode_stage_inputs) + .and(post_decode_stage_state) + .and(post_decode_stage_outputs) + .and(rename_dispatch_execute_stage_inputs) + .and(rename_dispatch_execute_stage_state) + .and(retire_stage_inputs) + .and(retire_stage_state) + } +} + +impl StatesAndQueues> { + #[hdl] + fn step_no_cancel( + this: &mut SimValue, + inputs: SimValue>>, + ) -> SimValue>>> { + #[hdl(sim)] + let NextPcStateStepInputs::<_> { + to_fetch_fetch_triggered, + to_fetch_cancel_triggered, + from_decode_inner_triggered, + post_decode_output_insns_triggered, + from_retire_inner_triggered, + } = inputs; + assert!(!*to_fetch_cancel_triggered); + #[hdl(sim)] + let Self { + next_pc_stage_state, + br_pred_stage_inputs, + br_pred_stage_state, + fetch_decode_stage_inputs, + fetch_decode_stage_state, + post_decode_stage_inputs, + post_decode_stage_state, + post_decode_stage_outputs, + rename_dispatch_execute_stage_inputs, + rename_dispatch_execute_stage_state, + retire_stage_inputs, + retire_stage_state, + config, + } = this; + let config = config.ty(); + let retval_ty = HdlOption[CancelInProgress[config]]; + let mut retval = #[hdl(sim)] + retval_ty.HdlNone(); + if Queue::capacity(br_pred_stage_inputs) - Queue::len(br_pred_stage_inputs) + #[hdl(sim)] + let StageOutput::<_, _, _> { outputs, cancel } = + Stage::run(next_pc_stage_state, &().to_sim_value()); + + retval + } + #[hdl] + fn step_cancel( + this: &mut SimValue, + cancel_opt: &mut SimValue>>>, + inputs: SimValue>>, + ) { + #[hdl(sim)] + let NextPcStateStepInputs::<_> { + to_fetch_fetch_triggered, + to_fetch_cancel_triggered, + from_decode_inner_triggered, + post_decode_output_insns_triggered, + from_retire_inner_triggered, + } = inputs; + assert!(!*to_fetch_fetch_triggered); + #[hdl(sim)] + if let HdlSome(_) = from_decode_inner_triggered { + unreachable!(); + } + assert_eq!(**ArrayVec::len_sim(&post_decode_output_insns_triggered), 0); + #[hdl(sim)] + if let HdlSome(_) = from_retire_inner_triggered { + unreachable!(); + } + #[hdl(sim)] + let Self { + next_pc_stage_state, + br_pred_stage_inputs, + br_pred_stage_state, + fetch_decode_stage_inputs, + fetch_decode_stage_state, + post_decode_stage_inputs, + post_decode_stage_state, + post_decode_stage_outputs, + rename_dispatch_execute_stage_inputs, + rename_dispatch_execute_stage_state, + retire_stage_inputs, + retire_stage_state, + config: _, + } = this; + let cancel = #[hdl(sim)] + match &mut *cancel_opt { + HdlSome(cancel) => cancel, + HdlNone => unreachable!(), + }; + #[hdl(sim)] + if let HdlSome(_) = CancelInProgress::to_fetch_cancel_data(cancel) { + if !*to_fetch_cancel_triggered { + return; + } + } + #[hdl(sim)] + let CancelInProgress::<_> { + cancel, + br_pred_stage_inputs_to_cancel, + br_pred_stage_cancel, + fetch_decode_stage_inputs_to_cancel, + fetch_decode_stage_cancel, + post_decode_stage_inputs_to_cancel, + post_decode_stage_cancel, + post_decode_stage_outputs_to_cancel, + rename_dispatch_execute_stage_inputs_to_cancel, + rename_dispatch_execute_stage_cancel, + retire_stage_inputs_to_cancel, + retire_stage_cancel, + config: _, + } = cancel; + Stage::cancel(next_pc_stage_state, cancel); + for _ in 0..**br_pred_stage_inputs_to_cancel { + Queue::undo_push(br_pred_stage_inputs).expect("known to be non-empty"); + } + if **br_pred_stage_cancel { + Stage::cancel(br_pred_stage_state, cancel); + } + for _ in 0..**fetch_decode_stage_inputs_to_cancel { + Queue::undo_push(fetch_decode_stage_inputs).expect("known to be non-empty"); + } + if **fetch_decode_stage_cancel { + Stage::cancel(fetch_decode_stage_state, cancel); + } + for _ in 0..**post_decode_stage_inputs_to_cancel { + Queue::undo_push(post_decode_stage_inputs).expect("known to be non-empty"); + } + if **post_decode_stage_cancel { + Stage::cancel(post_decode_stage_state, cancel); + } + for _ in 0..**post_decode_stage_outputs_to_cancel { + Queue::undo_push(post_decode_stage_outputs).expect("known to be non-empty"); + } + for _ in 0..**rename_dispatch_execute_stage_inputs_to_cancel { + Queue::undo_push(rename_dispatch_execute_stage_inputs).expect("known to be non-empty"); + } + if **rename_dispatch_execute_stage_cancel { + Stage::cancel(rename_dispatch_execute_stage_state, cancel); + } + for _ in 0..**retire_stage_inputs_to_cancel { + Queue::undo_push(retire_stage_inputs).expect("known to be non-empty"); + } + if **retire_stage_cancel { + Stage::cancel(retire_stage_state, cancel); + } + *cancel_opt = #[hdl(sim)] + (cancel_opt.ty()).HdlNone(); + } +} + +#[hdl(no_static)] +pub struct NextPcState> { + states_and_queues: StatesAndQueues, + cancel: HdlOption>, +} + +impl SimValueDefault for NextPcState> { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + states_and_queues, + cancel, + } = self; + #[hdl(sim)] + Self { + states_and_queues: states_and_queues.sim_value_default(), + cancel: cancel.sim_value_default(), + } + } +} + +impl ResetSteps for NextPcState> { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + states_and_queues, + cancel, + } = this; + *cancel = #[hdl(sim)] + (cancel.ty()).HdlNone(); + ResetSteps::reset_step(states_and_queues, step) + } +} + +#[hdl(no_static)] +struct NextPcStateOutputs> { + to_fetch_fetch_data: HdlOption, + to_fetch_cancel_data: + HdlOption, CpuConfigMaxFetchesInFlight>>, + from_decode_inner_ready: Bool, + post_decode_output_insns: ArrayVec>, + from_retire_inner_ready: Bool, + config: C, +} + +#[hdl(no_static)] +struct NextPcStateStepInputs> { + to_fetch_fetch_triggered: Bool, + to_fetch_cancel_triggered: Bool, + from_decode_inner_triggered: HdlOption>, + post_decode_output_insns_triggered: ArrayVec>, + from_retire_inner_triggered: HdlOption>, +} + +impl NextPcState> { + #[hdl] + fn outputs(this: &SimValue) -> SimValue>> { + #[hdl(sim)] + let Self { + states_and_queues, + cancel, + } = this; + #[hdl(sim)] + let StatesAndQueues::<_> { + next_pc_stage_state: _, + br_pred_stage_inputs: _, + br_pred_stage_state: _, + fetch_decode_stage_inputs, + fetch_decode_stage_state: _, + post_decode_stage_inputs, + post_decode_stage_state: _, + post_decode_stage_outputs, + rename_dispatch_execute_stage_inputs: _, + rename_dispatch_execute_stage_state: _, + retire_stage_inputs, + retire_stage_state: _, + config, + } = states_and_queues; + let config = config.ty(); + let NextPcStateOutputs { + to_fetch_fetch_data: _, + to_fetch_cancel_data: to_fetch_cancel_data_ty, + from_decode_inner_ready: _, + post_decode_output_insns: post_decode_output_insns_ty, + from_retire_inner_ready: _, + config: _, + } = NextPcStateOutputs[config]; + #[hdl(sim)] + if let HdlSome(cancel) = cancel { + #[hdl(sim)] + NextPcStateOutputs::<_> { + to_fetch_fetch_data: #[hdl(sim)] + HdlNone(), + to_fetch_cancel_data: CancelInProgress::to_fetch_cancel_data(cancel), + from_decode_inner_ready: false, + post_decode_output_insns: post_decode_output_insns_ty.sim_value_default(), + from_retire_inner_ready: false, + config, + } + } else { + let to_fetch_fetch_data = if let Some(data) = Queue::peek(fetch_decode_stage_inputs) { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + NextPcToFetchInterfaceInner { + start_pc: data.start_pc, + fetch_block_id: data.fetch_block_id, + }, + ) + } else { + #[hdl(sim)] + HdlNone() + }; + let mut post_decode_output_insns = + post_decode_output_insns_ty.new_sim(WipDecodedInsn.sim_value_default()); + let mut post_decode_stage_outputs = post_decode_stage_outputs.clone(); + while let Some(post_decode_stage_output) = Queue::pop(&mut post_decode_stage_outputs) { + #[hdl(sim)] + let PostDecodeStageOutput::<_> { + insn, + next_pc: _, + btb_entry_index: _, + start_branch_history: _, + start_call_stack: _, + branch_predictor_index: _, + config: _, + } = post_decode_stage_output; + ArrayVec::try_push_sim(&mut post_decode_output_insns, insn).expect("known to fit"); + } + #[hdl(sim)] + NextPcStateOutputs::<_> { + to_fetch_fetch_data, + to_fetch_cancel_data: to_fetch_cancel_data_ty.HdlNone(), + from_decode_inner_ready: !Queue::is_full(post_decode_stage_inputs), + post_decode_output_insns, + from_retire_inner_ready: !Queue::is_full(retire_stage_inputs), + config, + } + } + } + #[hdl] + fn step( + this: &mut SimValue, + inputs: SimValue>>, + ) { + #[hdl(sim)] + let Self { + states_and_queues, + cancel, + } = this; + #[hdl(sim)] + if let HdlSome(_) = &cancel { + StatesAndQueues::step_cancel(states_and_queues, cancel, inputs); + } else { + *cancel = StatesAndQueues::step_no_cancel(states_and_queues, inputs); + } + } +} + +#[hdl_module(extern)] +pub fn next_pc(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let to_fetch: NextPcToFetchInterface> = + m.output(NextPcToFetchInterface[config]); + #[hdl] + let from_decode: DecodeToPostDecodeInterface> = + m.input(DecodeToPostDecodeInterface[config]); + #[hdl] + let post_decode_output: PostDecodeOutputInterface> = + m.input(PostDecodeOutputInterface[config]); + #[hdl] + let from_retire: RetireToNextPcInterface> = + m.input(RetireToNextPcInterface[config]); + #[hdl] + let state_for_debug: NextPcState> = m.output(NextPcState[config]); + m.register_clock_for_past(cd.clk); + #[hdl] + async fn run( + mut sim: ExternModuleSimulationState, + cd: Expr, + to_fetch: Expr>>, + from_decode: Expr>>, + post_decode_output: Expr>>, + from_retire: Expr>>, + state_expr: Expr>>, + ) { + let mut state = sim.read(state_expr).await; + for step in 0usize.. { + sim.write(state_expr, state).await; + sim.wait_for_clock_edge(cd.clk).await; + state = sim.read_past(state_expr, cd.clk).await; + let reset_status = ResetSteps::reset_step(&mut state, step); + match reset_status { + ResetStatus::Done => break, + ResetStatus::Working => {} + } + } + loop { + #[hdl(sim)] + let NextPcStateOutputs::<_> { + to_fetch_fetch_data, + to_fetch_cancel_data, + from_decode_inner_ready, + post_decode_output_insns, + from_retire_inner_ready, + config: _, + } = NextPcState::outputs(&state); + sim.write(to_fetch.fetch.data, to_fetch_fetch_data).await; + sim.write(to_fetch.cancel.data, to_fetch_cancel_data).await; + sim.write(from_decode.inner.ready, from_decode_inner_ready) + .await; + sim.write(post_decode_output.insns, post_decode_output_insns) + .await; + sim.write(from_retire.inner.ready, from_retire_inner_ready) + .await; + sim.write(state_expr, state).await; + sim.wait_for_clock_edge(cd.clk).await; + state = sim.read_past(state_expr, cd.clk).await; + let to_fetch_fetch_triggered = + #[hdl(sim)] + if let HdlSome(_) = sim.read_past(to_fetch.fetch.data, cd.clk).await { + *sim.read_past(to_fetch.fetch.ready, cd.clk).await + } else { + false + }; + let to_fetch_cancel_triggered = + #[hdl(sim)] + if let HdlSome(_) = sim.read_past(to_fetch.cancel.data, cd.clk).await { + *sim.read_past(to_fetch.cancel.ready, cd.clk).await + } else { + false + }; + let from_decode_inner_triggered = + if *sim.read_past(from_decode.inner.ready, cd.clk).await { + sim.read_past(from_decode.inner.data, cd.clk).await + } else { + #[hdl(sim)] + (from_decode.ty().inner.data).HdlNone() + }; + let mut post_decode_output_insns_triggered = + sim.read_past(post_decode_output.insns, cd.clk).await; + ArrayVec::truncate_sim( + &mut post_decode_output_insns_triggered, + *sim.read_past(post_decode_output.ready, cd.clk).await, + ); + let from_retire_inner_triggered = + if *sim.read_past(from_retire.inner.ready, cd.clk).await { + sim.read_past(from_retire.inner.data, cd.clk).await + } else { + #[hdl(sim)] + (from_retire.ty().inner.data).HdlNone() + }; + NextPcState::step( + &mut state, + #[hdl(sim)] + NextPcStateStepInputs::<_> { + to_fetch_fetch_triggered, + to_fetch_cancel_triggered, + from_decode_inner_triggered, + post_decode_output_insns_triggered, + from_retire_inner_triggered, + }, + ); + } + } + m.extern_module_simulation_fn( + ( + cd, + to_fetch, + from_decode, + post_decode_output, + from_retire, + state_for_debug, + ), + |args, mut sim| async move { + let (cd, to_fetch, from_decode, post_decode_output, from_retire, state_for_debug) = + args; + sim.write(state_for_debug, state_for_debug.ty().sim_value_default()) + .await; + sim.resettable( + cd, + |mut sim: ExternModuleSimulationState| async move { + sim.write(to_fetch.fetch.data, HdlNone()).await; + sim.write(to_fetch.cancel.data, to_fetch.ty().cancel.data.HdlNone()) + .await; + sim.write(from_decode.inner.ready, false).await; + sim.write( + post_decode_output.insns, + post_decode_output + .ty() + .insns + .new_sim(SimValueDefault::sim_value_default(StaticType::TYPE)), + ) + .await; + sim.write(from_retire.inner.ready, false).await; + }, + |sim, ()| { + run( + sim, + cd, + to_fetch, + from_decode, + post_decode_output, + from_retire, + state_for_debug, + ) + }, + ) + .await; + }, + ); +} diff --git a/crates/cpu/src/next_pc/next_pc.mermaid b/crates/cpu/src/next_pc/next_pc.mermaid new file mode 100644 index 0000000..05ac31c --- /dev/null +++ b/crates/cpu/src/next_pc/next_pc.mermaid @@ -0,0 +1,25 @@ +stateDiagram-v2 + direction LR + + state "Next PC" as next_pc + [*] --> next_pc + + state "Fetch/Decode" as fetch_decode + next_pc --> fetch_decode + + state "Branch Predictor" as br_pred + next_pc --> br_pred + br_pred --> next_pc: cancel following + + state "Post-decode" as post_decode + fetch_decode --> post_decode + br_pred --> post_decode + post_decode --> next_pc: cancel following + + state "Rename\nDispatch\nExecute" as execute + post_decode --> execute + + state "Retire" as retire + execute --> retire + retire --> [*] + retire --> next_pc: cancel following \ No newline at end of file diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs index 6b3a6d5..13fc8b3 100644 --- a/crates/cpu/src/reg_alloc.rs +++ b/crates/cpu/src/reg_alloc.rs @@ -241,7 +241,7 @@ pub fn reg_alloc(config: &CpuConfig) { // TODO: finish connect( rob.renamed_insns_in[fetch_index].data, - Expr::ty(rob).renamed_insns_in.element().data.HdlNone(), + rob.ty().renamed_insns_in.element().data.HdlNone(), ); // TODO: finish connect( @@ -263,7 +263,7 @@ pub fn reg_alloc(config: &CpuConfig) { ); connect( renamed_mops[fetch_index], - Expr::ty(renamed_mops).element().HdlNone(), + renamed_mops.ty().element().HdlNone(), ); #[hdl] struct RenameTableReadPort { @@ -332,7 +332,7 @@ pub fn reg_alloc(config: &CpuConfig) { let write_port = wire_with_loc( &format!("{table_name}_{fetch_index}_{}", reg_kind.reg_name()), SourceLocation::caller(), - Expr::ty(write_port_), + write_port_.ty(), ); connect(write_port_, write_port); write_ports.push_back(write_port); @@ -343,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) { addr: 0_hdl_u0, en: false, clk: cd.clk, - data: Expr::ty(write_port.data).uninit(), + data: write_port.data.ty().uninit(), mask: splat_mask(config.p_reg_num(), true.to_expr()), }, ); @@ -375,7 +375,7 @@ pub fn reg_alloc(config: &CpuConfig) { config.renamed_mop_in_unit().TransformedMove, |renamed_mop, renamed_move_op: Expr>| { // TODO: finish handling MoveRegMOp - connect(renamed_mop, Expr::ty(renamed_mop).HdlNone()); + connect(renamed_mop, renamed_mop.ty().HdlNone()); }, ); connect( @@ -429,7 +429,7 @@ pub fn reg_alloc(config: &CpuConfig) { ); connect( selected_unit_index_leaf, - Expr::ty(selected_unit_index_leaf).HdlNone(), + selected_unit_index_leaf.ty().HdlNone(), ); let unit_index_wire = wire_with_loc( &format!("unit_index_{fetch_index}_{unit_index}"), @@ -447,7 +447,7 @@ pub fn reg_alloc(config: &CpuConfig) { let selected_unit_index_node = wire_with_loc( &format!("selected_unit_index_node_{fetch_index}_{state}"), SourceLocation::caller(), - Expr::ty(l), + l.ty(), ); *state += 1; connect(selected_unit_index_node, l); @@ -516,7 +516,7 @@ pub fn reg_alloc(config: &CpuConfig) { connect(unit_free_regs_tracker.alloc_out[0].ready, false); connect( unit_to_reg_alloc.input.data, - Expr::ty(unit_to_reg_alloc.input).data.HdlNone(), + unit_to_reg_alloc.input.ty().data.HdlNone(), ); for fetch_index in 0..config.fetch_width.get() { #[hdl] @@ -550,7 +550,7 @@ pub fn reg_alloc(config: &CpuConfig) { } else { connect( unit_to_reg_alloc.input.data, - HdlSome(Expr::ty(unit_to_reg_alloc.input).data.HdlSome.uninit()), + HdlSome(unit_to_reg_alloc.input.ty().data.HdlSome.uninit()), ); // FIXME: add hdl_assert(cd.clk, false.to_expr(), ""); } @@ -578,7 +578,8 @@ pub fn reg_alloc(config: &CpuConfig) { connect(unit_to_reg_alloc.unit_forwarding_info, unit_forwarding_info); connect( unit_forwarding_info.unit_output_writes[unit_index], - Expr::ty(unit_forwarding_info) + unit_forwarding_info + .ty() .unit_output_writes .element() .HdlNone(), diff --git a/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs b/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs index a7bf687..f1517c1 100644 --- a/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs +++ b/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs @@ -73,7 +73,7 @@ pub fn unit_free_regs_tracker( let reduced_alloc_nums = wire_with_loc( &format!("reduced_alloc_nums_{}_{}", range.start, range.end), SourceLocation::caller(), - Array[UInt[Expr::ty(l.alloc_nums).element().width() + 1]][alloc_at_once.get()], + Array[UInt[l.alloc_nums.ty().element().width() + 1]][alloc_at_once.get()], ); for alloc_index in 0..alloc_at_once.get() { #[hdl] @@ -195,7 +195,7 @@ mod tests { } } #[hdl] - let free_before_alloc_array = wire(Array[Expr::ty(free_reg)][alloc_at_once.get() + 1]); + let free_before_alloc_array = wire(Array[free_reg.ty()][alloc_at_once.get() + 1]); connect(free_before_alloc_array[0], free_reg); #[hdl] let expected_alloc = wire(Array[HdlOption[reg_num_ty]][alloc_at_once.get()]); diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index d6cd1d6..8db75c2 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -15,6 +15,7 @@ use fayalite::{ intern::{Intern, Interned}, prelude::*, }; +use serde::{Deserialize, Serialize}; pub mod alu_branch; pub mod unit_base; @@ -36,7 +37,7 @@ macro_rules! all_units { } ) => { $(#[$enum_meta])* - #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug, Serialize, Deserialize)] $vis enum $UnitKind { $( $(#[$variant_meta])* @@ -52,9 +53,16 @@ macro_rules! all_units { } } - impl ToExpr for $UnitKind { + impl ValueType for $UnitKind { type Type = $HdlUnitKind; + type ValueCategory = fayalite::expr::value_category::ValueCategoryExpr; + fn ty(&self) -> Self::Type { + $HdlUnitKind + } + } + + impl ToExpr for $UnitKind { fn to_expr(&self) -> Expr { match self { $($UnitKind::$Unit => $HdlUnitKind.$Unit(),)* @@ -98,7 +106,7 @@ macro_rules! all_units { #[hdl] $vis fn $extract(expr: impl ToExpr) -> Expr> { let expr = expr.to_expr(); - let ty = Expr::ty(expr); + let ty = expr.ty(); #[hdl] let $extract = wire(HdlOption[ty.$Unit]); connect($extract, HdlOption[ty.$Unit].HdlNone()); @@ -164,10 +172,10 @@ macro_rules! all_units { $TransformedMoveOp: MOpTrait, { let this = this.to_expr(); - let new_ty = Expr::ty(this).with_transformed_move_op_ty(new_transformed_move_op_ty); + let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty); #[hdl] let with_transformed_move_op = wire(HdlOption[new_ty]); - connect(with_transformed_move_op, Expr::ty(with_transformed_move_op).HdlNone()); + connect(with_transformed_move_op, with_transformed_move_op.ty().HdlNone()); // workaround #[hdl] match expanding to a loop, so you can't move variables in it let mut connect_transformed_move_op = Some(connect_transformed_move_op); #[hdl] @@ -209,7 +217,7 @@ macro_rules! all_units { RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)] } fn mop_into(this: Expr) -> Expr> { - MOpInto::>::mop_into_ty(Expr::ty(this)).$BeforeUnit(this) + MOpInto::>::mop_into_ty(this.ty()).$BeforeUnit(this) } })* @@ -218,7 +226,7 @@ macro_rules! all_units { RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)] } fn mop_into(this: Expr) -> Expr> { - MOpInto::>::mop_into_ty(Expr::ty(this)).$AfterUnit(this) + MOpInto::>::mop_into_ty(this.ty()).$AfterUnit(this) } })* }; diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs index 49908fc..8f20592 100644 --- a/crates/cpu/src/unit/alu_branch.rs +++ b/crates/cpu/src/unit/alu_branch.rs @@ -266,16 +266,13 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) { let unit_base = instance(unit_base( config, unit_index, - Expr::ty(unit_to_reg_alloc).input.data.HdlSome.mop, + unit_to_reg_alloc.ty().input.data.HdlSome.mop, (), )); connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc); connect(unit_base.cd, cd); connect(unit_base.execute_start.ready, true); - connect( - unit_base.execute_end, - Expr::ty(unit_base.execute_end).HdlNone(), - ); + connect(unit_base.execute_end, unit_base.execute_end.ty().HdlNone()); #[hdl] if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) { #[hdl] diff --git a/crates/cpu/src/unit/unit_base.rs b/crates/cpu/src/unit/unit_base.rs index 0803933..4e665e0 100644 --- a/crates/cpu/src/unit/unit_base.rs +++ b/crates/cpu/src/unit/unit_base.rs @@ -227,7 +227,7 @@ impl InFlightOpsSummary { in_flight_ops: impl ToExpr>, MaxInFlight>>, ) -> Expr { let in_flight_ops = in_flight_ops.to_expr(); - let max_in_flight = Expr::ty(in_flight_ops).len(); + let max_in_flight = in_flight_ops.ty().len(); let index_range = 0..max_in_flight; let index_ty = UInt::range(index_range.clone()); tree_reduce( @@ -259,7 +259,7 @@ pub fn unit_base< let execute_end: HdlOption> = m.input(HdlOption[ExecuteEnd[config.out_reg_num_width][extra_out_ty]]); - connect(execute_start.data, Expr::ty(execute_start).data.HdlNone()); + connect(execute_start.data, execute_start.ty().data.HdlNone()); let max_in_flight = config.unit_max_in_flight(unit_index).get(); let in_flight_op_ty = InFlightOp[mop_ty]; @@ -270,7 +270,7 @@ pub fn unit_base< let in_flight_ops_summary_value = InFlightOpsSummary::summarize(in_flight_ops); #[hdl] - let in_flight_ops_summary = wire(Expr::ty(in_flight_ops_summary_value)); + let in_flight_ops_summary = wire(in_flight_ops_summary_value.ty()); connect(in_flight_ops_summary, in_flight_ops_summary_value); connect( @@ -302,7 +302,7 @@ pub fn unit_base< #[hdl] let input_src_regs_valid = wire(); connect(input_src_regs_valid, [true; COMMON_MOP_SRC_LEN]); - let mut unit_output_regs_valid: Vec> = (0..Expr::ty(unit_output_writes).len()) + let mut unit_output_regs_valid: Vec> = (0..unit_output_writes.ty().len()) .map(|unit_index| { let mut mem = memory_with_loc( &format!("unit_{unit_index}_output_regs_valid"), @@ -313,7 +313,7 @@ pub fn unit_base< mem }) .collect(); - for unit_index in 0..Expr::ty(unit_output_writes).len() { + for unit_index in 0..unit_output_writes.ty().len() { let mut unit_output_regs = memory_with_loc( &format!("unit_{unit_index}_output_regs"), PRegValue, @@ -411,7 +411,7 @@ pub fn unit_base< connect( unit_to_reg_alloc.output, - Expr::ty(unit_to_reg_alloc.output).HdlNone(), + unit_to_reg_alloc.output.ty().HdlNone(), ); #[hdl] @@ -503,7 +503,7 @@ pub fn unit_base< #[hdl] if in_flight_ops_summary.ready_op_index.cmp_eq(HdlSome( - in_flight_op_index.cast_to(Expr::ty(in_flight_ops_summary).ready_op_index.HdlSome), + in_flight_op_index.cast_to(in_flight_ops_summary.ty().ready_op_index.HdlSome), )) { connect(read_src_regs, src_regs); } @@ -512,7 +512,7 @@ pub fn unit_base< in_flight_op_next_src_ready_flags[in_flight_op_index], src_ready_flags, ); - for unit_index in 0..Expr::ty(unit_output_writes).len() { + for unit_index in 0..unit_output_writes.ty().len() { #[hdl] if let HdlSome(unit_output_write) = unit_output_writes[unit_index] { #[hdl] diff --git a/crates/cpu/src/util/array_vec.rs b/crates/cpu/src/util/array_vec.rs index 4af5663..0f6fc6f 100644 --- a/crates/cpu/src/util/array_vec.rs +++ b/crates/cpu/src/util/array_vec.rs @@ -22,6 +22,30 @@ impl ArrayVec { len: 0u8.cast_to(self.len), } } + #[hdl] + pub fn new_sim(self, uninit_element: impl ToSimValueWithType) -> SimValue { + let uninit_element = uninit_element.into_sim_value_with_type(self.element()); + #[hdl(sim)] + ArrayVec::<_, _> { + elements: SimValue::from_array_elements( + self.elements, + (0..self.elements.len()).map(|_| uninit_element.clone()), + ), + len: 0u8.cast_to(self.len), + } + } + #[hdl] + pub fn new_full_sim( + self, + elements: impl ToSimValueWithType>, + ) -> SimValue { + let elements = elements.to_sim_value_with_type(self.elements); + #[hdl(sim)] + Self { + elements, + len: self.elements.len().to_sim_value_with_type(self.len), + } + } pub fn element(self) -> T { self.elements.element() } @@ -39,8 +63,8 @@ impl ArrayVec { let elements = elements.to_expr(); let len = len.to_expr(); assert_eq!( - Length[N::from_usize(Expr::ty(elements).len())], - Expr::ty(len), + Length[N::from_usize(elements.ty().len())], + len.ty(), "len type mismatch", ); #[hdl] @@ -52,6 +76,9 @@ impl ArrayVec { pub fn len(this: impl ToExpr) -> Expr> { this.to_expr().len } + pub fn len_sim(this: &SimValue) -> &SimValue> { + &this.len + } pub fn is_empty(this: impl ToExpr) -> Expr { let len = Self::len(this); len.cmp_eq(0u8) @@ -75,6 +102,72 @@ impl ArrayVec { } } } + pub fn elements_sim_ref(this: &SimValue) -> &[SimValue] { + &this.elements[..*this.len] + } + pub fn elements_sim_mut(this: &mut SimValue) -> &mut [SimValue] { + let len = *this.len; + &mut this.elements[..len] + } + #[hdl] + pub async fn async_for_each_sim( + this: impl ToSimValue, + mut f: impl AsyncFnMut(usize, SimValue), + ) { + #[hdl(sim)] + let ArrayVec::<_, _> { elements, len } = this.into_sim_value(); + for (index, element) in elements.into_iter().enumerate() { + if index.cmp_lt(*len) { + f(index, element).await; + } + } + } + #[hdl] + pub async fn async_for_each_sim_ref<'a>( + this: &'a SimValue, + mut f: impl AsyncFnMut(usize, &'a SimValue), + ) { + #[hdl(sim)] + let ArrayVec::<_, _> { elements, len } = this; + for (index, element) in elements.iter().enumerate() { + if index.cmp_lt(**len) { + f(index, element).await; + } + } + } + #[hdl] + pub async fn async_for_each_sim_mut<'a>( + this: &'a mut SimValue, + mut f: impl AsyncFnMut(usize, &'a mut SimValue), + ) { + #[hdl(sim)] + let ArrayVec::<_, _> { elements, len } = this; + for (index, element) in elements.iter_mut().enumerate() { + if index.cmp_lt(**len) { + f(index, element).await; + } + } + } + #[hdl] + pub fn try_push_sim( + this: &mut SimValue, + value: impl ToSimValueWithType, + ) -> Result<(), SimValue> { + let value = value.into_sim_value_with_type(this.ty().element()); + let capacity = this.ty().capacity(); + #[hdl(sim)] + let ArrayVec::<_, _> { elements, len } = this; + if **len < capacity { + elements[**len] = value; + **len += 1; + Ok(()) + } else { + Err(value) + } + } + pub fn truncate_sim(this: &mut SimValue, len: usize) { + *this.len = len.min(*this.len); + } pub fn mapped_ty(self, new_element_ty: U) -> ArrayVec { ArrayVec { elements: ArrayType[new_element_ty][N::from_usize(self.elements.len())], @@ -89,7 +182,7 @@ impl ArrayVec { ) -> Expr> { let this = this.to_expr(); #[hdl] - let mapped_array_vec = wire(Expr::ty(this).mapped_ty(new_element_ty)); + let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty)); connect(mapped_array_vec.len, this.len); Self::for_each(this, |index, element| { connect(mapped_array_vec[index], f(index, element)); @@ -100,12 +193,10 @@ impl ArrayVec { pub fn as_array_of_options(this: impl ToExpr) -> Expr, N>> { let this = this.to_expr(); #[hdl] - let array_vec_as_array_of_options = wire( - ArrayType[HdlOption[Expr::ty(this).element()]] - [N::from_usize(Expr::ty(this).capacity())], - ); + let array_vec_as_array_of_options = + wire(ArrayType[HdlOption[this.ty().element()]][N::from_usize(this.ty().capacity())]); for element in array_vec_as_array_of_options { - connect(element, Expr::ty(element).HdlNone()); + connect(element, element.ty().HdlNone()); } Self::for_each(this, |index, element| { connect(array_vec_as_array_of_options[index], HdlSome(element)) diff --git a/crates/cpu/tests/expected/next_pc.vcd b/crates/cpu/tests/expected/next_pc.vcd new file mode 100644 index 0000000..087e510 --- /dev/null +++ b/crates/cpu/tests/expected/next_pc.vcd @@ -0,0 +1,13046 @@ +$timescale 1 ps $end +$scope module dut $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$scope struct next_pc $end +$scope struct cd $end +$var wire 1 ++ clk $end +$var wire 1 ,+ rst $end +$upscope $end +$scope struct to_fetch $end +$scope struct inner $end +$scope struct data $end +$var string 1 -+ \$tag $end +$scope struct HdlSome $end +$var wire 64 .+ next_fetch_pc $end +$var wire 8 /+ fetch_block_id $end +$var wire 8 0+ in_progress_fetches_to_cancel $end +$upscope $end +$upscope $end +$var wire 1 1+ ready $end +$upscope $end +$var string 1 2+ config $end +$upscope $end +$scope struct from_decode $end +$scope struct inner $end +$scope struct data $end +$var string 1 3+ \$tag $end +$scope struct HdlSome $end +$var wire 8 4+ fetch_block_id $end +$scope struct insns $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 8 5+ fetch_block_id $end +$var wire 12 6+ id $end +$var wire 64 7+ pc $end +$var wire 4 8+ size_in_bytes $end +$scope struct kind $end +$var string 1 9+ \$tag $end +$var wire 64 :+ Branch $end +$var wire 64 ;+ BranchCond $end +$var wire 64 <+ Call $end +$var wire 64 =+ CallCond $end +$var wire 64 >+ Interrupt $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 8 ?+ fetch_block_id $end +$var wire 12 @+ id $end +$var wire 64 A+ pc $end +$var wire 4 B+ size_in_bytes $end +$scope struct kind $end +$var string 1 C+ \$tag $end +$var wire 64 D+ Branch $end +$var wire 64 E+ BranchCond $end +$var wire 64 F+ Call $end +$var wire 64 G+ CallCond $end +$var wire 64 H+ Interrupt $end +$upscope $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 I+ value $end +$var string 1 J+ range $end +$upscope $end +$upscope $end +$var string 1 K+ config $end +$upscope $end +$upscope $end +$var wire 1 L+ ready $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct speculative_call_stack $end +$scope struct return_addresses $end +$var wire 64 M+ \[0] $end +$var wire 64 N+ \[1] $end +$var wire 64 O+ \[2] $end +$var wire 64 P+ \[3] $end +$var wire 64 Q+ \[4] $end +$var wire 64 R+ \[5] $end +$var wire 64 S+ \[6] $end +$var wire 64 T+ \[7] $end +$var wire 64 U+ \[8] $end +$var wire 64 V+ \[9] $end +$var wire 64 W+ \[10] $end +$var wire 64 X+ \[11] $end +$var wire 64 Y+ \[12] $end +$var wire 64 Z+ \[13] $end +$var wire 64 [+ \[14] $end +$var wire 64 \+ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 ]+ value $end +$var string 1 ^+ range $end +$upscope $end +$upscope $end +$scope struct non_speculative_call_stack $end +$scope struct return_addresses $end +$var wire 64 _+ \[0] $end +$var wire 64 `+ \[1] $end +$var wire 64 a+ \[2] $end +$var wire 64 b+ \[3] $end +$var wire 64 c+ \[4] $end +$var wire 64 d+ \[5] $end +$var wire 64 e+ \[6] $end +$var wire 64 f+ \[7] $end +$var wire 64 g+ \[8] $end +$var wire 64 h+ \[9] $end +$var wire 64 i+ \[10] $end +$var wire 64 j+ \[11] $end +$var wire 64 k+ \[12] $end +$var wire 64 l+ \[13] $end +$var wire 64 m+ \[14] $end +$var wire 64 n+ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 o+ value $end +$var string 1 p+ range $end +$upscope $end +$upscope $end +$scope struct branch_target_buffer $end +$scope struct branch_pc_to_target_map $end +$scope struct \[0] $end +$var string 1 q+ \$tag $end +$scope struct HdlSome $end +$var wire 64 r+ start_pc $end +$var wire 64 s+ target_pc $end +$var wire 8 t+ fallthrough_offset $end +$var string 1 u+ insn_kind $end +$var string 1 v+ addr_kind $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 w+ \$tag $end +$scope struct HdlSome $end +$var wire 64 x+ start_pc $end +$var wire 64 y+ target_pc $end +$var wire 8 z+ fallthrough_offset $end +$var string 1 {+ insn_kind $end +$var string 1 |+ addr_kind $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 }+ \$tag $end +$scope struct HdlSome $end +$var wire 64 ~+ start_pc $end +$var wire 64 !, target_pc $end +$var wire 8 ", fallthrough_offset $end +$var string 1 #, insn_kind $end +$var string 1 $, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 %, \$tag $end +$scope struct HdlSome $end +$var wire 64 &, start_pc $end +$var wire 64 ', target_pc $end +$var wire 8 (, fallthrough_offset $end +$var string 1 ), insn_kind $end +$var string 1 *, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 +, \$tag $end +$scope struct HdlSome $end +$var wire 64 ,, start_pc $end +$var wire 64 -, target_pc $end +$var wire 8 ., fallthrough_offset $end +$var string 1 /, insn_kind $end +$var string 1 0, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 1, \$tag $end +$scope struct HdlSome $end +$var wire 64 2, start_pc $end +$var wire 64 3, target_pc $end +$var wire 8 4, fallthrough_offset $end +$var string 1 5, insn_kind $end +$var string 1 6, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$var string 1 7, \$tag $end +$scope struct HdlSome $end +$var wire 64 8, start_pc $end +$var wire 64 9, target_pc $end +$var wire 8 :, fallthrough_offset $end +$var string 1 ;, insn_kind $end +$var string 1 <, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$var string 1 =, \$tag $end +$scope struct HdlSome $end +$var wire 64 >, start_pc $end +$var wire 64 ?, target_pc $end +$var wire 8 @, fallthrough_offset $end +$var string 1 A, insn_kind $end +$var string 1 B, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$var string 1 C, \$tag $end +$scope struct HdlSome $end +$var wire 64 D, start_pc $end +$var wire 64 E, target_pc $end +$var wire 8 F, fallthrough_offset $end +$var string 1 G, insn_kind $end +$var string 1 H, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$var string 1 I, \$tag $end +$scope struct HdlSome $end +$var wire 64 J, start_pc $end +$var wire 64 K, target_pc $end +$var wire 8 L, fallthrough_offset $end +$var string 1 M, insn_kind $end +$var string 1 N, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$var string 1 O, \$tag $end +$scope struct HdlSome $end +$var wire 64 P, start_pc $end +$var wire 64 Q, target_pc $end +$var wire 8 R, fallthrough_offset $end +$var string 1 S, insn_kind $end +$var string 1 T, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$var string 1 U, \$tag $end +$scope struct HdlSome $end +$var wire 64 V, start_pc $end +$var wire 64 W, target_pc $end +$var wire 8 X, fallthrough_offset $end +$var string 1 Y, insn_kind $end +$var string 1 Z, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$var string 1 [, \$tag $end +$scope struct HdlSome $end +$var wire 64 \, start_pc $end +$var wire 64 ], target_pc $end +$var wire 8 ^, fallthrough_offset $end +$var string 1 _, insn_kind $end +$var string 1 `, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[13] $end +$var string 1 a, \$tag $end +$scope struct HdlSome $end +$var wire 64 b, start_pc $end +$var wire 64 c, target_pc $end +$var wire 8 d, fallthrough_offset $end +$var string 1 e, insn_kind $end +$var string 1 f, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$var string 1 g, \$tag $end +$scope struct HdlSome $end +$var wire 64 h, start_pc $end +$var wire 64 i, target_pc $end +$var wire 8 j, fallthrough_offset $end +$var string 1 k, insn_kind $end +$var string 1 l, addr_kind $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$var string 1 m, \$tag $end +$scope struct HdlSome $end +$var wire 64 n, start_pc $end +$var wire 64 o, target_pc $end +$var wire 8 p, fallthrough_offset $end +$var string 1 q, insn_kind $end +$var string 1 r, addr_kind $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct branch_history $end +$scope struct history $end +$var wire 1 s, \[0] $end +$var wire 1 t, \[1] $end +$var wire 1 u, \[2] $end +$var wire 1 v, \[3] $end +$var wire 1 w, \[4] $end +$var wire 1 x, \[5] $end +$var wire 1 y, \[6] $end +$var wire 1 z, \[7] $end +$var wire 1 {, \[8] $end +$var wire 1 |, \[9] $end +$var wire 1 }, \[10] $end +$var wire 1 ~, \[11] $end +$var wire 1 !- \[12] $end +$var wire 1 "- \[13] $end +$var wire 1 #- \[14] $end +$var wire 1 $- \[15] $end +$var wire 1 %- \[16] $end +$var wire 1 &- \[17] $end +$var wire 1 '- \[18] $end +$var wire 1 (- \[19] $end +$var wire 1 )- \[20] $end +$var wire 1 *- \[21] $end +$var wire 1 +- \[22] $end +$var wire 1 ,- \[23] $end +$var wire 1 -- \[24] $end +$var wire 1 .- \[25] $end +$var wire 1 /- \[26] $end +$var wire 1 0- \[27] $end +$var wire 1 1- \[28] $end +$var wire 1 2- \[29] $end +$var wire 1 3- \[30] $end +$var wire 1 4- \[31] $end +$var wire 1 5- \[32] $end +$var wire 1 6- \[33] $end +$var wire 1 7- \[34] $end +$var wire 1 8- \[35] $end +$var wire 1 9- \[36] $end +$var wire 1 :- \[37] $end +$var wire 1 ;- \[38] $end +$var wire 1 <- \[39] $end +$var wire 1 =- \[40] $end +$var wire 1 >- \[41] $end +$var wire 1 ?- \[42] $end +$var wire 1 @- \[43] $end +$var wire 1 A- \[44] $end +$var wire 1 B- \[45] $end +$var wire 1 C- \[46] $end +$var wire 1 D- \[47] $end +$var wire 1 E- \[48] $end +$var wire 1 F- \[49] $end +$var wire 1 G- \[50] $end +$var wire 1 H- \[51] $end +$var wire 1 I- \[52] $end +$var wire 1 J- \[53] $end +$var wire 1 K- \[54] $end +$var wire 1 L- \[55] $end +$var wire 1 M- \[56] $end +$var wire 1 N- \[57] $end +$var wire 1 O- \[58] $end +$var wire 1 P- \[59] $end +$var wire 1 Q- \[60] $end +$var wire 1 R- \[61] $end +$var wire 1 S- \[62] $end +$var wire 1 T- \[63] $end +$var wire 1 U- \[64] $end +$var wire 1 V- \[65] $end +$var wire 1 W- \[66] $end +$var wire 1 X- \[67] $end +$var wire 1 Y- \[68] $end +$var wire 1 Z- \[69] $end +$var wire 1 [- \[70] $end +$var wire 1 \- \[71] $end +$var wire 1 ]- \[72] $end +$var wire 1 ^- \[73] $end +$var wire 1 _- \[74] $end +$var wire 1 `- \[75] $end +$var wire 1 a- \[76] $end +$var wire 1 b- \[77] $end +$var wire 1 c- \[78] $end +$var wire 1 d- \[79] $end +$var wire 1 e- \[80] $end +$var wire 1 f- \[81] $end +$var wire 1 g- \[82] $end +$var wire 1 h- \[83] $end +$var wire 1 i- \[84] $end +$var wire 1 j- \[85] $end +$var wire 1 k- \[86] $end +$var wire 1 l- \[87] $end +$var wire 1 m- \[88] $end +$var wire 1 n- \[89] $end +$var wire 1 o- \[90] $end +$var wire 1 p- \[91] $end +$var wire 1 q- \[92] $end +$var wire 1 r- \[93] $end +$var wire 1 s- \[94] $end +$var wire 1 t- \[95] $end +$var wire 1 u- \[96] $end +$var wire 1 v- \[97] $end +$var wire 1 w- \[98] $end +$var wire 1 x- \[99] $end +$var wire 1 y- \[100] $end +$var wire 1 z- \[101] $end +$var wire 1 {- \[102] $end +$var wire 1 |- \[103] $end +$var wire 1 }- \[104] $end +$var wire 1 ~- \[105] $end +$var wire 1 !. \[106] $end +$var wire 1 ". \[107] $end +$var wire 1 #. \[108] $end +$var wire 1 $. \[109] $end +$var wire 1 %. \[110] $end +$var wire 1 &. \[111] $end +$var wire 1 '. \[112] $end +$var wire 1 (. \[113] $end +$var wire 1 ). \[114] $end +$var wire 1 *. \[115] $end +$var wire 1 +. \[116] $end +$var wire 1 ,. \[117] $end +$var wire 1 -. \[118] $end +$var wire 1 .. \[119] $end +$var wire 1 /. \[120] $end +$var wire 1 0. \[121] $end +$var wire 1 1. \[122] $end +$var wire 1 2. \[123] $end +$var wire 1 3. \[124] $end +$var wire 1 4. \[125] $end +$var wire 1 5. \[126] $end +$var wire 1 6. \[127] $end +$var wire 1 7. \[128] $end +$var wire 1 8. \[129] $end +$var wire 1 9. \[130] $end +$var wire 1 :. \[131] $end +$var wire 1 ;. \[132] $end +$var wire 1 <. \[133] $end +$var wire 1 =. \[134] $end +$var wire 1 >. \[135] $end +$var wire 1 ?. \[136] $end +$var wire 1 @. \[137] $end +$var wire 1 A. \[138] $end +$var wire 1 B. \[139] $end +$var wire 1 C. \[140] $end +$var wire 1 D. \[141] $end +$var wire 1 E. \[142] $end +$var wire 1 F. \[143] $end +$var wire 1 G. \[144] $end +$var wire 1 H. \[145] $end +$var wire 1 I. \[146] $end +$var wire 1 J. \[147] $end +$var wire 1 K. \[148] $end +$var wire 1 L. \[149] $end +$var wire 1 M. \[150] $end +$var wire 1 N. \[151] $end +$var wire 1 O. \[152] $end +$var wire 1 P. \[153] $end +$var wire 1 Q. \[154] $end +$var wire 1 R. \[155] $end +$var wire 1 S. \[156] $end +$var wire 1 T. \[157] $end +$var wire 1 U. \[158] $end +$var wire 1 V. \[159] $end +$var wire 1 W. \[160] $end +$var wire 1 X. \[161] $end +$var wire 1 Y. \[162] $end +$var wire 1 Z. \[163] $end +$var wire 1 [. \[164] $end +$var wire 1 \. \[165] $end +$var wire 1 ]. \[166] $end +$var wire 1 ^. \[167] $end +$var wire 1 _. \[168] $end +$var wire 1 `. \[169] $end +$var wire 1 a. \[170] $end +$var wire 1 b. \[171] $end +$var wire 1 c. \[172] $end +$var wire 1 d. \[173] $end +$var wire 1 e. \[174] $end +$var wire 1 f. \[175] $end +$var wire 1 g. \[176] $end +$var wire 1 h. \[177] $end +$var wire 1 i. \[178] $end +$var wire 1 j. \[179] $end +$var wire 1 k. \[180] $end +$var wire 1 l. \[181] $end +$var wire 1 m. \[182] $end +$var wire 1 n. \[183] $end +$var wire 1 o. \[184] $end +$var wire 1 p. \[185] $end +$var wire 1 q. \[186] $end +$var wire 1 r. \[187] $end +$var wire 1 s. \[188] $end +$var wire 1 t. \[189] $end +$var wire 1 u. \[190] $end +$var wire 1 v. \[191] $end +$var wire 1 w. \[192] $end +$var wire 1 x. \[193] $end +$var wire 1 y. \[194] $end +$var wire 1 z. \[195] $end +$var wire 1 {. \[196] $end +$var wire 1 |. \[197] $end +$var wire 1 }. \[198] $end +$var wire 1 ~. \[199] $end +$var wire 1 !/ \[200] $end +$var wire 1 "/ \[201] $end +$var wire 1 #/ \[202] $end +$var wire 1 $/ \[203] $end +$var wire 1 %/ \[204] $end +$var wire 1 &/ \[205] $end +$var wire 1 '/ \[206] $end +$var wire 1 (/ \[207] $end +$var wire 1 )/ \[208] $end +$var wire 1 */ \[209] $end +$var wire 1 +/ \[210] $end +$var wire 1 ,/ \[211] $end +$var wire 1 -/ \[212] $end +$var wire 1 ./ \[213] $end +$var wire 1 // \[214] $end +$var wire 1 0/ \[215] $end +$var wire 1 1/ \[216] $end +$var wire 1 2/ \[217] $end +$var wire 1 3/ \[218] $end +$var wire 1 4/ \[219] $end +$var wire 1 5/ \[220] $end +$var wire 1 6/ \[221] $end +$var wire 1 7/ \[222] $end +$var wire 1 8/ \[223] $end +$var wire 1 9/ \[224] $end +$var wire 1 :/ \[225] $end +$var wire 1 ;/ \[226] $end +$var wire 1 / \[229] $end +$var wire 1 ?/ \[230] $end +$var wire 1 @/ \[231] $end +$var wire 1 A/ \[232] $end +$var wire 1 B/ \[233] $end +$var wire 1 C/ \[234] $end +$var wire 1 D/ \[235] $end +$var wire 1 E/ \[236] $end +$var wire 1 F/ \[237] $end +$var wire 1 G/ \[238] $end +$var wire 1 H/ \[239] $end +$var wire 1 I/ \[240] $end +$var wire 1 J/ \[241] $end +$var wire 1 K/ \[242] $end +$var wire 1 L/ \[243] $end +$var wire 1 M/ \[244] $end +$var wire 1 N/ \[245] $end +$var wire 1 O/ \[246] $end +$var wire 1 P/ \[247] $end +$var wire 1 Q/ \[248] $end +$var wire 1 R/ \[249] $end +$var wire 1 S/ \[250] $end +$var wire 1 T/ \[251] $end +$var wire 1 U/ \[252] $end +$var wire 1 V/ \[253] $end +$var wire 1 W/ \[254] $end +$var wire 1 X/ \[255] $end +$upscope $end +$scope struct tail $end +$var wire 8 Y/ value $end +$var string 1 Z/ range $end +$upscope $end +$scope struct non_speculative_head $end +$var wire 8 [/ value $end +$var string 1 \/ range $end +$upscope $end +$scope struct speculative_head $end +$var wire 8 ]/ value $end +$var string 1 ^/ range $end +$upscope $end +$upscope $end +$scope struct branch_predictor $end +$var string 1 _/ \[0] $end +$var string 1 `/ \[1] $end +$var string 1 a/ \[2] $end +$var string 1 b/ \[3] $end +$var string 1 c/ \[4] $end +$var string 1 d/ \[5] $end +$var string 1 e/ \[6] $end +$var string 1 f/ \[7] $end +$var string 1 g/ \[8] $end +$var string 1 h/ \[9] $end +$var string 1 i/ \[10] $end +$var string 1 j/ \[11] $end +$var string 1 k/ \[12] $end +$var string 1 l/ \[13] $end +$var string 1 m/ \[14] $end +$var string 1 n/ \[15] $end +$var string 1 o/ \[16] $end +$var string 1 p/ \[17] $end +$var string 1 q/ \[18] $end +$var string 1 r/ \[19] $end +$var string 1 s/ \[20] $end +$var string 1 t/ \[21] $end +$var string 1 u/ \[22] $end +$var string 1 v/ \[23] $end +$var string 1 w/ \[24] $end +$var string 1 x/ \[25] $end +$var string 1 y/ \[26] $end +$var string 1 z/ \[27] $end +$var string 1 {/ \[28] $end +$var string 1 |/ \[29] $end +$var string 1 }/ \[30] $end +$var string 1 ~/ \[31] $end +$var string 1 !0 \[32] $end +$var string 1 "0 \[33] $end +$var string 1 #0 \[34] $end +$var string 1 $0 \[35] $end +$var string 1 %0 \[36] $end +$var string 1 &0 \[37] $end +$var string 1 '0 \[38] $end +$var string 1 (0 \[39] $end +$var string 1 )0 \[40] $end +$var string 1 *0 \[41] $end +$var string 1 +0 \[42] $end +$var string 1 ,0 \[43] $end +$var string 1 -0 \[44] $end +$var string 1 .0 \[45] $end +$var string 1 /0 \[46] $end +$var string 1 00 \[47] $end +$var string 1 10 \[48] $end +$var string 1 20 \[49] $end +$var string 1 30 \[50] $end +$var string 1 40 \[51] $end +$var string 1 50 \[52] $end +$var string 1 60 \[53] $end +$var string 1 70 \[54] $end +$var string 1 80 \[55] $end +$var string 1 90 \[56] $end +$var string 1 :0 \[57] $end +$var string 1 ;0 \[58] $end +$var string 1 <0 \[59] $end +$var string 1 =0 \[60] $end +$var string 1 >0 \[61] $end +$var string 1 ?0 \[62] $end +$var string 1 @0 \[63] $end +$var string 1 A0 \[64] $end +$var string 1 B0 \[65] $end +$var string 1 C0 \[66] $end +$var string 1 D0 \[67] $end +$var string 1 E0 \[68] $end +$var string 1 F0 \[69] $end +$var string 1 G0 \[70] $end +$var string 1 H0 \[71] $end +$var string 1 I0 \[72] $end +$var string 1 J0 \[73] $end +$var string 1 K0 \[74] $end +$var string 1 L0 \[75] $end +$var string 1 M0 \[76] $end +$var string 1 N0 \[77] $end +$var string 1 O0 \[78] $end +$var string 1 P0 \[79] $end +$var string 1 Q0 \[80] $end +$var string 1 R0 \[81] $end +$var string 1 S0 \[82] $end +$var string 1 T0 \[83] $end +$var string 1 U0 \[84] $end +$var string 1 V0 \[85] $end +$var string 1 W0 \[86] $end +$var string 1 X0 \[87] $end +$var string 1 Y0 \[88] $end +$var string 1 Z0 \[89] $end +$var string 1 [0 \[90] $end +$var string 1 \0 \[91] $end +$var string 1 ]0 \[92] $end +$var string 1 ^0 \[93] $end +$var string 1 _0 \[94] $end +$var string 1 `0 \[95] $end +$var string 1 a0 \[96] $end +$var string 1 b0 \[97] $end +$var string 1 c0 \[98] $end +$var string 1 d0 \[99] $end +$var string 1 e0 \[100] $end +$var string 1 f0 \[101] $end +$var string 1 g0 \[102] $end +$var string 1 h0 \[103] $end +$var string 1 i0 \[104] $end +$var string 1 j0 \[105] $end +$var string 1 k0 \[106] $end +$var string 1 l0 \[107] $end +$var string 1 m0 \[108] $end +$var string 1 n0 \[109] $end +$var string 1 o0 \[110] $end +$var string 1 p0 \[111] $end +$var string 1 q0 \[112] $end +$var string 1 r0 \[113] $end +$var string 1 s0 \[114] $end +$var string 1 t0 \[115] $end +$var string 1 u0 \[116] $end +$var string 1 v0 \[117] $end +$var string 1 w0 \[118] $end +$var string 1 x0 \[119] $end +$var string 1 y0 \[120] $end +$var string 1 z0 \[121] $end +$var string 1 {0 \[122] $end +$var string 1 |0 \[123] $end +$var string 1 }0 \[124] $end +$var string 1 ~0 \[125] $end +$var string 1 !1 \[126] $end +$var string 1 "1 \[127] $end +$var string 1 #1 \[128] $end +$var string 1 $1 \[129] $end +$var string 1 %1 \[130] $end +$var string 1 &1 \[131] $end +$var string 1 '1 \[132] $end +$var string 1 (1 \[133] $end +$var string 1 )1 \[134] $end +$var string 1 *1 \[135] $end +$var string 1 +1 \[136] $end +$var string 1 ,1 \[137] $end +$var string 1 -1 \[138] $end +$var string 1 .1 \[139] $end +$var string 1 /1 \[140] $end +$var string 1 01 \[141] $end +$var string 1 11 \[142] $end +$var string 1 21 \[143] $end +$var string 1 31 \[144] $end +$var string 1 41 \[145] $end +$var string 1 51 \[146] $end +$var string 1 61 \[147] $end +$var string 1 71 \[148] $end +$var string 1 81 \[149] $end +$var string 1 91 \[150] $end +$var string 1 :1 \[151] $end +$var string 1 ;1 \[152] $end +$var string 1 <1 \[153] $end +$var string 1 =1 \[154] $end +$var string 1 >1 \[155] $end +$var string 1 ?1 \[156] $end +$var string 1 @1 \[157] $end +$var string 1 A1 \[158] $end +$var string 1 B1 \[159] $end +$var string 1 C1 \[160] $end +$var string 1 D1 \[161] $end +$var string 1 E1 \[162] $end +$var string 1 F1 \[163] $end +$var string 1 G1 \[164] $end +$var string 1 H1 \[165] $end +$var string 1 I1 \[166] $end +$var string 1 J1 \[167] $end +$var string 1 K1 \[168] $end +$var string 1 L1 \[169] $end +$var string 1 M1 \[170] $end +$var string 1 N1 \[171] $end +$var string 1 O1 \[172] $end +$var string 1 P1 \[173] $end +$var string 1 Q1 \[174] $end +$var string 1 R1 \[175] $end +$var string 1 S1 \[176] $end +$var string 1 T1 \[177] $end +$var string 1 U1 \[178] $end +$var string 1 V1 \[179] $end +$var string 1 W1 \[180] $end +$var string 1 X1 \[181] $end +$var string 1 Y1 \[182] $end +$var string 1 Z1 \[183] $end +$var string 1 [1 \[184] $end +$var string 1 \1 \[185] $end +$var string 1 ]1 \[186] $end +$var string 1 ^1 \[187] $end +$var string 1 _1 \[188] $end +$var string 1 `1 \[189] $end +$var string 1 a1 \[190] $end +$var string 1 b1 \[191] $end +$var string 1 c1 \[192] $end +$var string 1 d1 \[193] $end +$var string 1 e1 \[194] $end +$var string 1 f1 \[195] $end +$var string 1 g1 \[196] $end +$var string 1 h1 \[197] $end +$var string 1 i1 \[198] $end +$var string 1 j1 \[199] $end +$var string 1 k1 \[200] $end +$var string 1 l1 \[201] $end +$var string 1 m1 \[202] $end +$var string 1 n1 \[203] $end +$var string 1 o1 \[204] $end +$var string 1 p1 \[205] $end +$var string 1 q1 \[206] $end +$var string 1 r1 \[207] $end +$var string 1 s1 \[208] $end +$var string 1 t1 \[209] $end +$var string 1 u1 \[210] $end +$var string 1 v1 \[211] $end +$var string 1 w1 \[212] $end +$var string 1 x1 \[213] $end +$var string 1 y1 \[214] $end +$var string 1 z1 \[215] $end +$var string 1 {1 \[216] $end +$var string 1 |1 \[217] $end +$var string 1 }1 \[218] $end +$var string 1 ~1 \[219] $end +$var string 1 !2 \[220] $end +$var string 1 "2 \[221] $end +$var string 1 #2 \[222] $end +$var string 1 $2 \[223] $end +$var string 1 %2 \[224] $end +$var string 1 &2 \[225] $end +$var string 1 '2 \[226] $end +$var string 1 (2 \[227] $end +$var string 1 )2 \[228] $end +$var string 1 *2 \[229] $end +$var string 1 +2 \[230] $end +$var string 1 ,2 \[231] $end +$var string 1 -2 \[232] $end +$var string 1 .2 \[233] $end +$var string 1 /2 \[234] $end +$var string 1 02 \[235] $end +$var string 1 12 \[236] $end +$var string 1 22 \[237] $end +$var string 1 32 \[238] $end +$var string 1 42 \[239] $end +$var string 1 52 \[240] $end +$var string 1 62 \[241] $end +$var string 1 72 \[242] $end +$var string 1 82 \[243] $end +$var string 1 92 \[244] $end +$var string 1 :2 \[245] $end +$var string 1 ;2 \[246] $end +$var string 1 <2 \[247] $end +$var string 1 =2 \[248] $end +$var string 1 >2 \[249] $end +$var string 1 ?2 \[250] $end +$var string 1 @2 \[251] $end +$var string 1 A2 \[252] $end +$var string 1 B2 \[253] $end +$var string 1 C2 \[254] $end +$var string 1 D2 \[255] $end +$upscope $end +$scope struct fetching_queue $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 E2 fetch_block_id $end +$upscope $end +$scope struct \[1] $end +$var wire 8 F2 fetch_block_id $end +$upscope $end +$scope struct \[2] $end +$var wire 8 G2 fetch_block_id $end +$upscope $end +$scope struct \[3] $end +$var wire 8 H2 fetch_block_id $end +$upscope $end +$scope struct \[4] $end +$var wire 8 I2 fetch_block_id $end +$upscope $end +$scope struct \[5] $end +$var wire 8 J2 fetch_block_id $end +$upscope $end +$scope struct \[6] $end +$var wire 8 K2 fetch_block_id $end +$upscope $end +$scope struct \[7] $end +$var wire 8 L2 fetch_block_id $end +$upscope $end +$scope struct \[8] $end +$var wire 8 M2 fetch_block_id $end +$upscope $end +$scope struct \[9] $end +$var wire 8 N2 fetch_block_id $end +$upscope $end +$scope struct \[10] $end +$var wire 8 O2 fetch_block_id $end +$upscope $end +$scope struct \[11] $end +$var wire 8 P2 fetch_block_id $end +$upscope $end +$scope struct \[12] $end +$var wire 8 Q2 fetch_block_id $end +$upscope $end +$scope struct \[13] $end +$var wire 8 R2 fetch_block_id $end +$upscope $end +$scope struct \[14] $end +$var wire 8 S2 fetch_block_id $end +$upscope $end +$scope struct \[15] $end +$var wire 8 T2 fetch_block_id $end +$upscope $end +$scope struct \[16] $end +$var wire 8 U2 fetch_block_id $end +$upscope $end +$scope struct \[17] $end +$var wire 8 V2 fetch_block_id $end +$upscope $end +$scope struct \[18] $end +$var wire 8 W2 fetch_block_id $end +$upscope $end +$scope struct \[19] $end +$var wire 8 X2 fetch_block_id $end +$upscope $end +$scope struct \[20] $end +$var wire 8 Y2 fetch_block_id $end +$upscope $end +$scope struct \[21] $end +$var wire 8 Z2 fetch_block_id $end +$upscope $end +$scope struct \[22] $end +$var wire 8 [2 fetch_block_id $end +$upscope $end +$scope struct \[23] $end +$var wire 8 \2 fetch_block_id $end +$upscope $end +$scope struct \[24] $end +$var wire 8 ]2 fetch_block_id $end +$upscope $end +$scope struct \[25] $end +$var wire 8 ^2 fetch_block_id $end +$upscope $end +$scope struct \[26] $end +$var wire 8 _2 fetch_block_id $end +$upscope $end +$scope struct \[27] $end +$var wire 8 `2 fetch_block_id $end +$upscope $end +$scope struct \[28] $end +$var wire 8 a2 fetch_block_id $end +$upscope $end +$scope struct \[29] $end +$var wire 8 b2 fetch_block_id $end +$upscope $end +$scope struct \[30] $end +$var wire 8 c2 fetch_block_id $end +$upscope $end +$scope struct \[31] $end +$var wire 8 d2 fetch_block_id $end +$upscope $end +$scope struct \[32] $end +$var wire 8 e2 fetch_block_id $end +$upscope $end +$scope struct \[33] $end +$var wire 8 f2 fetch_block_id $end +$upscope $end +$scope struct \[34] $end +$var wire 8 g2 fetch_block_id $end +$upscope $end +$scope struct \[35] $end +$var wire 8 h2 fetch_block_id $end +$upscope $end +$scope struct \[36] $end +$var wire 8 i2 fetch_block_id $end +$upscope $end +$scope struct \[37] $end +$var wire 8 j2 fetch_block_id $end +$upscope $end +$scope struct \[38] $end +$var wire 8 k2 fetch_block_id $end +$upscope $end +$scope struct \[39] $end +$var wire 8 l2 fetch_block_id $end +$upscope $end +$scope struct \[40] $end +$var wire 8 m2 fetch_block_id $end +$upscope $end +$scope struct \[41] $end +$var wire 8 n2 fetch_block_id $end +$upscope $end +$scope struct \[42] $end +$var wire 8 o2 fetch_block_id $end +$upscope $end +$scope struct \[43] $end +$var wire 8 p2 fetch_block_id $end +$upscope $end +$scope struct \[44] $end +$var wire 8 q2 fetch_block_id $end +$upscope $end +$scope struct \[45] $end +$var wire 8 r2 fetch_block_id $end +$upscope $end +$scope struct \[46] $end +$var wire 8 s2 fetch_block_id $end +$upscope $end +$scope struct \[47] $end +$var wire 8 t2 fetch_block_id $end +$upscope $end +$scope struct \[48] $end +$var wire 8 u2 fetch_block_id $end +$upscope $end +$scope struct \[49] $end +$var wire 8 v2 fetch_block_id $end +$upscope $end +$scope struct \[50] $end +$var wire 8 w2 fetch_block_id $end +$upscope $end +$scope struct \[51] $end +$var wire 8 x2 fetch_block_id $end +$upscope $end +$scope struct \[52] $end +$var wire 8 y2 fetch_block_id $end +$upscope $end +$scope struct \[53] $end +$var wire 8 z2 fetch_block_id $end +$upscope $end +$scope struct \[54] $end +$var wire 8 {2 fetch_block_id $end +$upscope $end +$scope struct \[55] $end +$var wire 8 |2 fetch_block_id $end +$upscope $end +$scope struct \[56] $end +$var wire 8 }2 fetch_block_id $end +$upscope $end +$scope struct \[57] $end +$var wire 8 ~2 fetch_block_id $end +$upscope $end +$scope struct \[58] $end +$var wire 8 !3 fetch_block_id $end +$upscope $end +$scope struct \[59] $end +$var wire 8 "3 fetch_block_id $end +$upscope $end +$scope struct \[60] $end +$var wire 8 #3 fetch_block_id $end +$upscope $end +$scope struct \[61] $end +$var wire 8 $3 fetch_block_id $end +$upscope $end +$scope struct \[62] $end +$var wire 8 %3 fetch_block_id $end +$upscope $end +$scope struct \[63] $end +$var wire 8 &3 fetch_block_id $end +$upscope $end +$scope struct \[64] $end +$var wire 8 '3 fetch_block_id $end +$upscope $end +$scope struct \[65] $end +$var wire 8 (3 fetch_block_id $end +$upscope $end +$scope struct \[66] $end +$var wire 8 )3 fetch_block_id $end +$upscope $end +$scope struct \[67] $end +$var wire 8 *3 fetch_block_id $end +$upscope $end +$scope struct \[68] $end +$var wire 8 +3 fetch_block_id $end +$upscope $end +$scope struct \[69] $end +$var wire 8 ,3 fetch_block_id $end +$upscope $end +$scope struct \[70] $end +$var wire 8 -3 fetch_block_id $end +$upscope $end +$scope struct \[71] $end +$var wire 8 .3 fetch_block_id $end +$upscope $end +$scope struct \[72] $end +$var wire 8 /3 fetch_block_id $end +$upscope $end +$scope struct \[73] $end +$var wire 8 03 fetch_block_id $end +$upscope $end +$scope struct \[74] $end +$var wire 8 13 fetch_block_id $end +$upscope $end +$scope struct \[75] $end +$var wire 8 23 fetch_block_id $end +$upscope $end +$scope struct \[76] $end +$var wire 8 33 fetch_block_id $end +$upscope $end +$scope struct \[77] $end +$var wire 8 43 fetch_block_id $end +$upscope $end +$scope struct \[78] $end +$var wire 8 53 fetch_block_id $end +$upscope $end +$scope struct \[79] $end +$var wire 8 63 fetch_block_id $end +$upscope $end +$scope struct \[80] $end +$var wire 8 73 fetch_block_id $end +$upscope $end +$scope struct \[81] $end +$var wire 8 83 fetch_block_id $end +$upscope $end +$scope struct \[82] $end +$var wire 8 93 fetch_block_id $end +$upscope $end +$scope struct \[83] $end +$var wire 8 :3 fetch_block_id $end +$upscope $end +$scope struct \[84] $end +$var wire 8 ;3 fetch_block_id $end +$upscope $end +$scope struct \[85] $end +$var wire 8 <3 fetch_block_id $end +$upscope $end +$scope struct \[86] $end +$var wire 8 =3 fetch_block_id $end +$upscope $end +$scope struct \[87] $end +$var wire 8 >3 fetch_block_id $end +$upscope $end +$scope struct \[88] $end +$var wire 8 ?3 fetch_block_id $end +$upscope $end +$scope struct \[89] $end +$var wire 8 @3 fetch_block_id $end +$upscope $end +$scope struct \[90] $end +$var wire 8 A3 fetch_block_id $end +$upscope $end +$scope struct \[91] $end +$var wire 8 B3 fetch_block_id $end +$upscope $end +$scope struct \[92] $end +$var wire 8 C3 fetch_block_id $end +$upscope $end +$scope struct \[93] $end +$var wire 8 D3 fetch_block_id $end +$upscope $end +$scope struct \[94] $end +$var wire 8 E3 fetch_block_id $end +$upscope $end +$scope struct \[95] $end +$var wire 8 F3 fetch_block_id $end +$upscope $end +$scope struct \[96] $end +$var wire 8 G3 fetch_block_id $end +$upscope $end +$scope struct \[97] $end +$var wire 8 H3 fetch_block_id $end +$upscope $end +$scope struct \[98] $end +$var wire 8 I3 fetch_block_id $end +$upscope $end +$scope struct \[99] $end +$var wire 8 J3 fetch_block_id $end +$upscope $end +$scope struct \[100] $end +$var wire 8 K3 fetch_block_id $end +$upscope $end +$scope struct \[101] $end +$var wire 8 L3 fetch_block_id $end +$upscope $end +$scope struct \[102] $end +$var wire 8 M3 fetch_block_id $end +$upscope $end +$scope struct \[103] $end +$var wire 8 N3 fetch_block_id $end +$upscope $end +$scope struct \[104] $end +$var wire 8 O3 fetch_block_id $end +$upscope $end +$scope struct \[105] $end +$var wire 8 P3 fetch_block_id $end +$upscope $end +$scope struct \[106] $end +$var wire 8 Q3 fetch_block_id $end +$upscope $end +$scope struct \[107] $end +$var wire 8 R3 fetch_block_id $end +$upscope $end +$scope struct \[108] $end +$var wire 8 S3 fetch_block_id $end +$upscope $end +$scope struct \[109] $end +$var wire 8 T3 fetch_block_id $end +$upscope $end +$scope struct \[110] $end +$var wire 8 U3 fetch_block_id $end +$upscope $end +$scope struct \[111] $end +$var wire 8 V3 fetch_block_id $end +$upscope $end +$scope struct \[112] $end +$var wire 8 W3 fetch_block_id $end +$upscope $end +$scope struct \[113] $end +$var wire 8 X3 fetch_block_id $end +$upscope $end +$scope struct \[114] $end +$var wire 8 Y3 fetch_block_id $end +$upscope $end +$scope struct \[115] $end +$var wire 8 Z3 fetch_block_id $end +$upscope $end +$scope struct \[116] $end +$var wire 8 [3 fetch_block_id $end +$upscope $end +$scope struct \[117] $end +$var wire 8 \3 fetch_block_id $end +$upscope $end +$scope struct \[118] $end +$var wire 8 ]3 fetch_block_id $end +$upscope $end +$scope struct \[119] $end +$var wire 8 ^3 fetch_block_id $end +$upscope $end +$scope struct \[120] $end +$var wire 8 _3 fetch_block_id $end +$upscope $end +$scope struct \[121] $end +$var wire 8 `3 fetch_block_id $end +$upscope $end +$scope struct \[122] $end +$var wire 8 a3 fetch_block_id $end +$upscope $end +$scope struct \[123] $end +$var wire 8 b3 fetch_block_id $end +$upscope $end +$scope struct \[124] $end +$var wire 8 c3 fetch_block_id $end +$upscope $end +$scope struct \[125] $end +$var wire 8 d3 fetch_block_id $end +$upscope $end +$scope struct \[126] $end +$var wire 8 e3 fetch_block_id $end +$upscope $end +$scope struct \[127] $end +$var wire 8 f3 fetch_block_id $end +$upscope $end +$scope struct \[128] $end +$var wire 8 g3 fetch_block_id $end +$upscope $end +$scope struct \[129] $end +$var wire 8 h3 fetch_block_id $end +$upscope $end +$scope struct \[130] $end +$var wire 8 i3 fetch_block_id $end +$upscope $end +$scope struct \[131] $end +$var wire 8 j3 fetch_block_id $end +$upscope $end +$scope struct \[132] $end +$var wire 8 k3 fetch_block_id $end +$upscope $end +$scope struct \[133] $end +$var wire 8 l3 fetch_block_id $end +$upscope $end +$scope struct \[134] $end +$var wire 8 m3 fetch_block_id $end +$upscope $end +$scope struct \[135] $end +$var wire 8 n3 fetch_block_id $end +$upscope $end +$scope struct \[136] $end +$var wire 8 o3 fetch_block_id $end +$upscope $end +$scope struct \[137] $end +$var wire 8 p3 fetch_block_id $end +$upscope $end +$scope struct \[138] $end +$var wire 8 q3 fetch_block_id $end +$upscope $end +$scope struct \[139] $end +$var wire 8 r3 fetch_block_id $end +$upscope $end +$scope struct \[140] $end +$var wire 8 s3 fetch_block_id $end +$upscope $end +$scope struct \[141] $end +$var wire 8 t3 fetch_block_id $end +$upscope $end +$scope struct \[142] $end +$var wire 8 u3 fetch_block_id $end +$upscope $end +$scope struct \[143] $end +$var wire 8 v3 fetch_block_id $end +$upscope $end +$scope struct \[144] $end +$var wire 8 w3 fetch_block_id $end +$upscope $end +$scope struct \[145] $end +$var wire 8 x3 fetch_block_id $end +$upscope $end +$scope struct \[146] $end +$var wire 8 y3 fetch_block_id $end +$upscope $end +$scope struct \[147] $end +$var wire 8 z3 fetch_block_id $end +$upscope $end +$scope struct \[148] $end +$var wire 8 {3 fetch_block_id $end +$upscope $end +$scope struct \[149] $end +$var wire 8 |3 fetch_block_id $end +$upscope $end +$scope struct \[150] $end +$var wire 8 }3 fetch_block_id $end +$upscope $end +$scope struct \[151] $end +$var wire 8 ~3 fetch_block_id $end +$upscope $end +$scope struct \[152] $end +$var wire 8 !4 fetch_block_id $end +$upscope $end +$scope struct \[153] $end +$var wire 8 "4 fetch_block_id $end +$upscope $end +$scope struct \[154] $end +$var wire 8 #4 fetch_block_id $end +$upscope $end +$scope struct \[155] $end +$var wire 8 $4 fetch_block_id $end +$upscope $end +$scope struct \[156] $end +$var wire 8 %4 fetch_block_id $end +$upscope $end +$scope struct \[157] $end +$var wire 8 &4 fetch_block_id $end +$upscope $end +$scope struct \[158] $end +$var wire 8 '4 fetch_block_id $end +$upscope $end +$scope struct \[159] $end +$var wire 8 (4 fetch_block_id $end +$upscope $end +$scope struct \[160] $end +$var wire 8 )4 fetch_block_id $end +$upscope $end +$scope struct \[161] $end +$var wire 8 *4 fetch_block_id $end +$upscope $end +$scope struct \[162] $end +$var wire 8 +4 fetch_block_id $end +$upscope $end +$scope struct \[163] $end +$var wire 8 ,4 fetch_block_id $end +$upscope $end +$scope struct \[164] $end +$var wire 8 -4 fetch_block_id $end +$upscope $end +$scope struct \[165] $end +$var wire 8 .4 fetch_block_id $end +$upscope $end +$scope struct \[166] $end +$var wire 8 /4 fetch_block_id $end +$upscope $end +$scope struct \[167] $end +$var wire 8 04 fetch_block_id $end +$upscope $end +$scope struct \[168] $end +$var wire 8 14 fetch_block_id $end +$upscope $end +$scope struct \[169] $end +$var wire 8 24 fetch_block_id $end +$upscope $end +$scope struct \[170] $end +$var wire 8 34 fetch_block_id $end +$upscope $end +$scope struct \[171] $end +$var wire 8 44 fetch_block_id $end +$upscope $end +$scope struct \[172] $end +$var wire 8 54 fetch_block_id $end +$upscope $end +$scope struct \[173] $end +$var wire 8 64 fetch_block_id $end +$upscope $end +$scope struct \[174] $end +$var wire 8 74 fetch_block_id $end +$upscope $end +$scope struct \[175] $end +$var wire 8 84 fetch_block_id $end +$upscope $end +$scope struct \[176] $end +$var wire 8 94 fetch_block_id $end +$upscope $end +$scope struct \[177] $end +$var wire 8 :4 fetch_block_id $end +$upscope $end +$scope struct \[178] $end +$var wire 8 ;4 fetch_block_id $end +$upscope $end +$scope struct \[179] $end +$var wire 8 <4 fetch_block_id $end +$upscope $end +$scope struct \[180] $end +$var wire 8 =4 fetch_block_id $end +$upscope $end +$scope struct \[181] $end +$var wire 8 >4 fetch_block_id $end +$upscope $end +$scope struct \[182] $end +$var wire 8 ?4 fetch_block_id $end +$upscope $end +$scope struct \[183] $end +$var wire 8 @4 fetch_block_id $end +$upscope $end +$scope struct \[184] $end +$var wire 8 A4 fetch_block_id $end +$upscope $end +$scope struct \[185] $end +$var wire 8 B4 fetch_block_id $end +$upscope $end +$scope struct \[186] $end +$var wire 8 C4 fetch_block_id $end +$upscope $end +$scope struct \[187] $end +$var wire 8 D4 fetch_block_id $end +$upscope $end +$scope struct \[188] $end +$var wire 8 E4 fetch_block_id $end +$upscope $end +$scope struct \[189] $end +$var wire 8 F4 fetch_block_id $end +$upscope $end +$scope struct \[190] $end +$var wire 8 G4 fetch_block_id $end +$upscope $end +$scope struct \[191] $end +$var wire 8 H4 fetch_block_id $end +$upscope $end +$scope struct \[192] $end +$var wire 8 I4 fetch_block_id $end +$upscope $end +$scope struct \[193] $end +$var wire 8 J4 fetch_block_id $end +$upscope $end +$scope struct \[194] $end +$var wire 8 K4 fetch_block_id $end +$upscope $end +$scope struct \[195] $end +$var wire 8 L4 fetch_block_id $end +$upscope $end +$scope struct \[196] $end +$var wire 8 M4 fetch_block_id $end +$upscope $end +$scope struct \[197] $end +$var wire 8 N4 fetch_block_id $end +$upscope $end +$scope struct \[198] $end +$var wire 8 O4 fetch_block_id $end +$upscope $end +$scope struct \[199] $end +$var wire 8 P4 fetch_block_id $end +$upscope $end +$scope struct \[200] $end +$var wire 8 Q4 fetch_block_id $end +$upscope $end +$scope struct \[201] $end +$var wire 8 R4 fetch_block_id $end +$upscope $end +$scope struct \[202] $end +$var wire 8 S4 fetch_block_id $end +$upscope $end +$scope struct \[203] $end +$var wire 8 T4 fetch_block_id $end +$upscope $end +$scope struct \[204] $end +$var wire 8 U4 fetch_block_id $end +$upscope $end +$scope struct \[205] $end +$var wire 8 V4 fetch_block_id $end +$upscope $end +$scope struct \[206] $end +$var wire 8 W4 fetch_block_id $end +$upscope $end +$scope struct \[207] $end +$var wire 8 X4 fetch_block_id $end +$upscope $end +$scope struct \[208] $end +$var wire 8 Y4 fetch_block_id $end +$upscope $end +$scope struct \[209] $end +$var wire 8 Z4 fetch_block_id $end +$upscope $end +$scope struct \[210] $end +$var wire 8 [4 fetch_block_id $end +$upscope $end +$scope struct \[211] $end +$var wire 8 \4 fetch_block_id $end +$upscope $end +$scope struct \[212] $end +$var wire 8 ]4 fetch_block_id $end +$upscope $end +$scope struct \[213] $end +$var wire 8 ^4 fetch_block_id $end +$upscope $end +$scope struct \[214] $end +$var wire 8 _4 fetch_block_id $end +$upscope $end +$scope struct \[215] $end +$var wire 8 `4 fetch_block_id $end +$upscope $end +$scope struct \[216] $end +$var wire 8 a4 fetch_block_id $end +$upscope $end +$scope struct \[217] $end +$var wire 8 b4 fetch_block_id $end +$upscope $end +$scope struct \[218] $end +$var wire 8 c4 fetch_block_id $end +$upscope $end +$scope struct \[219] $end +$var wire 8 d4 fetch_block_id $end +$upscope $end +$scope struct \[220] $end +$var wire 8 e4 fetch_block_id $end +$upscope $end +$scope struct \[221] $end +$var wire 8 f4 fetch_block_id $end +$upscope $end +$scope struct \[222] $end +$var wire 8 g4 fetch_block_id $end +$upscope $end +$scope struct \[223] $end +$var wire 8 h4 fetch_block_id $end +$upscope $end +$scope struct \[224] $end +$var wire 8 i4 fetch_block_id $end +$upscope $end +$scope struct \[225] $end +$var wire 8 j4 fetch_block_id $end +$upscope $end +$scope struct \[226] $end +$var wire 8 k4 fetch_block_id $end +$upscope $end +$scope struct \[227] $end +$var wire 8 l4 fetch_block_id $end +$upscope $end +$scope struct \[228] $end +$var wire 8 m4 fetch_block_id $end +$upscope $end +$scope struct \[229] $end +$var wire 8 n4 fetch_block_id $end +$upscope $end +$scope struct \[230] $end +$var wire 8 o4 fetch_block_id $end +$upscope $end +$scope struct \[231] $end +$var wire 8 p4 fetch_block_id $end +$upscope $end +$scope struct \[232] $end +$var wire 8 q4 fetch_block_id $end +$upscope $end +$scope struct \[233] $end +$var wire 8 r4 fetch_block_id $end +$upscope $end +$scope struct \[234] $end +$var wire 8 s4 fetch_block_id $end +$upscope $end +$scope struct \[235] $end +$var wire 8 t4 fetch_block_id $end +$upscope $end +$scope struct \[236] $end +$var wire 8 u4 fetch_block_id $end +$upscope $end +$scope struct \[237] $end +$var wire 8 v4 fetch_block_id $end +$upscope $end +$scope struct \[238] $end +$var wire 8 w4 fetch_block_id $end +$upscope $end +$scope struct \[239] $end +$var wire 8 x4 fetch_block_id $end +$upscope $end +$scope struct \[240] $end +$var wire 8 y4 fetch_block_id $end +$upscope $end +$scope struct \[241] $end +$var wire 8 z4 fetch_block_id $end +$upscope $end +$scope struct \[242] $end +$var wire 8 {4 fetch_block_id $end +$upscope $end +$scope struct \[243] $end +$var wire 8 |4 fetch_block_id $end +$upscope $end +$scope struct \[244] $end +$var wire 8 }4 fetch_block_id $end +$upscope $end +$scope struct \[245] $end +$var wire 8 ~4 fetch_block_id $end +$upscope $end +$scope struct \[246] $end +$var wire 8 !5 fetch_block_id $end +$upscope $end +$scope struct \[247] $end +$var wire 8 "5 fetch_block_id $end +$upscope $end +$scope struct \[248] $end +$var wire 8 #5 fetch_block_id $end +$upscope $end +$scope struct \[249] $end +$var wire 8 $5 fetch_block_id $end +$upscope $end +$scope struct \[250] $end +$var wire 8 %5 fetch_block_id $end +$upscope $end +$scope struct \[251] $end +$var wire 8 &5 fetch_block_id $end +$upscope $end +$scope struct \[252] $end +$var wire 8 '5 fetch_block_id $end +$upscope $end +$scope struct \[253] $end +$var wire 8 (5 fetch_block_id $end +$upscope $end +$scope struct \[254] $end +$var wire 8 )5 fetch_block_id $end +$upscope $end +$scope struct \[255] $end +$var wire 8 *5 fetch_block_id $end +$upscope $end +$upscope $end +$scope struct head $end +$var wire 8 +5 value $end +$var string 1 ,5 range $end +$upscope $end +$scope struct tail $end +$var wire 8 -5 value $end +$var string 1 .5 range $end +$upscope $end +$upscope $end +$var wire 1 /5 cancel_in_progress_fetches $end +$var wire 64 05 pc $end +$var wire 8 15 fetch_block_id $end +$var string 1 25 config $end +$upscope $end +$upscope $end +$scope module next_pc_2 $end +$scope struct cd $end +$var wire 1 # clk $end +$var wire 1 $ rst $end +$upscope $end +$scope struct to_fetch $end +$scope struct inner $end +$scope struct data $end +$var string 1 % \$tag $end +$scope struct HdlSome $end +$var wire 64 & next_fetch_pc $end +$var wire 8 ' fetch_block_id $end +$var wire 8 ( in_progress_fetches_to_cancel $end +$upscope $end +$upscope $end +$var wire 1 ) ready $end +$upscope $end +$var string 1 * config $end +$upscope $end +$scope struct from_decode $end +$scope struct inner $end +$scope struct data $end +$var string 1 + \$tag $end +$scope struct HdlSome $end +$var wire 8 , fetch_block_id $end +$scope struct insns $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 8 - fetch_block_id $end +$var wire 12 . id $end +$var wire 64 / pc $end +$var wire 4 0 size_in_bytes $end +$scope struct kind $end +$var string 1 1 \$tag $end +$var wire 64 2 Branch $end +$var wire 64 3 BranchCond $end +$var wire 64 4 Call $end +$var wire 64 5 CallCond $end +$var wire 64 6 Interrupt $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 8 7 fetch_block_id $end +$var wire 12 8 id $end +$var wire 64 9 pc $end +$var wire 4 : size_in_bytes $end +$scope struct kind $end +$var string 1 ; \$tag $end +$var wire 64 < Branch $end +$var wire 64 = BranchCond $end +$var wire 64 > Call $end +$var wire 64 ? CallCond $end +$var wire 64 @ Interrupt $end +$upscope $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 A value $end +$var string 1 B range $end +$upscope $end +$upscope $end +$var string 1 C config $end +$upscope $end +$upscope $end +$var wire 1 D ready $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct speculative_call_stack $end +$scope struct return_addresses $end +$var wire 64 E \[0] $end +$var wire 64 F \[1] $end +$var wire 64 G \[2] $end +$var wire 64 H \[3] $end +$var wire 64 I \[4] $end +$var wire 64 J \[5] $end +$var wire 64 K \[6] $end +$var wire 64 L \[7] $end +$var wire 64 M \[8] $end +$var wire 64 N \[9] $end +$var wire 64 O \[10] $end +$var wire 64 P \[11] $end +$var wire 64 Q \[12] $end +$var wire 64 R \[13] $end +$var wire 64 S \[14] $end +$var wire 64 T \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 U value $end +$var string 1 V range $end +$upscope $end +$upscope $end +$scope struct non_speculative_call_stack $end +$scope struct return_addresses $end +$var wire 64 W \[0] $end +$var wire 64 X \[1] $end +$var wire 64 Y \[2] $end +$var wire 64 Z \[3] $end +$var wire 64 [ \[4] $end +$var wire 64 \ \[5] $end +$var wire 64 ] \[6] $end +$var wire 64 ^ \[7] $end +$var wire 64 _ \[8] $end +$var wire 64 ` \[9] $end +$var wire 64 a \[10] $end +$var wire 64 b \[11] $end +$var wire 64 c \[12] $end +$var wire 64 d \[13] $end +$var wire 64 e \[14] $end +$var wire 64 f \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 g value $end +$var string 1 h range $end +$upscope $end +$upscope $end +$scope struct branch_target_buffer $end +$scope struct branch_pc_to_target_map $end +$scope struct \[0] $end +$var string 1 i \$tag $end +$scope struct HdlSome $end +$var wire 64 j start_pc $end +$var wire 64 k target_pc $end +$var wire 8 l fallthrough_offset $end +$var string 1 m insn_kind $end +$var string 1 n addr_kind $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 o \$tag $end +$scope struct HdlSome $end +$var wire 64 p start_pc $end +$var wire 64 q target_pc $end +$var wire 8 r fallthrough_offset $end +$var string 1 s insn_kind $end +$var string 1 t addr_kind $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 u \$tag $end +$scope struct HdlSome $end +$var wire 64 v start_pc $end +$var wire 64 w target_pc $end +$var wire 8 x fallthrough_offset $end +$var string 1 y insn_kind $end +$var string 1 z addr_kind $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 { \$tag $end +$scope struct HdlSome $end +$var wire 64 | start_pc $end +$var wire 64 } target_pc $end +$var wire 8 ~ fallthrough_offset $end +$var string 1 !" insn_kind $end +$var string 1 "" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 #" \$tag $end +$scope struct HdlSome $end +$var wire 64 $" start_pc $end +$var wire 64 %" target_pc $end +$var wire 8 &" fallthrough_offset $end +$var string 1 '" insn_kind $end +$var string 1 (" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 )" \$tag $end +$scope struct HdlSome $end +$var wire 64 *" start_pc $end +$var wire 64 +" target_pc $end +$var wire 8 ," fallthrough_offset $end +$var string 1 -" insn_kind $end +$var string 1 ." addr_kind $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$var string 1 /" \$tag $end +$scope struct HdlSome $end +$var wire 64 0" start_pc $end +$var wire 64 1" target_pc $end +$var wire 8 2" fallthrough_offset $end +$var string 1 3" insn_kind $end +$var string 1 4" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$var string 1 5" \$tag $end +$scope struct HdlSome $end +$var wire 64 6" start_pc $end +$var wire 64 7" target_pc $end +$var wire 8 8" fallthrough_offset $end +$var string 1 9" insn_kind $end +$var string 1 :" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$var string 1 ;" \$tag $end +$scope struct HdlSome $end +$var wire 64 <" start_pc $end +$var wire 64 =" target_pc $end +$var wire 8 >" fallthrough_offset $end +$var string 1 ?" insn_kind $end +$var string 1 @" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[9] $end +$var string 1 A" \$tag $end +$scope struct HdlSome $end +$var wire 64 B" start_pc $end +$var wire 64 C" target_pc $end +$var wire 8 D" fallthrough_offset $end +$var string 1 E" insn_kind $end +$var string 1 F" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$var string 1 G" \$tag $end +$scope struct HdlSome $end +$var wire 64 H" start_pc $end +$var wire 64 I" target_pc $end +$var wire 8 J" fallthrough_offset $end +$var string 1 K" insn_kind $end +$var string 1 L" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$var string 1 M" \$tag $end +$scope struct HdlSome $end +$var wire 64 N" start_pc $end +$var wire 64 O" target_pc $end +$var wire 8 P" fallthrough_offset $end +$var string 1 Q" insn_kind $end +$var string 1 R" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$var string 1 S" \$tag $end +$scope struct HdlSome $end +$var wire 64 T" start_pc $end +$var wire 64 U" target_pc $end +$var wire 8 V" fallthrough_offset $end +$var string 1 W" insn_kind $end +$var string 1 X" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[13] $end +$var string 1 Y" \$tag $end +$scope struct HdlSome $end +$var wire 64 Z" start_pc $end +$var wire 64 [" target_pc $end +$var wire 8 \" fallthrough_offset $end +$var string 1 ]" insn_kind $end +$var string 1 ^" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$var string 1 _" \$tag $end +$scope struct HdlSome $end +$var wire 64 `" start_pc $end +$var wire 64 a" target_pc $end +$var wire 8 b" fallthrough_offset $end +$var string 1 c" insn_kind $end +$var string 1 d" addr_kind $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$var string 1 e" \$tag $end +$scope struct HdlSome $end +$var wire 64 f" start_pc $end +$var wire 64 g" target_pc $end +$var wire 8 h" fallthrough_offset $end +$var string 1 i" insn_kind $end +$var string 1 j" addr_kind $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct branch_history $end +$scope struct history $end +$var wire 1 k" \[0] $end +$var wire 1 l" \[1] $end +$var wire 1 m" \[2] $end +$var wire 1 n" \[3] $end +$var wire 1 o" \[4] $end +$var wire 1 p" \[5] $end +$var wire 1 q" \[6] $end +$var wire 1 r" \[7] $end +$var wire 1 s" \[8] $end +$var wire 1 t" \[9] $end +$var wire 1 u" \[10] $end +$var wire 1 v" \[11] $end +$var wire 1 w" \[12] $end +$var wire 1 x" \[13] $end +$var wire 1 y" \[14] $end +$var wire 1 z" \[15] $end +$var wire 1 {" \[16] $end +$var wire 1 |" \[17] $end +$var wire 1 }" \[18] $end +$var wire 1 ~" \[19] $end +$var wire 1 !# \[20] $end +$var wire 1 "# \[21] $end +$var wire 1 ## \[22] $end +$var wire 1 $# \[23] $end +$var wire 1 %# \[24] $end +$var wire 1 &# \[25] $end +$var wire 1 '# \[26] $end +$var wire 1 (# \[27] $end +$var wire 1 )# \[28] $end +$var wire 1 *# \[29] $end +$var wire 1 +# \[30] $end +$var wire 1 ,# \[31] $end +$var wire 1 -# \[32] $end +$var wire 1 .# \[33] $end +$var wire 1 /# \[34] $end +$var wire 1 0# \[35] $end +$var wire 1 1# \[36] $end +$var wire 1 2# \[37] $end +$var wire 1 3# \[38] $end +$var wire 1 4# \[39] $end +$var wire 1 5# \[40] $end +$var wire 1 6# \[41] $end +$var wire 1 7# \[42] $end +$var wire 1 8# \[43] $end +$var wire 1 9# \[44] $end +$var wire 1 :# \[45] $end +$var wire 1 ;# \[46] $end +$var wire 1 <# \[47] $end +$var wire 1 =# \[48] $end +$var wire 1 ># \[49] $end +$var wire 1 ?# \[50] $end +$var wire 1 @# \[51] $end +$var wire 1 A# \[52] $end +$var wire 1 B# \[53] $end +$var wire 1 C# \[54] $end +$var wire 1 D# \[55] $end +$var wire 1 E# \[56] $end +$var wire 1 F# \[57] $end +$var wire 1 G# \[58] $end +$var wire 1 H# \[59] $end +$var wire 1 I# \[60] $end +$var wire 1 J# \[61] $end +$var wire 1 K# \[62] $end +$var wire 1 L# \[63] $end +$var wire 1 M# \[64] $end +$var wire 1 N# \[65] $end +$var wire 1 O# \[66] $end +$var wire 1 P# \[67] $end +$var wire 1 Q# \[68] $end +$var wire 1 R# \[69] $end +$var wire 1 S# \[70] $end +$var wire 1 T# \[71] $end +$var wire 1 U# \[72] $end +$var wire 1 V# \[73] $end +$var wire 1 W# \[74] $end +$var wire 1 X# \[75] $end +$var wire 1 Y# \[76] $end +$var wire 1 Z# \[77] $end +$var wire 1 [# \[78] $end +$var wire 1 \# \[79] $end +$var wire 1 ]# \[80] $end +$var wire 1 ^# \[81] $end +$var wire 1 _# \[82] $end +$var wire 1 `# \[83] $end +$var wire 1 a# \[84] $end +$var wire 1 b# \[85] $end +$var wire 1 c# \[86] $end +$var wire 1 d# \[87] $end +$var wire 1 e# \[88] $end +$var wire 1 f# \[89] $end +$var wire 1 g# \[90] $end +$var wire 1 h# \[91] $end +$var wire 1 i# \[92] $end +$var wire 1 j# \[93] $end +$var wire 1 k# \[94] $end +$var wire 1 l# \[95] $end +$var wire 1 m# \[96] $end +$var wire 1 n# \[97] $end +$var wire 1 o# \[98] $end +$var wire 1 p# \[99] $end +$var wire 1 q# \[100] $end +$var wire 1 r# \[101] $end +$var wire 1 s# \[102] $end +$var wire 1 t# \[103] $end +$var wire 1 u# \[104] $end +$var wire 1 v# \[105] $end +$var wire 1 w# \[106] $end +$var wire 1 x# \[107] $end +$var wire 1 y# \[108] $end +$var wire 1 z# \[109] $end +$var wire 1 {# \[110] $end +$var wire 1 |# \[111] $end +$var wire 1 }# \[112] $end +$var wire 1 ~# \[113] $end +$var wire 1 !$ \[114] $end +$var wire 1 "$ \[115] $end +$var wire 1 #$ \[116] $end +$var wire 1 $$ \[117] $end +$var wire 1 %$ \[118] $end +$var wire 1 &$ \[119] $end +$var wire 1 '$ \[120] $end +$var wire 1 ($ \[121] $end +$var wire 1 )$ \[122] $end +$var wire 1 *$ \[123] $end +$var wire 1 +$ \[124] $end +$var wire 1 ,$ \[125] $end +$var wire 1 -$ \[126] $end +$var wire 1 .$ \[127] $end +$var wire 1 /$ \[128] $end +$var wire 1 0$ \[129] $end +$var wire 1 1$ \[130] $end +$var wire 1 2$ \[131] $end +$var wire 1 3$ \[132] $end +$var wire 1 4$ \[133] $end +$var wire 1 5$ \[134] $end +$var wire 1 6$ \[135] $end +$var wire 1 7$ \[136] $end +$var wire 1 8$ \[137] $end +$var wire 1 9$ \[138] $end +$var wire 1 :$ \[139] $end +$var wire 1 ;$ \[140] $end +$var wire 1 <$ \[141] $end +$var wire 1 =$ \[142] $end +$var wire 1 >$ \[143] $end +$var wire 1 ?$ \[144] $end +$var wire 1 @$ \[145] $end +$var wire 1 A$ \[146] $end +$var wire 1 B$ \[147] $end +$var wire 1 C$ \[148] $end +$var wire 1 D$ \[149] $end +$var wire 1 E$ \[150] $end +$var wire 1 F$ \[151] $end +$var wire 1 G$ \[152] $end +$var wire 1 H$ \[153] $end +$var wire 1 I$ \[154] $end +$var wire 1 J$ \[155] $end +$var wire 1 K$ \[156] $end +$var wire 1 L$ \[157] $end +$var wire 1 M$ \[158] $end +$var wire 1 N$ \[159] $end +$var wire 1 O$ \[160] $end +$var wire 1 P$ \[161] $end +$var wire 1 Q$ \[162] $end +$var wire 1 R$ \[163] $end +$var wire 1 S$ \[164] $end +$var wire 1 T$ \[165] $end +$var wire 1 U$ \[166] $end +$var wire 1 V$ \[167] $end +$var wire 1 W$ \[168] $end +$var wire 1 X$ \[169] $end +$var wire 1 Y$ \[170] $end +$var wire 1 Z$ \[171] $end +$var wire 1 [$ \[172] $end +$var wire 1 \$ \[173] $end +$var wire 1 ]$ \[174] $end +$var wire 1 ^$ \[175] $end +$var wire 1 _$ \[176] $end +$var wire 1 `$ \[177] $end +$var wire 1 a$ \[178] $end +$var wire 1 b$ \[179] $end +$var wire 1 c$ \[180] $end +$var wire 1 d$ \[181] $end +$var wire 1 e$ \[182] $end +$var wire 1 f$ \[183] $end +$var wire 1 g$ \[184] $end +$var wire 1 h$ \[185] $end +$var wire 1 i$ \[186] $end +$var wire 1 j$ \[187] $end +$var wire 1 k$ \[188] $end +$var wire 1 l$ \[189] $end +$var wire 1 m$ \[190] $end +$var wire 1 n$ \[191] $end +$var wire 1 o$ \[192] $end +$var wire 1 p$ \[193] $end +$var wire 1 q$ \[194] $end +$var wire 1 r$ \[195] $end +$var wire 1 s$ \[196] $end +$var wire 1 t$ \[197] $end +$var wire 1 u$ \[198] $end +$var wire 1 v$ \[199] $end +$var wire 1 w$ \[200] $end +$var wire 1 x$ \[201] $end +$var wire 1 y$ \[202] $end +$var wire 1 z$ \[203] $end +$var wire 1 {$ \[204] $end +$var wire 1 |$ \[205] $end +$var wire 1 }$ \[206] $end +$var wire 1 ~$ \[207] $end +$var wire 1 !% \[208] $end +$var wire 1 "% \[209] $end +$var wire 1 #% \[210] $end +$var wire 1 $% \[211] $end +$var wire 1 %% \[212] $end +$var wire 1 &% \[213] $end +$var wire 1 '% \[214] $end +$var wire 1 (% \[215] $end +$var wire 1 )% \[216] $end +$var wire 1 *% \[217] $end +$var wire 1 +% \[218] $end +$var wire 1 ,% \[219] $end +$var wire 1 -% \[220] $end +$var wire 1 .% \[221] $end +$var wire 1 /% \[222] $end +$var wire 1 0% \[223] $end +$var wire 1 1% \[224] $end +$var wire 1 2% \[225] $end +$var wire 1 3% \[226] $end +$var wire 1 4% \[227] $end +$var wire 1 5% \[228] $end +$var wire 1 6% \[229] $end +$var wire 1 7% \[230] $end +$var wire 1 8% \[231] $end +$var wire 1 9% \[232] $end +$var wire 1 :% \[233] $end +$var wire 1 ;% \[234] $end +$var wire 1 <% \[235] $end +$var wire 1 =% \[236] $end +$var wire 1 >% \[237] $end +$var wire 1 ?% \[238] $end +$var wire 1 @% \[239] $end +$var wire 1 A% \[240] $end +$var wire 1 B% \[241] $end +$var wire 1 C% \[242] $end +$var wire 1 D% \[243] $end +$var wire 1 E% \[244] $end +$var wire 1 F% \[245] $end +$var wire 1 G% \[246] $end +$var wire 1 H% \[247] $end +$var wire 1 I% \[248] $end +$var wire 1 J% \[249] $end +$var wire 1 K% \[250] $end +$var wire 1 L% \[251] $end +$var wire 1 M% \[252] $end +$var wire 1 N% \[253] $end +$var wire 1 O% \[254] $end +$var wire 1 P% \[255] $end +$upscope $end +$scope struct tail $end +$var wire 8 Q% value $end +$var string 1 R% range $end +$upscope $end +$scope struct non_speculative_head $end +$var wire 8 S% value $end +$var string 1 T% range $end +$upscope $end +$scope struct speculative_head $end +$var wire 8 U% value $end +$var string 1 V% range $end +$upscope $end +$upscope $end +$scope struct branch_predictor $end +$var string 1 W% \[0] $end +$var string 1 X% \[1] $end +$var string 1 Y% \[2] $end +$var string 1 Z% \[3] $end +$var string 1 [% \[4] $end +$var string 1 \% \[5] $end +$var string 1 ]% \[6] $end +$var string 1 ^% \[7] $end +$var string 1 _% \[8] $end +$var string 1 `% \[9] $end +$var string 1 a% \[10] $end +$var string 1 b% \[11] $end +$var string 1 c% \[12] $end +$var string 1 d% \[13] $end +$var string 1 e% \[14] $end +$var string 1 f% \[15] $end +$var string 1 g% \[16] $end +$var string 1 h% \[17] $end +$var string 1 i% \[18] $end +$var string 1 j% \[19] $end +$var string 1 k% \[20] $end +$var string 1 l% \[21] $end +$var string 1 m% \[22] $end +$var string 1 n% \[23] $end +$var string 1 o% \[24] $end +$var string 1 p% \[25] $end +$var string 1 q% \[26] $end +$var string 1 r% \[27] $end +$var string 1 s% \[28] $end +$var string 1 t% \[29] $end +$var string 1 u% \[30] $end +$var string 1 v% \[31] $end +$var string 1 w% \[32] $end +$var string 1 x% \[33] $end +$var string 1 y% \[34] $end +$var string 1 z% \[35] $end +$var string 1 {% \[36] $end +$var string 1 |% \[37] $end +$var string 1 }% \[38] $end +$var string 1 ~% \[39] $end +$var string 1 !& \[40] $end +$var string 1 "& \[41] $end +$var string 1 #& \[42] $end +$var string 1 $& \[43] $end +$var string 1 %& \[44] $end +$var string 1 && \[45] $end +$var string 1 '& \[46] $end +$var string 1 (& \[47] $end +$var string 1 )& \[48] $end +$var string 1 *& \[49] $end +$var string 1 +& \[50] $end +$var string 1 ,& \[51] $end +$var string 1 -& \[52] $end +$var string 1 .& \[53] $end +$var string 1 /& \[54] $end +$var string 1 0& \[55] $end +$var string 1 1& \[56] $end +$var string 1 2& \[57] $end +$var string 1 3& \[58] $end +$var string 1 4& \[59] $end +$var string 1 5& \[60] $end +$var string 1 6& \[61] $end +$var string 1 7& \[62] $end +$var string 1 8& \[63] $end +$var string 1 9& \[64] $end +$var string 1 :& \[65] $end +$var string 1 ;& \[66] $end +$var string 1 <& \[67] $end +$var string 1 =& \[68] $end +$var string 1 >& \[69] $end +$var string 1 ?& \[70] $end +$var string 1 @& \[71] $end +$var string 1 A& \[72] $end +$var string 1 B& \[73] $end +$var string 1 C& \[74] $end +$var string 1 D& \[75] $end +$var string 1 E& \[76] $end +$var string 1 F& \[77] $end +$var string 1 G& \[78] $end +$var string 1 H& \[79] $end +$var string 1 I& \[80] $end +$var string 1 J& \[81] $end +$var string 1 K& \[82] $end +$var string 1 L& \[83] $end +$var string 1 M& \[84] $end +$var string 1 N& \[85] $end +$var string 1 O& \[86] $end +$var string 1 P& \[87] $end +$var string 1 Q& \[88] $end +$var string 1 R& \[89] $end +$var string 1 S& \[90] $end +$var string 1 T& \[91] $end +$var string 1 U& \[92] $end +$var string 1 V& \[93] $end +$var string 1 W& \[94] $end +$var string 1 X& \[95] $end +$var string 1 Y& \[96] $end +$var string 1 Z& \[97] $end +$var string 1 [& \[98] $end +$var string 1 \& \[99] $end +$var string 1 ]& \[100] $end +$var string 1 ^& \[101] $end +$var string 1 _& \[102] $end +$var string 1 `& \[103] $end +$var string 1 a& \[104] $end +$var string 1 b& \[105] $end +$var string 1 c& \[106] $end +$var string 1 d& \[107] $end +$var string 1 e& \[108] $end +$var string 1 f& \[109] $end +$var string 1 g& \[110] $end +$var string 1 h& \[111] $end +$var string 1 i& \[112] $end +$var string 1 j& \[113] $end +$var string 1 k& \[114] $end +$var string 1 l& \[115] $end +$var string 1 m& \[116] $end +$var string 1 n& \[117] $end +$var string 1 o& \[118] $end +$var string 1 p& \[119] $end +$var string 1 q& \[120] $end +$var string 1 r& \[121] $end +$var string 1 s& \[122] $end +$var string 1 t& \[123] $end +$var string 1 u& \[124] $end +$var string 1 v& \[125] $end +$var string 1 w& \[126] $end +$var string 1 x& \[127] $end +$var string 1 y& \[128] $end +$var string 1 z& \[129] $end +$var string 1 {& \[130] $end +$var string 1 |& \[131] $end +$var string 1 }& \[132] $end +$var string 1 ~& \[133] $end +$var string 1 !' \[134] $end +$var string 1 "' \[135] $end +$var string 1 #' \[136] $end +$var string 1 $' \[137] $end +$var string 1 %' \[138] $end +$var string 1 &' \[139] $end +$var string 1 '' \[140] $end +$var string 1 (' \[141] $end +$var string 1 )' \[142] $end +$var string 1 *' \[143] $end +$var string 1 +' \[144] $end +$var string 1 ,' \[145] $end +$var string 1 -' \[146] $end +$var string 1 .' \[147] $end +$var string 1 /' \[148] $end +$var string 1 0' \[149] $end +$var string 1 1' \[150] $end +$var string 1 2' \[151] $end +$var string 1 3' \[152] $end +$var string 1 4' \[153] $end +$var string 1 5' \[154] $end +$var string 1 6' \[155] $end +$var string 1 7' \[156] $end +$var string 1 8' \[157] $end +$var string 1 9' \[158] $end +$var string 1 :' \[159] $end +$var string 1 ;' \[160] $end +$var string 1 <' \[161] $end +$var string 1 =' \[162] $end +$var string 1 >' \[163] $end +$var string 1 ?' \[164] $end +$var string 1 @' \[165] $end +$var string 1 A' \[166] $end +$var string 1 B' \[167] $end +$var string 1 C' \[168] $end +$var string 1 D' \[169] $end +$var string 1 E' \[170] $end +$var string 1 F' \[171] $end +$var string 1 G' \[172] $end +$var string 1 H' \[173] $end +$var string 1 I' \[174] $end +$var string 1 J' \[175] $end +$var string 1 K' \[176] $end +$var string 1 L' \[177] $end +$var string 1 M' \[178] $end +$var string 1 N' \[179] $end +$var string 1 O' \[180] $end +$var string 1 P' \[181] $end +$var string 1 Q' \[182] $end +$var string 1 R' \[183] $end +$var string 1 S' \[184] $end +$var string 1 T' \[185] $end +$var string 1 U' \[186] $end +$var string 1 V' \[187] $end +$var string 1 W' \[188] $end +$var string 1 X' \[189] $end +$var string 1 Y' \[190] $end +$var string 1 Z' \[191] $end +$var string 1 [' \[192] $end +$var string 1 \' \[193] $end +$var string 1 ]' \[194] $end +$var string 1 ^' \[195] $end +$var string 1 _' \[196] $end +$var string 1 `' \[197] $end +$var string 1 a' \[198] $end +$var string 1 b' \[199] $end +$var string 1 c' \[200] $end +$var string 1 d' \[201] $end +$var string 1 e' \[202] $end +$var string 1 f' \[203] $end +$var string 1 g' \[204] $end +$var string 1 h' \[205] $end +$var string 1 i' \[206] $end +$var string 1 j' \[207] $end +$var string 1 k' \[208] $end +$var string 1 l' \[209] $end +$var string 1 m' \[210] $end +$var string 1 n' \[211] $end +$var string 1 o' \[212] $end +$var string 1 p' \[213] $end +$var string 1 q' \[214] $end +$var string 1 r' \[215] $end +$var string 1 s' \[216] $end +$var string 1 t' \[217] $end +$var string 1 u' \[218] $end +$var string 1 v' \[219] $end +$var string 1 w' \[220] $end +$var string 1 x' \[221] $end +$var string 1 y' \[222] $end +$var string 1 z' \[223] $end +$var string 1 {' \[224] $end +$var string 1 |' \[225] $end +$var string 1 }' \[226] $end +$var string 1 ~' \[227] $end +$var string 1 !( \[228] $end +$var string 1 "( \[229] $end +$var string 1 #( \[230] $end +$var string 1 $( \[231] $end +$var string 1 %( \[232] $end +$var string 1 &( \[233] $end +$var string 1 '( \[234] $end +$var string 1 (( \[235] $end +$var string 1 )( \[236] $end +$var string 1 *( \[237] $end +$var string 1 +( \[238] $end +$var string 1 ,( \[239] $end +$var string 1 -( \[240] $end +$var string 1 .( \[241] $end +$var string 1 /( \[242] $end +$var string 1 0( \[243] $end +$var string 1 1( \[244] $end +$var string 1 2( \[245] $end +$var string 1 3( \[246] $end +$var string 1 4( \[247] $end +$var string 1 5( \[248] $end +$var string 1 6( \[249] $end +$var string 1 7( \[250] $end +$var string 1 8( \[251] $end +$var string 1 9( \[252] $end +$var string 1 :( \[253] $end +$var string 1 ;( \[254] $end +$var string 1 <( \[255] $end +$upscope $end +$scope struct fetching_queue $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 =( fetch_block_id $end +$upscope $end +$scope struct \[1] $end +$var wire 8 >( fetch_block_id $end +$upscope $end +$scope struct \[2] $end +$var wire 8 ?( fetch_block_id $end +$upscope $end +$scope struct \[3] $end +$var wire 8 @( fetch_block_id $end +$upscope $end +$scope struct \[4] $end +$var wire 8 A( fetch_block_id $end +$upscope $end +$scope struct \[5] $end +$var wire 8 B( fetch_block_id $end +$upscope $end +$scope struct \[6] $end +$var wire 8 C( fetch_block_id $end +$upscope $end +$scope struct \[7] $end +$var wire 8 D( fetch_block_id $end +$upscope $end +$scope struct \[8] $end +$var wire 8 E( fetch_block_id $end +$upscope $end +$scope struct \[9] $end +$var wire 8 F( fetch_block_id $end +$upscope $end +$scope struct \[10] $end +$var wire 8 G( fetch_block_id $end +$upscope $end +$scope struct \[11] $end +$var wire 8 H( fetch_block_id $end +$upscope $end +$scope struct \[12] $end +$var wire 8 I( fetch_block_id $end +$upscope $end +$scope struct \[13] $end +$var wire 8 J( fetch_block_id $end +$upscope $end +$scope struct \[14] $end +$var wire 8 K( fetch_block_id $end +$upscope $end +$scope struct \[15] $end +$var wire 8 L( fetch_block_id $end +$upscope $end +$scope struct \[16] $end +$var wire 8 M( fetch_block_id $end +$upscope $end +$scope struct \[17] $end +$var wire 8 N( fetch_block_id $end +$upscope $end +$scope struct \[18] $end +$var wire 8 O( fetch_block_id $end +$upscope $end +$scope struct \[19] $end +$var wire 8 P( fetch_block_id $end +$upscope $end +$scope struct \[20] $end +$var wire 8 Q( fetch_block_id $end +$upscope $end +$scope struct \[21] $end +$var wire 8 R( fetch_block_id $end +$upscope $end +$scope struct \[22] $end +$var wire 8 S( fetch_block_id $end +$upscope $end +$scope struct \[23] $end +$var wire 8 T( fetch_block_id $end +$upscope $end +$scope struct \[24] $end +$var wire 8 U( fetch_block_id $end +$upscope $end +$scope struct \[25] $end +$var wire 8 V( fetch_block_id $end +$upscope $end +$scope struct \[26] $end +$var wire 8 W( fetch_block_id $end +$upscope $end +$scope struct \[27] $end +$var wire 8 X( fetch_block_id $end +$upscope $end +$scope struct \[28] $end +$var wire 8 Y( fetch_block_id $end +$upscope $end +$scope struct \[29] $end +$var wire 8 Z( fetch_block_id $end +$upscope $end +$scope struct \[30] $end +$var wire 8 [( fetch_block_id $end +$upscope $end +$scope struct \[31] $end +$var wire 8 \( fetch_block_id $end +$upscope $end +$scope struct \[32] $end +$var wire 8 ]( fetch_block_id $end +$upscope $end +$scope struct \[33] $end +$var wire 8 ^( fetch_block_id $end +$upscope $end +$scope struct \[34] $end +$var wire 8 _( fetch_block_id $end +$upscope $end +$scope struct \[35] $end +$var wire 8 `( fetch_block_id $end +$upscope $end +$scope struct \[36] $end +$var wire 8 a( fetch_block_id $end +$upscope $end +$scope struct \[37] $end +$var wire 8 b( fetch_block_id $end +$upscope $end +$scope struct \[38] $end +$var wire 8 c( fetch_block_id $end +$upscope $end +$scope struct \[39] $end +$var wire 8 d( fetch_block_id $end +$upscope $end +$scope struct \[40] $end +$var wire 8 e( fetch_block_id $end +$upscope $end +$scope struct \[41] $end +$var wire 8 f( fetch_block_id $end +$upscope $end +$scope struct \[42] $end +$var wire 8 g( fetch_block_id $end +$upscope $end +$scope struct \[43] $end +$var wire 8 h( fetch_block_id $end +$upscope $end +$scope struct \[44] $end +$var wire 8 i( fetch_block_id $end +$upscope $end +$scope struct \[45] $end +$var wire 8 j( fetch_block_id $end +$upscope $end +$scope struct \[46] $end +$var wire 8 k( fetch_block_id $end +$upscope $end +$scope struct \[47] $end +$var wire 8 l( fetch_block_id $end +$upscope $end +$scope struct \[48] $end +$var wire 8 m( fetch_block_id $end +$upscope $end +$scope struct \[49] $end +$var wire 8 n( fetch_block_id $end +$upscope $end +$scope struct \[50] $end +$var wire 8 o( fetch_block_id $end +$upscope $end +$scope struct \[51] $end +$var wire 8 p( fetch_block_id $end +$upscope $end +$scope struct \[52] $end +$var wire 8 q( fetch_block_id $end +$upscope $end +$scope struct \[53] $end +$var wire 8 r( fetch_block_id $end +$upscope $end +$scope struct \[54] $end +$var wire 8 s( fetch_block_id $end +$upscope $end +$scope struct \[55] $end +$var wire 8 t( fetch_block_id $end +$upscope $end +$scope struct \[56] $end +$var wire 8 u( fetch_block_id $end +$upscope $end +$scope struct \[57] $end +$var wire 8 v( fetch_block_id $end +$upscope $end +$scope struct \[58] $end +$var wire 8 w( fetch_block_id $end +$upscope $end +$scope struct \[59] $end +$var wire 8 x( fetch_block_id $end +$upscope $end +$scope struct \[60] $end +$var wire 8 y( fetch_block_id $end +$upscope $end +$scope struct \[61] $end +$var wire 8 z( fetch_block_id $end +$upscope $end +$scope struct \[62] $end +$var wire 8 {( fetch_block_id $end +$upscope $end +$scope struct \[63] $end +$var wire 8 |( fetch_block_id $end +$upscope $end +$scope struct \[64] $end +$var wire 8 }( fetch_block_id $end +$upscope $end +$scope struct \[65] $end +$var wire 8 ~( fetch_block_id $end +$upscope $end +$scope struct \[66] $end +$var wire 8 !) fetch_block_id $end +$upscope $end +$scope struct \[67] $end +$var wire 8 ") fetch_block_id $end +$upscope $end +$scope struct \[68] $end +$var wire 8 #) fetch_block_id $end +$upscope $end +$scope struct \[69] $end +$var wire 8 $) fetch_block_id $end +$upscope $end +$scope struct \[70] $end +$var wire 8 %) fetch_block_id $end +$upscope $end +$scope struct \[71] $end +$var wire 8 &) fetch_block_id $end +$upscope $end +$scope struct \[72] $end +$var wire 8 ') fetch_block_id $end +$upscope $end +$scope struct \[73] $end +$var wire 8 () fetch_block_id $end +$upscope $end +$scope struct \[74] $end +$var wire 8 )) fetch_block_id $end +$upscope $end +$scope struct \[75] $end +$var wire 8 *) fetch_block_id $end +$upscope $end +$scope struct \[76] $end +$var wire 8 +) fetch_block_id $end +$upscope $end +$scope struct \[77] $end +$var wire 8 ,) fetch_block_id $end +$upscope $end +$scope struct \[78] $end +$var wire 8 -) fetch_block_id $end +$upscope $end +$scope struct \[79] $end +$var wire 8 .) fetch_block_id $end +$upscope $end +$scope struct \[80] $end +$var wire 8 /) fetch_block_id $end +$upscope $end +$scope struct \[81] $end +$var wire 8 0) fetch_block_id $end +$upscope $end +$scope struct \[82] $end +$var wire 8 1) fetch_block_id $end +$upscope $end +$scope struct \[83] $end +$var wire 8 2) fetch_block_id $end +$upscope $end +$scope struct \[84] $end +$var wire 8 3) fetch_block_id $end +$upscope $end +$scope struct \[85] $end +$var wire 8 4) fetch_block_id $end +$upscope $end +$scope struct \[86] $end +$var wire 8 5) fetch_block_id $end +$upscope $end +$scope struct \[87] $end +$var wire 8 6) fetch_block_id $end +$upscope $end +$scope struct \[88] $end +$var wire 8 7) fetch_block_id $end +$upscope $end +$scope struct \[89] $end +$var wire 8 8) fetch_block_id $end +$upscope $end +$scope struct \[90] $end +$var wire 8 9) fetch_block_id $end +$upscope $end +$scope struct \[91] $end +$var wire 8 :) fetch_block_id $end +$upscope $end +$scope struct \[92] $end +$var wire 8 ;) fetch_block_id $end +$upscope $end +$scope struct \[93] $end +$var wire 8 <) fetch_block_id $end +$upscope $end +$scope struct \[94] $end +$var wire 8 =) fetch_block_id $end +$upscope $end +$scope struct \[95] $end +$var wire 8 >) fetch_block_id $end +$upscope $end +$scope struct \[96] $end +$var wire 8 ?) fetch_block_id $end +$upscope $end +$scope struct \[97] $end +$var wire 8 @) fetch_block_id $end +$upscope $end +$scope struct \[98] $end +$var wire 8 A) fetch_block_id $end +$upscope $end +$scope struct \[99] $end +$var wire 8 B) fetch_block_id $end +$upscope $end +$scope struct \[100] $end +$var wire 8 C) fetch_block_id $end +$upscope $end +$scope struct \[101] $end +$var wire 8 D) fetch_block_id $end +$upscope $end +$scope struct \[102] $end +$var wire 8 E) fetch_block_id $end +$upscope $end +$scope struct \[103] $end +$var wire 8 F) fetch_block_id $end +$upscope $end +$scope struct \[104] $end +$var wire 8 G) fetch_block_id $end +$upscope $end +$scope struct \[105] $end +$var wire 8 H) fetch_block_id $end +$upscope $end +$scope struct \[106] $end +$var wire 8 I) fetch_block_id $end +$upscope $end +$scope struct \[107] $end +$var wire 8 J) fetch_block_id $end +$upscope $end +$scope struct \[108] $end +$var wire 8 K) fetch_block_id $end +$upscope $end +$scope struct \[109] $end +$var wire 8 L) fetch_block_id $end +$upscope $end +$scope struct \[110] $end +$var wire 8 M) fetch_block_id $end +$upscope $end +$scope struct \[111] $end +$var wire 8 N) fetch_block_id $end +$upscope $end +$scope struct \[112] $end +$var wire 8 O) fetch_block_id $end +$upscope $end +$scope struct \[113] $end +$var wire 8 P) fetch_block_id $end +$upscope $end +$scope struct \[114] $end +$var wire 8 Q) fetch_block_id $end +$upscope $end +$scope struct \[115] $end +$var wire 8 R) fetch_block_id $end +$upscope $end +$scope struct \[116] $end +$var wire 8 S) fetch_block_id $end +$upscope $end +$scope struct \[117] $end +$var wire 8 T) fetch_block_id $end +$upscope $end +$scope struct \[118] $end +$var wire 8 U) fetch_block_id $end +$upscope $end +$scope struct \[119] $end +$var wire 8 V) fetch_block_id $end +$upscope $end +$scope struct \[120] $end +$var wire 8 W) fetch_block_id $end +$upscope $end +$scope struct \[121] $end +$var wire 8 X) fetch_block_id $end +$upscope $end +$scope struct \[122] $end +$var wire 8 Y) fetch_block_id $end +$upscope $end +$scope struct \[123] $end +$var wire 8 Z) fetch_block_id $end +$upscope $end +$scope struct \[124] $end +$var wire 8 [) fetch_block_id $end +$upscope $end +$scope struct \[125] $end +$var wire 8 \) fetch_block_id $end +$upscope $end +$scope struct \[126] $end +$var wire 8 ]) fetch_block_id $end +$upscope $end +$scope struct \[127] $end +$var wire 8 ^) fetch_block_id $end +$upscope $end +$scope struct \[128] $end +$var wire 8 _) fetch_block_id $end +$upscope $end +$scope struct \[129] $end +$var wire 8 `) fetch_block_id $end +$upscope $end +$scope struct \[130] $end +$var wire 8 a) fetch_block_id $end +$upscope $end +$scope struct \[131] $end +$var wire 8 b) fetch_block_id $end +$upscope $end +$scope struct \[132] $end +$var wire 8 c) fetch_block_id $end +$upscope $end +$scope struct \[133] $end +$var wire 8 d) fetch_block_id $end +$upscope $end +$scope struct \[134] $end +$var wire 8 e) fetch_block_id $end +$upscope $end +$scope struct \[135] $end +$var wire 8 f) fetch_block_id $end +$upscope $end +$scope struct \[136] $end +$var wire 8 g) fetch_block_id $end +$upscope $end +$scope struct \[137] $end +$var wire 8 h) fetch_block_id $end +$upscope $end +$scope struct \[138] $end +$var wire 8 i) fetch_block_id $end +$upscope $end +$scope struct \[139] $end +$var wire 8 j) fetch_block_id $end +$upscope $end +$scope struct \[140] $end +$var wire 8 k) fetch_block_id $end +$upscope $end +$scope struct \[141] $end +$var wire 8 l) fetch_block_id $end +$upscope $end +$scope struct \[142] $end +$var wire 8 m) fetch_block_id $end +$upscope $end +$scope struct \[143] $end +$var wire 8 n) fetch_block_id $end +$upscope $end +$scope struct \[144] $end +$var wire 8 o) fetch_block_id $end +$upscope $end +$scope struct \[145] $end +$var wire 8 p) fetch_block_id $end +$upscope $end +$scope struct \[146] $end +$var wire 8 q) fetch_block_id $end +$upscope $end +$scope struct \[147] $end +$var wire 8 r) fetch_block_id $end +$upscope $end +$scope struct \[148] $end +$var wire 8 s) fetch_block_id $end +$upscope $end +$scope struct \[149] $end +$var wire 8 t) fetch_block_id $end +$upscope $end +$scope struct \[150] $end +$var wire 8 u) fetch_block_id $end +$upscope $end +$scope struct \[151] $end +$var wire 8 v) fetch_block_id $end +$upscope $end +$scope struct \[152] $end +$var wire 8 w) fetch_block_id $end +$upscope $end +$scope struct \[153] $end +$var wire 8 x) fetch_block_id $end +$upscope $end +$scope struct \[154] $end +$var wire 8 y) fetch_block_id $end +$upscope $end +$scope struct \[155] $end +$var wire 8 z) fetch_block_id $end +$upscope $end +$scope struct \[156] $end +$var wire 8 {) fetch_block_id $end +$upscope $end +$scope struct \[157] $end +$var wire 8 |) fetch_block_id $end +$upscope $end +$scope struct \[158] $end +$var wire 8 }) fetch_block_id $end +$upscope $end +$scope struct \[159] $end +$var wire 8 ~) fetch_block_id $end +$upscope $end +$scope struct \[160] $end +$var wire 8 !* fetch_block_id $end +$upscope $end +$scope struct \[161] $end +$var wire 8 "* fetch_block_id $end +$upscope $end +$scope struct \[162] $end +$var wire 8 #* fetch_block_id $end +$upscope $end +$scope struct \[163] $end +$var wire 8 $* fetch_block_id $end +$upscope $end +$scope struct \[164] $end +$var wire 8 %* fetch_block_id $end +$upscope $end +$scope struct \[165] $end +$var wire 8 &* fetch_block_id $end +$upscope $end +$scope struct \[166] $end +$var wire 8 '* fetch_block_id $end +$upscope $end +$scope struct \[167] $end +$var wire 8 (* fetch_block_id $end +$upscope $end +$scope struct \[168] $end +$var wire 8 )* fetch_block_id $end +$upscope $end +$scope struct \[169] $end +$var wire 8 ** fetch_block_id $end +$upscope $end +$scope struct \[170] $end +$var wire 8 +* fetch_block_id $end +$upscope $end +$scope struct \[171] $end +$var wire 8 ,* fetch_block_id $end +$upscope $end +$scope struct \[172] $end +$var wire 8 -* fetch_block_id $end +$upscope $end +$scope struct \[173] $end +$var wire 8 .* fetch_block_id $end +$upscope $end +$scope struct \[174] $end +$var wire 8 /* fetch_block_id $end +$upscope $end +$scope struct \[175] $end +$var wire 8 0* fetch_block_id $end +$upscope $end +$scope struct \[176] $end +$var wire 8 1* fetch_block_id $end +$upscope $end +$scope struct \[177] $end +$var wire 8 2* fetch_block_id $end +$upscope $end +$scope struct \[178] $end +$var wire 8 3* fetch_block_id $end +$upscope $end +$scope struct \[179] $end +$var wire 8 4* fetch_block_id $end +$upscope $end +$scope struct \[180] $end +$var wire 8 5* fetch_block_id $end +$upscope $end +$scope struct \[181] $end +$var wire 8 6* fetch_block_id $end +$upscope $end +$scope struct \[182] $end +$var wire 8 7* fetch_block_id $end +$upscope $end +$scope struct \[183] $end +$var wire 8 8* fetch_block_id $end +$upscope $end +$scope struct \[184] $end +$var wire 8 9* fetch_block_id $end +$upscope $end +$scope struct \[185] $end +$var wire 8 :* fetch_block_id $end +$upscope $end +$scope struct \[186] $end +$var wire 8 ;* fetch_block_id $end +$upscope $end +$scope struct \[187] $end +$var wire 8 <* fetch_block_id $end +$upscope $end +$scope struct \[188] $end +$var wire 8 =* fetch_block_id $end +$upscope $end +$scope struct \[189] $end +$var wire 8 >* fetch_block_id $end +$upscope $end +$scope struct \[190] $end +$var wire 8 ?* fetch_block_id $end +$upscope $end +$scope struct \[191] $end +$var wire 8 @* fetch_block_id $end +$upscope $end +$scope struct \[192] $end +$var wire 8 A* fetch_block_id $end +$upscope $end +$scope struct \[193] $end +$var wire 8 B* fetch_block_id $end +$upscope $end +$scope struct \[194] $end +$var wire 8 C* fetch_block_id $end +$upscope $end +$scope struct \[195] $end +$var wire 8 D* fetch_block_id $end +$upscope $end +$scope struct \[196] $end +$var wire 8 E* fetch_block_id $end +$upscope $end +$scope struct \[197] $end +$var wire 8 F* fetch_block_id $end +$upscope $end +$scope struct \[198] $end +$var wire 8 G* fetch_block_id $end +$upscope $end +$scope struct \[199] $end +$var wire 8 H* fetch_block_id $end +$upscope $end +$scope struct \[200] $end +$var wire 8 I* fetch_block_id $end +$upscope $end +$scope struct \[201] $end +$var wire 8 J* fetch_block_id $end +$upscope $end +$scope struct \[202] $end +$var wire 8 K* fetch_block_id $end +$upscope $end +$scope struct \[203] $end +$var wire 8 L* fetch_block_id $end +$upscope $end +$scope struct \[204] $end +$var wire 8 M* fetch_block_id $end +$upscope $end +$scope struct \[205] $end +$var wire 8 N* fetch_block_id $end +$upscope $end +$scope struct \[206] $end +$var wire 8 O* fetch_block_id $end +$upscope $end +$scope struct \[207] $end +$var wire 8 P* fetch_block_id $end +$upscope $end +$scope struct \[208] $end +$var wire 8 Q* fetch_block_id $end +$upscope $end +$scope struct \[209] $end +$var wire 8 R* fetch_block_id $end +$upscope $end +$scope struct \[210] $end +$var wire 8 S* fetch_block_id $end +$upscope $end +$scope struct \[211] $end +$var wire 8 T* fetch_block_id $end +$upscope $end +$scope struct \[212] $end +$var wire 8 U* fetch_block_id $end +$upscope $end +$scope struct \[213] $end +$var wire 8 V* fetch_block_id $end +$upscope $end +$scope struct \[214] $end +$var wire 8 W* fetch_block_id $end +$upscope $end +$scope struct \[215] $end +$var wire 8 X* fetch_block_id $end +$upscope $end +$scope struct \[216] $end +$var wire 8 Y* fetch_block_id $end +$upscope $end +$scope struct \[217] $end +$var wire 8 Z* fetch_block_id $end +$upscope $end +$scope struct \[218] $end +$var wire 8 [* fetch_block_id $end +$upscope $end +$scope struct \[219] $end +$var wire 8 \* fetch_block_id $end +$upscope $end +$scope struct \[220] $end +$var wire 8 ]* fetch_block_id $end +$upscope $end +$scope struct \[221] $end +$var wire 8 ^* fetch_block_id $end +$upscope $end +$scope struct \[222] $end +$var wire 8 _* fetch_block_id $end +$upscope $end +$scope struct \[223] $end +$var wire 8 `* fetch_block_id $end +$upscope $end +$scope struct \[224] $end +$var wire 8 a* fetch_block_id $end +$upscope $end +$scope struct \[225] $end +$var wire 8 b* fetch_block_id $end +$upscope $end +$scope struct \[226] $end +$var wire 8 c* fetch_block_id $end +$upscope $end +$scope struct \[227] $end +$var wire 8 d* fetch_block_id $end +$upscope $end +$scope struct \[228] $end +$var wire 8 e* fetch_block_id $end +$upscope $end +$scope struct \[229] $end +$var wire 8 f* fetch_block_id $end +$upscope $end +$scope struct \[230] $end +$var wire 8 g* fetch_block_id $end +$upscope $end +$scope struct \[231] $end +$var wire 8 h* fetch_block_id $end +$upscope $end +$scope struct \[232] $end +$var wire 8 i* fetch_block_id $end +$upscope $end +$scope struct \[233] $end +$var wire 8 j* fetch_block_id $end +$upscope $end +$scope struct \[234] $end +$var wire 8 k* fetch_block_id $end +$upscope $end +$scope struct \[235] $end +$var wire 8 l* fetch_block_id $end +$upscope $end +$scope struct \[236] $end +$var wire 8 m* fetch_block_id $end +$upscope $end +$scope struct \[237] $end +$var wire 8 n* fetch_block_id $end +$upscope $end +$scope struct \[238] $end +$var wire 8 o* fetch_block_id $end +$upscope $end +$scope struct \[239] $end +$var wire 8 p* fetch_block_id $end +$upscope $end +$scope struct \[240] $end +$var wire 8 q* fetch_block_id $end +$upscope $end +$scope struct \[241] $end +$var wire 8 r* fetch_block_id $end +$upscope $end +$scope struct \[242] $end +$var wire 8 s* fetch_block_id $end +$upscope $end +$scope struct \[243] $end +$var wire 8 t* fetch_block_id $end +$upscope $end +$scope struct \[244] $end +$var wire 8 u* fetch_block_id $end +$upscope $end +$scope struct \[245] $end +$var wire 8 v* fetch_block_id $end +$upscope $end +$scope struct \[246] $end +$var wire 8 w* fetch_block_id $end +$upscope $end +$scope struct \[247] $end +$var wire 8 x* fetch_block_id $end +$upscope $end +$scope struct \[248] $end +$var wire 8 y* fetch_block_id $end +$upscope $end +$scope struct \[249] $end +$var wire 8 z* fetch_block_id $end +$upscope $end +$scope struct \[250] $end +$var wire 8 {* fetch_block_id $end +$upscope $end +$scope struct \[251] $end +$var wire 8 |* fetch_block_id $end +$upscope $end +$scope struct \[252] $end +$var wire 8 }* fetch_block_id $end +$upscope $end +$scope struct \[253] $end +$var wire 8 ~* fetch_block_id $end +$upscope $end +$scope struct \[254] $end +$var wire 8 !+ fetch_block_id $end +$upscope $end +$scope struct \[255] $end +$var wire 8 "+ fetch_block_id $end +$upscope $end +$upscope $end +$scope struct head $end +$var wire 8 #+ value $end +$var string 1 $+ range $end +$upscope $end +$scope struct tail $end +$var wire 8 %+ value $end +$var string 1 &+ range $end +$upscope $end +$upscope $end +$var wire 1 '+ cancel_in_progress_fetches $end +$var wire 64 (+ pc $end +$var wire 8 )+ fetch_block_id $end +$var string 1 *+ config $end +$upscope $end +$upscope $end +$scope struct mock_fetch_pipe $end +$scope struct cd $end +$var wire 1 f5 clk $end +$var wire 1 g5 rst $end +$upscope $end +$scope struct from_fetch $end +$scope struct inner $end +$scope struct data $end +$var string 1 h5 \$tag $end +$scope struct HdlSome $end +$var wire 64 i5 next_fetch_pc $end +$var wire 8 j5 fetch_block_id $end +$var wire 8 k5 in_progress_fetches_to_cancel $end +$upscope $end +$upscope $end +$var wire 1 l5 ready $end +$upscope $end +$var string 1 m5 config $end +$upscope $end +$scope struct to_post_decode $end +$scope struct inner $end +$scope struct data $end +$var string 1 n5 \$tag $end +$scope struct HdlSome $end +$var wire 8 o5 fetch_block_id $end +$scope struct insns $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 8 p5 fetch_block_id $end +$var wire 12 q5 id $end +$var wire 64 r5 pc $end +$var wire 4 s5 size_in_bytes $end +$scope struct kind $end +$var string 1 t5 \$tag $end +$var wire 64 u5 Branch $end +$var wire 64 v5 BranchCond $end +$var wire 64 w5 Call $end +$var wire 64 x5 CallCond $end +$var wire 64 y5 Interrupt $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 8 z5 fetch_block_id $end +$var wire 12 {5 id $end +$var wire 64 |5 pc $end +$var wire 4 }5 size_in_bytes $end +$scope struct kind $end +$var string 1 ~5 \$tag $end +$var wire 64 !6 Branch $end +$var wire 64 "6 BranchCond $end +$var wire 64 #6 Call $end +$var wire 64 $6 CallCond $end +$var wire 64 %6 Interrupt $end +$upscope $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 &6 value $end +$var string 1 '6 range $end +$upscope $end +$upscope $end +$var string 1 (6 config $end +$upscope $end +$upscope $end +$var wire 1 )6 ready $end +$upscope $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 *6 fetch_pc $end +$var wire 8 +6 cycles_left $end +$var wire 8 ,6 fetch_block_id $end +$upscope $end +$scope struct \[1] $end +$var wire 64 -6 fetch_pc $end +$var wire 8 .6 cycles_left $end +$var wire 8 /6 fetch_block_id $end +$upscope $end +$scope struct \[2] $end +$var wire 64 06 fetch_pc $end +$var wire 8 16 cycles_left $end +$var wire 8 26 fetch_block_id $end +$upscope $end +$scope struct \[3] $end +$var wire 64 36 fetch_pc $end +$var wire 8 46 cycles_left $end +$var wire 8 56 fetch_block_id $end +$upscope $end +$scope struct \[4] $end +$var wire 64 66 fetch_pc $end +$var wire 8 76 cycles_left $end +$var wire 8 86 fetch_block_id $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 3 96 value $end +$var string 1 :6 range $end +$upscope $end +$upscope $end +$upscope $end +$scope module mock_fetch_pipe_2 $end +$scope struct cd $end +$var wire 1 35 clk $end +$var wire 1 45 rst $end +$upscope $end +$scope struct from_fetch $end +$scope struct inner $end +$scope struct data $end +$var string 1 55 \$tag $end +$scope struct HdlSome $end +$var wire 64 65 next_fetch_pc $end +$var wire 8 75 fetch_block_id $end +$var wire 8 85 in_progress_fetches_to_cancel $end +$upscope $end +$upscope $end +$var wire 1 95 ready $end +$upscope $end +$var string 1 :5 config $end +$upscope $end +$scope struct to_post_decode $end +$scope struct inner $end +$scope struct data $end +$var string 1 ;5 \$tag $end +$scope struct HdlSome $end +$var wire 8 <5 fetch_block_id $end +$scope struct insns $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 8 =5 fetch_block_id $end +$var wire 12 >5 id $end +$var wire 64 ?5 pc $end +$var wire 4 @5 size_in_bytes $end +$scope struct kind $end +$var string 1 A5 \$tag $end +$var wire 64 B5 Branch $end +$var wire 64 C5 BranchCond $end +$var wire 64 D5 Call $end +$var wire 64 E5 CallCond $end +$var wire 64 F5 Interrupt $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var wire 8 G5 fetch_block_id $end +$var wire 12 H5 id $end +$var wire 64 I5 pc $end +$var wire 4 J5 size_in_bytes $end +$scope struct kind $end +$var string 1 K5 \$tag $end +$var wire 64 L5 Branch $end +$var wire 64 M5 BranchCond $end +$var wire 64 N5 Call $end +$var wire 64 O5 CallCond $end +$var wire 64 P5 Interrupt $end +$upscope $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 Q5 value $end +$var string 1 R5 range $end +$upscope $end +$upscope $end +$var string 1 S5 config $end +$upscope $end +$upscope $end +$var wire 1 T5 ready $end +$upscope $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 U5 fetch_pc $end +$var wire 8 V5 cycles_left $end +$var wire 8 W5 fetch_block_id $end +$upscope $end +$scope struct \[1] $end +$var wire 64 X5 fetch_pc $end +$var wire 8 Y5 cycles_left $end +$var wire 8 Z5 fetch_block_id $end +$upscope $end +$scope struct \[2] $end +$var wire 64 [5 fetch_pc $end +$var wire 8 \5 cycles_left $end +$var wire 8 ]5 fetch_block_id $end +$upscope $end +$scope struct \[3] $end +$var wire 64 ^5 fetch_pc $end +$var wire 8 _5 cycles_left $end +$var wire 8 `5 fetch_block_id $end +$upscope $end +$scope struct \[4] $end +$var wire 64 a5 fetch_pc $end +$var wire 8 b5 cycles_left $end +$var wire 8 c5 fetch_block_id $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 3 d5 value $end +$var string 1 e5 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +0# +1$ +sHdlNone\x20(0) % +b0 & +b0 ' +b0 ( +0) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) * +sHdlNone\x20(0) + +b0 , +b0 - +b0 . +b0 / +b0 0 +sNonBranch\x20(0) 1 +b0 2 +b0 3 +b0 4 +b0 5 +b0 6 +b0 7 +b0 8 +b0 9 +b0 : +sNonBranch\x20(0) ; +b0 < +b0 = +b0 > +b0 ? +b0 @ +b0 A +sPhantomConst(\"0..=2\") B +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) C +0D +b0 E +b0 F +b0 G +b0 H +b0 I +b0 J +b0 K +b0 L +b0 M +b0 N +b0 O +b0 P +b0 Q +b0 R +b0 S +b0 T +b0 U +sPhantomConst(\"0..=16\") V +b0 W +b0 X +b0 Y +b0 Z +b0 [ +b0 \ +b0 ] +b0 ^ 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+sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 25 +035 +145 +sHdlNone\x20(0) 55 +b0 65 +b0 75 +b0 85 +095 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :5 +sHdlNone\x20(0) ;5 +b0 <5 +b0 =5 +b0 >5 +b0 ?5 +b0 @5 +sNonBranch\x20(0) A5 +b0 B5 +b0 C5 +b0 D5 +b0 E5 +b0 F5 +b0 G5 +b0 H5 +b0 I5 +b0 J5 +sNonBranch\x20(0) K5 +b0 L5 +b0 M5 +b0 N5 +b0 O5 +b0 P5 +b0 Q5 +sPhantomConst(\"0..=2\") R5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) S5 +0T5 +b0 U5 +b0 V5 +b0 W5 +b0 X5 +b0 Y5 +b0 Z5 +b0 [5 +b0 \5 +b0 ]5 +b0 ^5 +b0 _5 +b0 `5 +b0 a5 +b0 b5 +b0 c5 +b0 d5 +sPhantomConst(\"0..=5\") e5 +0f5 +1g5 +sHdlNone\x20(0) h5 +b0 i5 +b0 j5 +b0 k5 +0l5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m5 +sHdlNone\x20(0) n5 +b0 o5 +b0 p5 +b0 q5 +b0 r5 +b0 s5 +sNonBranch\x20(0) t5 +b0 u5 +b0 v5 +b0 w5 +b0 x5 +b0 y5 +b0 z5 +b0 {5 +b0 |5 +b0 }5 +sNonBranch\x20(0) ~5 +b0 !6 +b0 "6 +b0 #6 +b0 $6 +b0 %6 +b0 &6 +sPhantomConst(\"0..=2\") '6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"log2_fetch_width_in_bytes\":3,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (6 +0)6 +b0 *6 +b0 +6 +b0 ,6 +b0 -6 +b0 .6 +b0 /6 +b0 06 +b0 16 +b0 26 +b0 36 +b0 46 +b0 56 +b0 66 +b0 76 +b0 86 +b0 96 +sPhantomConst(\"0..=5\") :6 +$end +b1111111111111111111111111111111111111111111111111111111111111111 E +b1111111111111111111111111111111111111111111111111111111111111111 F +b1111111111111111111111111111111111111111111111111111111111111111 G +b1111111111111111111111111111111111111111111111111111111111111111 H +b1111111111111111111111111111111111111111111111111111111111111111 I +b1111111111111111111111111111111111111111111111111111111111111111 J +b1111111111111111111111111111111111111111111111111111111111111111 K +b1111111111111111111111111111111111111111111111111111111111111111 L +b1111111111111111111111111111111111111111111111111111111111111111 M +b1111111111111111111111111111111111111111111111111111111111111111 N +b1111111111111111111111111111111111111111111111111111111111111111 O +b1111111111111111111111111111111111111111111111111111111111111111 P +b1111111111111111111111111111111111111111111111111111111111111111 Q +b1111111111111111111111111111111111111111111111111111111111111111 R +b1111111111111111111111111111111111111111111111111111111111111111 S +b1111111111111111111111111111111111111111111111111111111111111111 T +b1111111111111111111111111111111111111111111111111111111111111111 W +b1111111111111111111111111111111111111111111111111111111111111111 X +b1111111111111111111111111111111111111111111111111111111111111111 Y +b1111111111111111111111111111111111111111111111111111111111111111 Z +b1111111111111111111111111111111111111111111111111111111111111111 [ +b1111111111111111111111111111111111111111111111111111111111111111 \ +b1111111111111111111111111111111111111111111111111111111111111111 ] +b1111111111111111111111111111111111111111111111111111111111111111 ^ +b1111111111111111111111111111111111111111111111111111111111111111 _ +b1111111111111111111111111111111111111111111111111111111111111111 ` +b1111111111111111111111111111111111111111111111111111111111111111 a +b1111111111111111111111111111111111111111111111111111111111111111 b +b1111111111111111111111111111111111111111111111111111111111111111 c +b1111111111111111111111111111111111111111111111111111111111111111 d +b1111111111111111111111111111111111111111111111111111111111111111 e +b1111111111111111111111111111111111111111111111111111111111111111 f +sHdlSome\x20(1) i +b1111111111111111111111111111111111111111111111111111111111111111 j +b1111111111111111111111111111111111111111111111111111111111111111 k +b11111111 l +sCall\x20(1) m +sCondNotTaken\x20(3) n +sHdlSome\x20(1) o +b1111111111111111111111111111111111111111111111111111111111111111 p +b1111111111111111111111111111111111111111111111111111111111111111 q +b11111111 r +sCall\x20(1) s +sCondNotTaken\x20(3) t +sHdlSome\x20(1) u +b1111111111111111111111111111111111111111111111111111111111111111 v +b1111111111111111111111111111111111111111111111111111111111111111 w +b11111111 x +sCall\x20(1) y +sCondNotTaken\x20(3) z +sHdlSome\x20(1) { +b1111111111111111111111111111111111111111111111111111111111111111 | +b1111111111111111111111111111111111111111111111111111111111111111 } +b11111111 ~ +sCall\x20(1) !" +sCondNotTaken\x20(3) "" +sHdlSome\x20(1) #" +b1111111111111111111111111111111111111111111111111111111111111111 $" +b1111111111111111111111111111111111111111111111111111111111111111 %" +b11111111 &" +sCall\x20(1) '" +sCondNotTaken\x20(3) (" +sHdlSome\x20(1) )" +b1111111111111111111111111111111111111111111111111111111111111111 *" +b1111111111111111111111111111111111111111111111111111111111111111 +" +b11111111 ," +sCall\x20(1) -" +sCondNotTaken\x20(3) ." +sHdlSome\x20(1) /" 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I" +b11111111 J" +sCall\x20(1) K" +sCondNotTaken\x20(3) L" +sHdlSome\x20(1) M" +b1111111111111111111111111111111111111111111111111111111111111111 N" +b1111111111111111111111111111111111111111111111111111111111111111 O" +b11111111 P" +sCall\x20(1) Q" +sCondNotTaken\x20(3) R" +sHdlSome\x20(1) S" +b1111111111111111111111111111111111111111111111111111111111111111 T" +b1111111111111111111111111111111111111111111111111111111111111111 U" +b11111111 V" +sCall\x20(1) W" +sCondNotTaken\x20(3) X" +sHdlSome\x20(1) Y" +b1111111111111111111111111111111111111111111111111111111111111111 Z" +b1111111111111111111111111111111111111111111111111111111111111111 [" +b11111111 \" +sCall\x20(1) ]" +sCondNotTaken\x20(3) ^" +sHdlSome\x20(1) _" +b1111111111111111111111111111111111111111111111111111111111111111 `" +b1111111111111111111111111111111111111111111111111111111111111111 a" +b11111111 b" +sCall\x20(1) c" +sCondNotTaken\x20(3) d" +sHdlSome\x20(1) e" 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+b1111111111111111111111111111111111111111111111111111111111111111 S+ +b1111111111111111111111111111111111111111111111111111111111111111 T+ +b1111111111111111111111111111111111111111111111111111111111111111 U+ +b1111111111111111111111111111111111111111111111111111111111111111 V+ +b1111111111111111111111111111111111111111111111111111111111111111 W+ +b1111111111111111111111111111111111111111111111111111111111111111 X+ +b1111111111111111111111111111111111111111111111111111111111111111 Y+ +b1111111111111111111111111111111111111111111111111111111111111111 Z+ +b1111111111111111111111111111111111111111111111111111111111111111 [+ +b1111111111111111111111111111111111111111111111111111111111111111 \+ +b1111111111111111111111111111111111111111111111111111111111111111 _+ +b1111111111111111111111111111111111111111111111111111111111111111 `+ +b1111111111111111111111111111111111111111111111111111111111111111 a+ +b1111111111111111111111111111111111111111111111111111111111111111 b+ +b1111111111111111111111111111111111111111111111111111111111111111 c+ +b1111111111111111111111111111111111111111111111111111111111111111 d+ +b1111111111111111111111111111111111111111111111111111111111111111 e+ +b1111111111111111111111111111111111111111111111111111111111111111 f+ +b1111111111111111111111111111111111111111111111111111111111111111 g+ +b1111111111111111111111111111111111111111111111111111111111111111 h+ +b1111111111111111111111111111111111111111111111111111111111111111 i+ +b1111111111111111111111111111111111111111111111111111111111111111 j+ +b1111111111111111111111111111111111111111111111111111111111111111 k+ +b1111111111111111111111111111111111111111111111111111111111111111 l+ +b1111111111111111111111111111111111111111111111111111111111111111 m+ +b1111111111111111111111111111111111111111111111111111111111111111 n+ +sHdlSome\x20(1) q+ +b1111111111111111111111111111111111111111111111111111111111111111 r+ +b1111111111111111111111111111111111111111111111111111111111111111 s+ +b11111111 t+ +sCall\x20(1) u+ +sCondNotTaken\x20(3) v+ +sHdlSome\x20(1) w+ +b1111111111111111111111111111111111111111111111111111111111111111 x+ +b1111111111111111111111111111111111111111111111111111111111111111 y+ +b11111111 z+ +sCall\x20(1) {+ +sCondNotTaken\x20(3) |+ +sHdlSome\x20(1) }+ +b1111111111111111111111111111111111111111111111111111111111111111 ~+ +b1111111111111111111111111111111111111111111111111111111111111111 !, +b11111111 ", +sCall\x20(1) #, +sCondNotTaken\x20(3) $, +sHdlSome\x20(1) %, +b1111111111111111111111111111111111111111111111111111111111111111 &, +b1111111111111111111111111111111111111111111111111111111111111111 ', +b11111111 (, +sCall\x20(1) ), +sCondNotTaken\x20(3) *, +sHdlSome\x20(1) +, +b1111111111111111111111111111111111111111111111111111111111111111 ,, +b1111111111111111111111111111111111111111111111111111111111111111 -, +b11111111 ., +sCall\x20(1) /, +sCondNotTaken\x20(3) 0, +sHdlSome\x20(1) 1, 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+#256000000 +0! +0# +0++ +035 +0f5 +#256500000 +1! +1# +1++ +135 +1f5 +sHdlSome\x20(1) % +0P% +sWeaklyNotTaken\x20(1) <( +b1 #+ +b1000 (+ +b1 )+ +sHdlSome\x20(1) -+ +0X/ +sWeaklyNotTaken\x20(1) D2 +b1 +5 +b1000 05 +b1 15 +sHdlSome\x20(1) 55 +sHdlSome\x20(1) h5 +#257000000 +0! +0# +0++ +035 +0f5 +#257500000 +1! +1# +1++ +135 +1f5 +1D +1L+ +1T5 +1)6 +b1000 & +b1 ' +b1 ?( +b10 #+ +b10000 (+ +b10 )+ +b1000 .+ +b1 /+ +b1 G2 +b10 +5 +b10000 05 +b10 15 +b1000 65 +b1 75 +b1000 i5 +b1 j5 +b10 V5 +b1 d5 +b10 +6 +b1 96 +#258000000 +0! +0# +0++ +035 +0f5 +#258500000 +1! +1# +1++ +135 +1f5 +b10000 & +b10 ' +b10 @( +b11 #+ +b11000 (+ +b11 )+ +b10000 .+ +b10 /+ +b10 H2 +b11 +5 +b11000 05 +b11 15 +b10000 65 +b10 75 +b10000 i5 +b10 j5 +b1 V5 +b1000 X5 +b110 Y5 +b1 Z5 +b10 d5 +b1 +6 +b1000 -6 +b110 .6 +b1 /6 +b10 96 +#259000000 +0! +0# +0++ +035 +0f5 +#259500000 +1! +1# +1++ +135 +1f5 +b11000 & +b11 ' +b11 A( +b100 #+ +b100000 (+ +b100 )+ +b11000 .+ +b11 /+ +b11 I2 +b100 +5 +b100000 05 +b100 15 +b11000 65 +b11 75 +b11000 i5 +b11 j5 +sHdlSome\x20(1) + +b100 0 +b1 8 +b100 9 +b100 : +b10 A +sHdlSome\x20(1) 3+ +b100 8+ +b1 @+ +b100 A+ +b100 B+ +b10 I+ +sHdlSome\x20(1) ;5 +b100 @5 +b1 H5 +b100 I5 +b100 J5 +b10 Q5 +b0 V5 +b101 Y5 +b10000 [5 +b1 \5 +b10 ]5 +b11 d5 +sHdlSome\x20(1) n5 +b100 s5 +b1 {5 +b100 |5 +b100 }5 +b10 &6 +b0 +6 +b101 .6 +b10000 06 +b1 16 +b10 26 +b11 96 +#260000000 +0! +0# +0++ +035 +0f5 +#260500000 +1! +1# +1++ +135 +1f5 +b100000 & +b100 ' +b100 B( +b101 #+ +b101000 (+ +b101 )+ +b100000 .+ +b100 /+ +b100 J2 +b101 +5 +b101000 05 +b101 15 +b100000 65 +b100 75 +b100000 i5 +b100 j5 +sHdlNone\x20(0) + +b0 0 +b0 8 +b0 9 +b0 : +b0 A +sHdlNone\x20(0) 3+ +b0 8+ +b0 @+ +b0 A+ +b0 B+ +b0 I+ +sHdlNone\x20(0) ;5 +b0 @5 +b0 H5 +b0 I5 +b0 J5 +b0 Q5 +b1000 U5 +b100 V5 +b1 W5 +b10000 X5 +b0 Y5 +b10 Z5 +b11000 [5 +b101 \5 +b11 ]5 +sHdlNone\x20(0) n5 +b0 s5 +b0 {5 +b0 |5 +b0 }5 +b0 &6 +b1000 *6 +b100 +6 +b1 ,6 +b10000 -6 +b0 .6 +b10 /6 +b11000 06 +b101 16 +b11 26 +#261000000 +0! +0# +0++ +035 +0f5 +#261500000 +1! +1# +1++ +135 +1f5 +b101000 & +b101 ' +b101 C( +b110 #+ +b110000 (+ +b110 )+ +b101000 .+ +b101 /+ +b101 K2 +b110 +5 +b110000 05 +b110 15 +b101000 65 +b101 75 +b101000 i5 +b101 j5 +b11 V5 +b100 \5 +b100000 ^5 +b100 `5 +b100 d5 +b11 +6 +b100 16 +b100000 36 +b100 56 +b100 96 +#262000000 +0! +0# +0++ +035 +0f5 +#262500000 +1! +1# +1++ +135 +1f5 +b110000 & +b110 ' +b110 D( +b111 #+ +b111000 (+ +b111 )+ +b110000 .+ +b110 /+ +b110 L2 +b111 +5 +b111000 05 +b111 15 +b110000 65 +b110 75 +b110000 i5 +b110 j5 +0) +01+ +095 +b10 V5 +b11 \5 +b101000 a5 +b11 b5 +b101 c5 +b101 d5 +0l5 +b10 +6 +b11 16 +b101000 66 +b11 76 +b101 86 +b101 96 +#263000000 +0! +0# +0++ +035 +0f5 +#263500000 +1! +1# +1++ +135 +1f5 +b111000 & +b111 ' +b111000 .+ +b111 /+ +b111000 65 +b111 75 +b111000 i5 +b111 j5 +b1 V5 +b10 \5 +b10 b5 +b1 +6 +b10 16 +b10 76 +#264000000 +0! +0# +0++ +035 +0f5 +#264500000 +1! +1# +1++ +135 +1f5 +sHdlSome\x20(1) + +b1 , +b1 - +b10 . +b1000 / +b100 0 +sBranchCond\x20(2) 1 +b100 2 +b100 3 +b100 4 +b100 5 +b100 6 +b1 7 +b11 8 +b1100 9 +b100 : +sCall\x20(5) ; +b11000 < +b11000 = +b11000 > +b11000 ? +b11000 @ +b10 A +sHdlSome\x20(1) 3+ +b1 4+ +b1 5+ +b10 6+ +b1000 7+ +b100 8+ +sBranchCond\x20(2) 9+ +b100 :+ +b100 ;+ +b100 <+ +b100 =+ +b100 >+ +b1 ?+ +b11 @+ +b1100 A+ +b100 B+ +sCall\x20(5) C+ +b11000 D+ +b11000 E+ +b11000 F+ +b11000 G+ +b11000 H+ +b10 I+ +sHdlSome\x20(1) ;5 +b1 <5 +b1 =5 +b10 >5 +b1000 ?5 +b100 @5 +sBranchCond\x20(2) A5 +b100 B5 +b100 C5 +b100 D5 +b100 E5 +b100 F5 +b1 G5 +b11 H5 +b1100 I5 +b100 J5 +sCall\x20(5) K5 +b11000 L5 +b11000 M5 +b11000 N5 +b11000 O5 +b11000 P5 +b10 Q5 +b0 V5 +b1 \5 +b1 b5 +sHdlSome\x20(1) n5 +b1 o5 +b1 p5 +b10 q5 +b1000 r5 +b100 s5 +sBranchCond\x20(2) t5 +b100 u5 +b100 v5 +b100 w5 +b100 x5 +b100 y5 +b1 z5 +b11 {5 +b1100 |5 +b100 }5 +sCall\x20(5) ~5 +b11000 !6 +b11000 "6 +b11000 #6 +b11000 $6 +b11000 %6 +b10 &6 +b0 +6 +b1 16 +b1 76 +#265000000 +0! +0# +0++ +035 +0f5 +#265500000 +1! +1# +1++ +135 +1f5 +1) +b10 , +b10 - +b100 . +b10000 / +sBranch\x20(1) 1 +b10000 2 +b10000 3 +b10000 4 +b10000 5 +b10000 6 +b10 7 +b101 8 +b10100 9 +sBranch\x20(1) ; +b10000 < +b10000 = +b10000 > +b10000 ? +b10000 @ +11+ +b10 4+ +b10 5+ +b100 6+ +b10000 7+ +sBranch\x20(1) 9+ +b10000 :+ +b10000 ;+ +b10000 <+ +b10000 =+ +b10000 >+ +b10 ?+ +b101 @+ +b10100 A+ +sBranch\x20(1) C+ +b10000 D+ +b10000 E+ +b10000 F+ +b10000 G+ +b10000 H+ +195 +b10 <5 +b10 =5 +b100 >5 +b10000 ?5 +sBranch\x20(1) A5 +b10000 B5 +b10000 C5 +b10000 D5 +b10000 E5 +b10000 F5 +b10 G5 +b101 H5 +b10100 I5 +sBranch\x20(1) K5 +b10000 L5 +b10000 M5 +b10000 N5 +b10000 O5 +b10000 P5 +b10000 U5 +b10 W5 +b11000 X5 +b11 Z5 +b100000 [5 +b0 \5 +b100 ]5 +b101000 ^5 +b101 `5 +b0 a5 +b0 b5 +b0 c5 +b100 d5 +1l5 +b10 o5 +b10 p5 +b100 q5 +b10000 r5 +sBranch\x20(1) t5 +b10000 u5 +b10000 v5 +b10000 w5 +b10000 x5 +b10000 y5 +b10 z5 +b101 {5 +b10100 |5 +sBranch\x20(1) ~5 +b10000 !6 +b10000 "6 +b10000 #6 +b10000 $6 +b10000 %6 +b10000 *6 +b10 ,6 +b11000 -6 +b11 /6 +b100000 06 +b0 16 +b100 26 +b101000 36 +b101 56 +b0 66 +b0 76 +b0 86 +b100 96 +#266000000 +0! +0# +0++ +035 +0f5 +#266500000 +1! +1# +1++ +135 +1f5 +b111 E( +b1000 #+ +b1000000 (+ +b1000 )+ +b111 M2 +b1000 +5 +b1000000 05 +b1000 15 +b11 , +b11 - +b110 . +b11000 / +b11100 2 +b11100 3 +b11100 4 +b11100 5 +b11100 6 +b11 7 +b111 8 +b11100 9 +sRet\x20(9) ; +b0 < +b0 = +b0 > +b0 ? +b0 @ +b11 4+ +b11 5+ +b110 6+ +b11000 7+ +b11100 :+ +b11100 ;+ +b11100 <+ +b11100 =+ +b11100 >+ +b11 ?+ +b111 @+ +b11100 A+ +sRet\x20(9) C+ +b0 D+ +b0 E+ +b0 F+ +b0 G+ +b0 H+ +b11 <5 +b11 =5 +b110 >5 +b11000 ?5 +b11100 B5 +b11100 C5 +b11100 D5 +b11100 E5 +b11100 F5 +b11 G5 +b111 H5 +b11100 I5 +sRet\x20(9) K5 +b0 L5 +b0 M5 +b0 N5 +b0 O5 +b0 P5 +b11000 U5 +b11 W5 +b100000 X5 +b100 Z5 +b101000 [5 +b101 ]5 +b111000 ^5 +b111 _5 +b111 `5 +b11 o5 +b11 p5 +b110 q5 +b11000 r5 +b11100 u5 +b11100 v5 +b11100 w5 +b11100 x5 +b11100 y5 +b11 z5 +b111 {5 +b11100 |5 +sRet\x20(9) ~5 +b0 !6 +b0 "6 +b0 #6 +b0 $6 +b0 %6 +b11000 *6 +b11 ,6 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+0# +0++ +035 +0f5 +#299500000 +1! +1# +1++ +135 +1f5 +1) +b11010 . +11+ +b11010 6+ +195 +b11010 >5 +b10111000 X5 +b10111 Z5 +b11000000 [5 +b0 \5 +b11000 ]5 +b11001000 ^5 +b11001 `5 +b0 a5 +b0 b5 +b0 c5 +b100 d5 +1l5 +b11010 q5 +b10111000 -6 +b10111 /6 +b11000000 06 +b0 16 +b11000 26 +b11001000 36 +b11001 56 +b0 66 +b0 76 +b0 86 +b100 96 +#300000000 diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd index f69c9a7..aad4689 100644 --- a/crates/cpu/tests/expected/reg_alloc.vcd +++ b/crates/cpu/tests/expected/reg_alloc.vcd @@ -24027,11 +24027,13 @@ b0 Nd 1n" 1s" 1x" +b1 z" 1!# 1(# 1-# 12# 17# +b1 9# 1># 1E# 1J# @@ -24039,6 +24041,7 @@ b0 Nd 1T# 1[# 1b# +b1 d# 1i# 1p# 1u# @@ -24046,81 +24049,16 @@ b0 Nd 1!$ 1($ 1/$ +b1 1$ 16$ 1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1`D -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1!\ -1b\ -b1 z" -b1 9# -b1 d# -b1 1$ sHdlSome\x20(1) Q$ b1001000110100010101100111100000010010001101000101011001111000 S$ 1Y$ sHdlSome\x20(1) \$ b1001000110100010101100111100000010010001101000101011001111000 ^$ 1d$ +1P& sHdlSome\x20(1) b& b1001000110100010101100111100000010010001101000101011001111000 d& 1j& @@ -24143,8 +24081,14 @@ b1 @( b1 G( b1 P( b1 S( +1_( b1 a( +1f( +1m( +1t( +1{( b1 }( +1$) b1 0) b1 <) b1 H) @@ -24170,8 +24114,14 @@ b1 O+ b1 V+ b1 ^+ b1 e+ +1v, b1 x, +1}, +1&- +1-- +14- b1 6- +1;- b1 G- b1 S- b1 _- @@ -24203,6 +24153,7 @@ b1001000110100010101100111100000010010001101000101011001111000 00 sHdlSome\x20(1) 90 b1001000110100010101100111100000010010001101000101011001111000 ;0 1A0 +1H0 sHdlSome\x20(1) J0 b1001000110100010101100111100000010010001101000101011001111000 L0 1R0 @@ -24215,6 +24166,7 @@ b1 !1 sHdlSome\x20(1) -1 b1001000110100010101100111100000010010001101000101011001111000 01 161 +1:1 sHdlSome\x20(1) <1 b1001000110100010101100111100000010010001101000101011001111000 >1 1D1 @@ -24242,12 +24194,30 @@ b1000000000000 N2 sHdlSome\x20(1) k2 b1001000110100010101100111100000010010001101000101011001111000 n2 1t2 +1y2 +1}2 +1#3 1&3 +1'3 +1,3 +113 +153 +193 1<3 +1=3 +1B3 +1G3 +1S3 +1_3 1j3 +1k3 b1001000110100010101100111100000010010001101000101011001111000 l3 1r3 +1"4 +1.4 +1:4 1E4 +1F4 b1001000110100010101100111100000010010001101000101011001111000 G4 1M4 sHdlSome\x20(1) Y4 @@ -24384,6 +24354,7 @@ b1001 8@ b1101000101011001111000 9@ sDupLow32\x20(1) ;@ b1000000000000 =@ +1Z@ sHdlSome\x20(1) \@ b1001000110100010101100111100000010010001101000101011001111000 ^@ 1d@ @@ -24437,6 +24408,7 @@ b1001000110100010101100111100000010010001101000101011001111000 OC 1\C 1cC 0dC +1fC sHdlSome\x20(1) hC b1001000110100010101100111100000010010001101000101011001111000 jC 1pC @@ -24449,7 +24421,9 @@ b1 ?D sHdlSome\x20(1) KD b1001000110100010101100111100000010010001101000101011001111000 ND 1TD +1XD b1 ^D +1`D 1rD 0sD 1tD @@ -24460,6 +24434,7 @@ b1 (E 1>E b1 @E b1 BE +1CE b1 IE b1 NE b1 ZE @@ -24479,6 +24454,7 @@ b1 9G b1 EG b1 QG b1 ]G +1gG sHdlSome\x20(1) iG b1001000110100010101100111100000010010001101000101011001111000 kG 1qG @@ -24491,6 +24467,7 @@ b1 @H sHdlSome\x20(1) LH b1001000110100010101100111100000010010001101000101011001111000 OH 1UH +1YH sHdlSome\x20(1) [H b1001000110100010101100111100000010010001101000101011001111000 ]H 1cH @@ -24518,12 +24495,30 @@ b1000000000100 mI sHdlSome\x20(1) ,J b1001000110100010101100111100000010010001101000101011001111000 /J 15J +1:J +1>J +1BJ 1EJ +1FJ +1KJ +1PJ +1TJ +1XJ 1[J +1\J +1aJ +1fJ +1rJ +1~J 1+K +1,K b1001000110100010101100111100000010010001101000101011001111000 -K 13K +1AK +1MK +1YK 1dK +1eK b1001000110100010101100111100000010010001101000101011001111000 fK 1lK sHdlSome\x20(1) xK @@ -24660,6 +24655,7 @@ b1001 WW b1101000101011001111000 XW sDupLow32\x20(1) ZW b1000000000100 \W +1yW sHdlSome\x20(1) {W b1001000110100010101100111100000010010001101000101011001111000 }W 1%X @@ -24713,6 +24709,7 @@ b1001000110100010101100111100000010010001101000101011001111000 nZ 1{Z 1$[ 0%[ +1'[ sHdlSome\x20(1) )[ b1001000110100010101100111100000010010001101000101011001111000 +[ 11[ @@ -24725,7 +24722,9 @@ b1 ^[ sHdlSome\x20(1) j[ b1001000110100010101100111100000010010001101000101011001111000 m[ 1s[ +1w[ b1 }[ +1!\ 13\ 04\ 15\ @@ -24736,6 +24735,7 @@ b1 G\ 1]\ b1 _\ b1 a\ +1b\ b1 h\ b1 m\ b1 y\ @@ -24962,11 +24962,13 @@ b1001000110100010101100111100000010010001101000101011001111000 ji 1n" 1s" 1x" +b10 z" 1!# 1(# 1-# 12# 17# +b10 9# 1># 1E# 1J# @@ -24974,6 +24976,7 @@ b1001000110100010101100111100000010010001101000101011001111000 ji 1T# 1[# 1b# +b10 d# 1i# 1p# 1u# @@ -24981,77 +24984,12 @@ b1001000110100010101100111100000010010001101000101011001111000 ji 1!$ 1($ 1/$ +b10 1$ 16$ 1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1aD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1"\ -1b\ -b10 z" -b10 9# -b10 d# -b10 1$ b1 R$ b1 ]$ +1P& b1 c& b1 n& b10 *' @@ -25070,8 +25008,14 @@ b10 @( b10 G( b10 P( b10 S( +1_( b10 a( +1f( +1m( +1t( +1{( b10 }( +1$) b10 0) b10 <) b10 H) @@ -25097,8 +25041,14 @@ b10 O+ b10 V+ b10 ^+ b10 e+ +1v, b10 x, +1}, +1&- +1-- +14- b10 6- +1;- b10 G- b10 S- b10 _- @@ -25126,12 +25076,14 @@ b10 u/ b10 |/ b1 /0 b1 :0 +1H0 b1 K0 b1 V0 b10 g0 b10 s0 b10 !1 b1 .1 +1:1 b1 =1 b1 H1 b10 Y1 @@ -25143,10 +25095,28 @@ b1 :2 b1 F2 b1000000001000 N2 b1 l2 +1y2 +1}2 +1#3 b1 %3 +1'3 +1,3 +113 +153 +193 b1 ;3 +1=3 +1B3 +1G3 +1S3 +1_3 b1 i3 +1k3 +1"4 +1.4 +1:4 b1 D4 +1F4 sHdlNone\x20(0) Y4 sAddSub\x20(0) [4 b0 `4 @@ -25254,6 +25224,7 @@ b1 )@ b1 5@ b1000000001000 =@ b1 Y@ +1Z@ b1 ]@ b1 h@ b10 y@ @@ -25269,13 +25240,16 @@ b1 E b10 @E b10 BE +1CE b10 IE b10 NE b10 ZE @@ -25303,12 +25278,14 @@ b10 9G b10 EG b10 QG b10 ]G +1gG b1 jG b1 uG b10 (H b10 4H b10 @H b1 MH +1YH b1 \H b1 gH b10 xH @@ -25320,10 +25297,28 @@ b1 YI b1 eI b1000000001100 mI b1 -J +1:J +1>J +1BJ b1 DJ +1FJ +1KJ +1PJ +1TJ +1XJ b1 ZJ +1\J +1aJ +1fJ +1rJ +1~J b1 *K +1,K +1AK +1MK +1YK b1 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 !L @@ -25431,6 +25426,7 @@ b1 HW b1 TW b1000000001100 \W b1 xW +1yW b1 |W b1 )X b10 :X @@ -25446,13 +25442,16 @@ b1 [Y b1 gY b1 sY b1000000001100 {Y +1'[ b1 *[ b1 5[ b10 F[ b10 R[ b10 ^[ b1 k[ +1w[ b10 }[ +1"\ 03\ 09\ b10 ;\ @@ -25461,6 +25460,7 @@ b10 G\ 0]\ b10 _\ b10 a\ +1b\ b10 h\ b10 m\ b10 y\ @@ -26534,14 +26534,18 @@ b1001000110100010101100111100000010010001101000101011001111000 ki 0/k 1! 1i" +b10 k" 1n" 1s" 1x" +b11 z" 1!# 1(# +b10 *# 1-# 12# 17# +b11 9# 1># 1E# 1J# @@ -26549,6 +26553,7 @@ b1001000110100010101100111100000010010001101000101011001111000 ki 1T# 1[# 1b# +b11 d# 1i# 1p# 1u# @@ -26557,81 +26562,14 @@ b1001000110100010101100111100000010010001101000101011001111000 ki 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1bD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1#\ -1b\ -b10 k" -b11 z" -b10 *# -b11 9# -b11 d# b11 8$ +1?$ b10 R$ b1001000110100010101100111100000010010001101000101011001111001 S$ b10 ]$ b0 ^$ 0d$ +1P& b10 c& b1001000110100010101100111100000010010001101000101011001111001 d& b10 n& @@ -26668,8 +26606,14 @@ b1010 H( b11 P( b11 S( b10 V( +1_( b11 a( +1f( +1m( +1t( +1{( b11 }( +1$) b11 0) b1001 1) b11 <) @@ -26719,7 +26663,13 @@ b1001 _+ b11 e+ b1001 f+ b10 w+ +1v, b11 x, +1}, +1&- +1-- +14- +1;- b11 =- b11 G- b1010 H- @@ -26774,6 +26724,7 @@ b1001000110100010101100111100000010010001101000101011001111001 00 b10 :0 b0 ;0 0A0 +1H0 b10 K0 b1001000110100010101100111100000010010001101000101011001111001 L0 b10 V0 @@ -26787,6 +26738,7 @@ b11 !1 b1001 "1 b10 .1 b1001000110100010101100111100000010010001101000101011001111001 01 +1:1 b10 =1 b1001000110100010101100111100000010010001101000101011001111001 >1 b10 H1 @@ -26822,16 +26774,34 @@ b1001000110100010101100111100000010010001101000101011001111000 O2 b10 l2 b1001000110100010101100111100000010010001101000101011001111001 n2 b10 w2 +1y2 0z2 +1}2 +1#3 b10 %3 +1'3 +1,3 b10 /3 +113 +153 +193 b10 ;3 +1=3 +1B3 1F3 +1G3 b1001000110100010101100111100000010010001101000101011001111000 H3 1N3 +1S3 +1_3 b10 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111001 l3 +1"4 +1.4 +1:4 b10 D4 +1F4 b0 G4 0M4 sHdlSome\x20(1) Y4 @@ -27073,6 +27043,7 @@ b1000000010000 =@ b1001000110100010101100111100000010010001101000101011001111000 >@ 1D@ b10 Y@ +1Z@ b10 ]@ b1001000110100010101100111100000010010001101000101011001111001 ^@ b10 h@ @@ -27134,6 +27105,7 @@ b1001000110100010101100111100000010010001101000101011001111000 CC b1001000110100010101100111100000010010001101000101011001111001 EC b1001000110100010101100111100000010010001101000101011001111001 OC 0TC +1fC b10 iC b1001000110100010101100111100000010010001101000101011001111001 jC b10 tC @@ -27147,7 +27119,9 @@ b11 ?D b1001 @D b10 LD b1001000110100010101100111100000010010001101000101011001111001 ND +1XD b11 ^D +1bD 1uD 0vD 1wD @@ -27159,6 +27133,7 @@ b11 (E 1>E b11 @E b11 BE +1CE b11 IE b11 NE b1001 OE @@ -27196,6 +27171,7 @@ b11 QG b1010 RG b11 ]G b1010 ^G +1gG b10 jG b1001000110100010101100111100000010010001101000101011001111001 kG b10 uG @@ -27210,6 +27186,7 @@ b1010 AH b10 MH b0 OH 0UH +1YH b10 \H b1001000110100010101100111100000010010001101000101011001111001 ]H b10 gH @@ -27257,22 +27234,40 @@ b10 -J b0 /J 05J b10 8J +1:J +1>J +1BJ b10 DJ +1FJ +1KJ b10 NJ +1PJ 0QJ +1TJ 1UJ +1XJ b10 ZJ +1\J +1aJ +1fJ b1 pJ +1rJ +1~J b10 *K +1,K b1001000110100010101100111100000010010001101000101011001111001 -K 1@K +1AK b1001000110100010101100111100000010010001101000101011001111000 BK 1HK b1 KK 1LK +1MK b1001000110100010101100111100000010010001101000101011001111000 NK 1TK +1YK b10 cK +1eK b0 fK 0lK sHdlSome\x20(1) xK @@ -27604,6 +27599,7 @@ b1001000110100010101100111100000010010001101000101011001111000 ]W b1001000110100010101100111100000010010001101000101011001111000 fW 1lW b10 xW +1yW b10 |W b1001000110100010101100111100000010010001101000101011001111001 }W b10 )X @@ -27686,6 +27682,7 @@ b1001000110100010101100111100000010010001101000101011001111000 HZ 1aZ b1001000110100010101100111100000010010001101000101011001111000 bZ b1001000110100010101100111100000010010001101000101011001111000 dZ +1'[ b10 *[ b1001000110100010101100111100000010010001101000101011001111001 +[ b10 5[ @@ -27700,7 +27697,9 @@ b1010 _[ b10 k[ b0 m[ 0s[ +1w[ b11 }[ +1#\ 16\ 07\ 18\ @@ -27712,6 +27711,7 @@ b11 G\ 1]\ b11 _\ b11 a\ +1b\ b11 h\ b11 m\ b1001 n\ @@ -27914,14 +27914,18 @@ b0 li 00k 1! 1i" +b11 k" 1n" 1s" 1x" +b100 z" 1!# 1(# +b11 *# 1-# 12# 17# +b100 9# 1># 1E# 1J# @@ -27929,6 +27933,7 @@ b0 li 1T# 1[# 1b# +b100 d# 1i# 1p# 1u# @@ -27937,79 +27942,12 @@ b0 li 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1cD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1$\ -1b\ -b11 k" -b100 z" -b11 *# -b100 9# -b100 d# b100 8$ +1?$ b11 R$ b1001000110100010101100111100000010010001101000101011001111010 S$ b11 ]$ +1P& b11 c& b1001000110100010101100111100000010010001101000101011001111010 d& b11 n& @@ -28044,8 +27982,14 @@ b1110 H( b100 P( b100 S( b11 V( +1_( b100 a( +1f( +1m( +1t( +1{( b100 }( +1$) b100 0) b1101 1) b100 <) @@ -28095,7 +28039,13 @@ b1101 _+ b100 e+ b1101 f+ b11 w+ +1v, b100 x, +1}, +1&- +1-- +14- +1;- b100 =- b100 G- b1110 H- @@ -28148,6 +28098,7 @@ b1110 }/ b11 /0 b1001000110100010101100111100000010010001101000101011001111010 00 b11 :0 +1H0 b11 K0 b1001000110100010101100111100000010010001101000101011001111010 L0 b11 V0 @@ -28159,6 +28110,7 @@ b100 !1 b1101 "1 b11 .1 b1001000110100010101100111100000010010001101000101011001111010 01 +1:1 b11 =1 b1001000110100010101100111100000010010001101000101011001111010 >1 b11 H1 @@ -28181,15 +28133,33 @@ b1001000110100010101100111100000010010001101000101011001111001 O2 b11 l2 b1001000110100010101100111100000010010001101000101011001111010 n2 b11 w2 +1y2 +1}2 +1#3 b11 %3 +1'3 +1,3 b11 /3 +113 +153 +193 b11 ;3 +1=3 +1B3 b10 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111001 H3 +1S3 +1_3 b11 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111010 l3 b10 ~3 +1"4 +1.4 +1:4 b11 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -28337,6 +28307,7 @@ b1001 6@ b1000000011000 =@ b1001000110100010101100111100000010010001101000101011001111001 >@ b11 Y@ +1Z@ b11 ]@ b1001000110100010101100111100000010010001101000101011001111010 ^@ b11 h@ @@ -28372,6 +28343,7 @@ b1001000110100010101100111100000010010001101000101011001111010 )C b1001000110100010101100111100000010010001101000101011001111001 CC b1001000110100010101100111100000010010001101000101011001111010 EC b1001000110100010101100111100000010010001101000101011001111010 OC +1fC b11 iC b1001000110100010101100111100000010010001101000101011001111010 jC b11 tC @@ -28383,7 +28355,9 @@ b100 ?D b1101 @D b11 LD b1001000110100010101100111100000010010001101000101011001111010 ND +1XD b100 ^D +1cD 0uD 0xD 0&E @@ -28391,6 +28365,7 @@ b100 (E 0>E b100 @E b100 BE +1CE b100 IE b100 NE b1101 OE @@ -28428,6 +28403,7 @@ b100 QG b1110 RG b100 ]G b1110 ^G +1gG b11 jG b1001000110100010101100111100000010010001101000101011001111010 kG b11 uG @@ -28438,6 +28414,7 @@ b1110 5H b100 @H b1110 AH b11 MH +1YH b11 \H b1001000110100010101100111100000010010001101000101011001111010 ]H b11 gH @@ -28459,16 +28436,34 @@ b0 nI 0tI b11 -J b11 8J +1:J +1>J +1BJ b11 DJ +1FJ +1KJ b11 NJ +1PJ +1TJ +1XJ b11 ZJ +1\J +1aJ b10 dJ +1fJ +1rJ +1~J b11 *K +1,K b1001000110100010101100111100000010010001101000101011001111010 -K b10 ?K +1AK b0 BK 0HK +1MK +1YK b11 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -28639,6 +28634,7 @@ b1000000011100 \W b0 ]W 0cW b11 xW +1yW b11 |W b1001000110100010101100111100000010010001101000101011001111010 }W b11 )X @@ -28684,6 +28680,7 @@ b0 nZ 0{Z 0$[ 1%[ +1'[ b11 *[ b1001000110100010101100111100000010010001101000101011001111010 +[ b11 5[ @@ -28694,7 +28691,9 @@ b1110 S[ b100 ^[ b1110 _[ b11 k[ +1w[ b100 }[ +1$\ 06\ 09\ 0E\ @@ -28702,6 +28701,7 @@ b100 G\ 0]\ b100 _\ b100 a\ +1b\ b100 h\ b100 m\ b1101 n\ @@ -28904,14 +28904,18 @@ b0 mi 01k 1! 1i" +b100 k" 1n" 1s" 1x" +b101 z" 1!# 1(# +b100 *# 1-# 12# 17# +b101 9# 1># 1E# 1J# @@ -28919,6 +28923,7 @@ b0 mi 1T# 1[# 1b# +b101 d# 1i# 1p# 1u# @@ -28927,79 +28932,12 @@ b0 mi 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1dD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1%\ -1b\ -b100 k" -b101 z" -b100 *# -b101 9# -b101 d# b101 8$ +1?$ b100 R$ b1001000110100010101100111100000010010001101000101011001111011 S$ b100 ]$ +1P& b100 c& b1001000110100010101100111100000010010001101000101011001111011 d& b100 n& @@ -29034,8 +28972,14 @@ b10010 H( b101 P( b101 S( b100 V( +1_( b101 a( +1f( +1m( +1t( +1{( b101 }( +1$) b101 0) b10001 1) b101 <) @@ -29085,7 +29029,13 @@ b10001 _+ b101 e+ b10001 f+ b100 w+ +1v, b101 x, +1}, +1&- +1-- +14- +1;- b101 =- b101 G- b10010 H- @@ -29138,6 +29088,7 @@ b10010 }/ b100 /0 b1001000110100010101100111100000010010001101000101011001111011 00 b100 :0 +1H0 b100 K0 b1001000110100010101100111100000010010001101000101011001111011 L0 b100 V0 @@ -29149,6 +29100,7 @@ b101 !1 b10001 "1 b100 .1 b1001000110100010101100111100000010010001101000101011001111011 01 +1:1 b100 =1 b1001000110100010101100111100000010010001101000101011001111011 >1 b100 H1 @@ -29171,15 +29123,33 @@ b1001000110100010101100111100000010010001101000101011001111010 O2 b100 l2 b1001000110100010101100111100000010010001101000101011001111011 n2 b100 w2 +1y2 +1}2 +1#3 b100 %3 +1'3 +1,3 b100 /3 +113 +153 +193 b100 ;3 +1=3 +1B3 b11 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111010 H3 +1S3 +1_3 b100 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111011 l3 b11 ~3 +1"4 +1.4 +1:4 b100 D4 +1F4 sHdlSome\x20(1) Y4 b100 ]4 b1101 ^4 @@ -29327,6 +29297,7 @@ b1101 6@ b1000000100000 =@ b1001000110100010101100111100000010010001101000101011001111010 >@ b100 Y@ +1Z@ b100 ]@ b1001000110100010101100111100000010010001101000101011001111011 ^@ b100 h@ @@ -29364,6 +29335,7 @@ b1001000110100010101100111100000010010001101000101011001111010 CC b1001000110100010101100111100000010010001101000101011001111011 EC b1001000110100010101100111100000010010001101000101011001111011 OC 1TC +1fC b100 iC b1001000110100010101100111100000010010001101000101011001111011 jC b100 tC @@ -29375,7 +29347,9 @@ b101 ?D b10001 @D b100 LD b1001000110100010101100111100000010010001101000101011001111011 ND +1XD b101 ^D +1dD 1{D 0|D 1}D @@ -29386,6 +29360,7 @@ b101 (E 1>E b101 @E b101 BE +1CE b101 IE b101 NE b10001 OE @@ -29423,6 +29398,7 @@ b101 QG b10010 RG b101 ]G b10010 ^G +1gG b100 jG b1001000110100010101100111100000010010001101000101011001111011 kG b100 uG @@ -29433,6 +29409,7 @@ b10010 5H b101 @H b10010 AH b100 MH +1YH b100 \H b1001000110100010101100111100000010010001101000101011001111011 ]H b100 gH @@ -29452,14 +29429,32 @@ b1110 fI b1000000100100 mI b100 -J b100 8J +1:J +1>J +1BJ b100 DJ +1FJ +1KJ b100 NJ +1PJ +1TJ +1XJ b100 ZJ +1\J +1aJ b11 dJ +1fJ +1rJ +1~J b100 *K +1,K b1001000110100010101100111100000010010001101000101011001111011 -K b11 ?K +1AK +1MK +1YK b100 cK +1eK sHdlSome\x20(1) xK sLogical\x20(2) zK b100 |K @@ -29612,6 +29607,7 @@ b100 TW b1110 UW b1000000100100 \W b100 xW +1yW b100 |W b1001000110100010101100111100000010010001101000101011001111011 }W b100 )X @@ -29637,6 +29633,7 @@ b1110 hY b100 sY b1110 tY b1000000100100 {Y +1'[ b100 *[ b1001000110100010101100111100000010010001101000101011001111011 +[ b100 5[ @@ -29647,7 +29644,9 @@ b10010 S[ b101 ^[ b10010 _[ b100 k[ +1w[ b101 }[ +1%\ 1<\ 0=\ 1>\ @@ -29658,6 +29657,7 @@ b101 G\ 1]\ b101 _\ b101 a\ +1b\ b101 h\ b101 m\ b10001 n\ @@ -29860,14 +29860,18 @@ b0 ni 02k 1! 1i" +b101 k" 1n" 1s" 1x" +b110 z" 1!# 1(# +b101 *# 1-# 12# 17# +b110 9# 1># 1E# 1J# @@ -29875,6 +29879,7 @@ b0 ni 1T# 1[# 1b# +b110 d# 1i# 1p# 1u# @@ -29883,79 +29888,12 @@ b0 ni 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1eD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1&\ -1b\ -b101 k" -b110 z" -b101 *# -b110 9# -b110 d# b110 8$ +1?$ b101 R$ b1001000110100010101100111100000010010001101000101011001111100 S$ b101 ]$ +1P& b101 c& b1001000110100010101100111100000010010001101000101011001111100 d& b101 n& @@ -29990,8 +29928,14 @@ b10110 H( b110 P( b110 S( b101 V( +1_( b110 a( +1f( +1m( +1t( +1{( b110 }( +1$) b110 0) b10101 1) b110 <) @@ -30041,7 +29985,13 @@ b10101 _+ b110 e+ b10101 f+ b101 w+ +1v, b110 x, +1}, +1&- +1-- +14- +1;- b110 =- b110 G- b10110 H- @@ -30094,6 +30044,7 @@ b10110 }/ b101 /0 b1001000110100010101100111100000010010001101000101011001111100 00 b101 :0 +1H0 b101 K0 b1001000110100010101100111100000010010001101000101011001111100 L0 b101 V0 @@ -30105,6 +30056,7 @@ b110 !1 b10101 "1 b101 .1 b1001000110100010101100111100000010010001101000101011001111100 01 +1:1 b101 =1 b1001000110100010101100111100000010010001101000101011001111100 >1 b101 H1 @@ -30127,15 +30079,33 @@ b1001000110100010101100111100000010010001101000101011001111011 O2 b101 l2 b1001000110100010101100111100000010010001101000101011001111100 n2 b101 w2 +1y2 +1}2 +1#3 b101 %3 +1'3 +1,3 b101 /3 +113 +153 +193 b101 ;3 +1=3 +1B3 b100 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111011 H3 +1S3 +1_3 b101 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111100 l3 b100 ~3 +1"4 +1.4 +1:4 b101 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -30283,6 +30253,7 @@ b10001 6@ b1000000101000 =@ b1001000110100010101100111100000010010001101000101011001111011 >@ b101 Y@ +1Z@ b101 ]@ b1001000110100010101100111100000010010001101000101011001111100 ^@ b101 h@ @@ -30320,6 +30291,7 @@ b1001000110100010101100111100000010010001101000101011001111011 CC b1001000110100010101100111100000010010001101000101011001111100 EC b1001000110100010101100111100000010010001101000101011001111100 OC 0TC +1fC b101 iC b1001000110100010101100111100000010010001101000101011001111100 jC b101 tC @@ -30331,7 +30303,9 @@ b110 ?D b10101 @D b101 LD b1001000110100010101100111100000010010001101000101011001111100 ND +1XD b110 ^D +1eD 0{D 0#E b10 %E @@ -30340,6 +30314,7 @@ b110 (E 0>E b110 @E b110 BE +1CE b110 IE b110 NE b10101 OE @@ -30377,6 +30352,7 @@ b110 QG b10110 RG b110 ]G b10110 ^G +1gG b101 jG b1001000110100010101100111100000010010001101000101011001111100 kG b101 uG @@ -30387,6 +30363,7 @@ b10110 5H b110 @H b10110 AH b101 MH +1YH b101 \H b1001000110100010101100111100000010010001101000101011001111100 ]H b101 gH @@ -30406,14 +30383,32 @@ b10010 fI b1000000101100 mI b101 -J b101 8J +1:J +1>J +1BJ b101 DJ +1FJ +1KJ b101 NJ +1PJ +1TJ +1XJ b101 ZJ +1\J +1aJ b100 dJ +1fJ +1rJ +1~J b101 *K +1,K b1001000110100010101100111100000010010001101000101011001111100 -K b100 ?K +1AK +1MK +1YK b101 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -30566,6 +30561,7 @@ b101 TW b10010 UW b1000000101100 \W b101 xW +1yW b101 |W b1001000110100010101100111100000010010001101000101011001111100 }W b101 )X @@ -30591,6 +30587,7 @@ b10010 hY b101 sY b10010 tY b1000000101100 {Y +1'[ b101 *[ b1001000110100010101100111100000010010001101000101011001111100 +[ b101 5[ @@ -30601,7 +30598,9 @@ b10110 S[ b110 ^[ b10110 _[ b101 k[ +1w[ b110 }[ +1&\ 0<\ 0B\ b10 D\ @@ -30610,6 +30609,7 @@ b110 G\ 0]\ b110 _\ b110 a\ +1b\ b110 h\ b110 m\ b10101 n\ @@ -30812,14 +30812,18 @@ b0 oi 03k 1! 1i" +b110 k" 1n" 1s" 1x" +b111 z" 1!# 1(# +b110 *# 1-# 12# 17# +b111 9# 1># 1E# 1J# @@ -30827,6 +30831,7 @@ b0 oi 1T# 1[# 1b# +b111 d# 1i# 1p# 1u# @@ -30835,79 +30840,12 @@ b0 oi 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1fD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1'\ -1b\ -b110 k" -b111 z" -b110 *# -b111 9# -b111 d# b111 8$ +1?$ b110 R$ b1001000110100010101100111100000010010001101000101011001111101 S$ b110 ]$ +1P& b110 c& b1001000110100010101100111100000010010001101000101011001111101 d& b110 n& @@ -30942,8 +30880,14 @@ b11010 H( b111 P( b111 S( b110 V( +1_( b111 a( +1f( +1m( +1t( +1{( b111 }( +1$) b111 0) b11001 1) b111 <) @@ -30993,7 +30937,13 @@ b11001 _+ b111 e+ b11001 f+ b110 w+ +1v, b111 x, +1}, +1&- +1-- +14- +1;- b111 =- b111 G- b11010 H- @@ -31046,6 +30996,7 @@ b11010 }/ b110 /0 b1001000110100010101100111100000010010001101000101011001111101 00 b110 :0 +1H0 b110 K0 b1001000110100010101100111100000010010001101000101011001111101 L0 b110 V0 @@ -31057,6 +31008,7 @@ b111 !1 b11001 "1 b110 .1 b1001000110100010101100111100000010010001101000101011001111101 01 +1:1 b110 =1 b1001000110100010101100111100000010010001101000101011001111101 >1 b110 H1 @@ -31079,15 +31031,33 @@ b1001000110100010101100111100000010010001101000101011001111100 O2 b110 l2 b1001000110100010101100111100000010010001101000101011001111101 n2 b110 w2 +1y2 +1}2 +1#3 b110 %3 +1'3 +1,3 b110 /3 +113 +153 +193 b110 ;3 +1=3 +1B3 b101 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111100 H3 +1S3 +1_3 b110 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111101 l3 b101 ~3 +1"4 +1.4 +1:4 b110 D4 +1F4 sHdlSome\x20(1) Y4 b110 ]4 b10101 ^4 @@ -31235,6 +31205,7 @@ b10101 6@ b1000000110000 =@ b1001000110100010101100111100000010010001101000101011001111100 >@ b110 Y@ +1Z@ b110 ]@ b1001000110100010101100111100000010010001101000101011001111101 ^@ b110 h@ @@ -31272,6 +31243,7 @@ b1001000110100010101100111100000010010001101000101011001111100 CC b1001000110100010101100111100000010010001101000101011001111101 EC b1001000110100010101100111100000010010001101000101011001111101 OC 1TC +1fC b110 iC b1001000110100010101100111100000010010001101000101011001111101 jC b110 tC @@ -31283,7 +31255,9 @@ b111 ?D b11001 @D b110 LD b1001000110100010101100111100000010010001101000101011001111101 ND +1XD b111 ^D +1fD 1~D 0!E 1"E @@ -31296,6 +31270,7 @@ b111 (E 1>E b111 @E b111 BE +1CE b111 IE b111 NE b11001 OE @@ -31333,6 +31308,7 @@ b111 QG b11010 RG b111 ]G b11010 ^G +1gG b110 jG b1001000110100010101100111100000010010001101000101011001111101 kG b110 uG @@ -31343,6 +31319,7 @@ b11010 5H b111 @H b11010 AH b110 MH +1YH b110 \H b1001000110100010101100111100000010010001101000101011001111101 ]H b110 gH @@ -31362,14 +31339,32 @@ b10110 fI b1000000110100 mI b110 -J b110 8J +1:J +1>J +1BJ b110 DJ +1FJ +1KJ b110 NJ +1PJ +1TJ +1XJ b110 ZJ +1\J +1aJ b101 dJ +1fJ +1rJ +1~J b110 *K +1,K b1001000110100010101100111100000010010001101000101011001111101 -K b101 ?K +1AK +1MK +1YK b110 cK +1eK sHdlSome\x20(1) xK sLogical\x20(2) zK b110 |K @@ -31522,6 +31517,7 @@ b110 TW b10110 UW b1000000110100 \W b110 xW +1yW b110 |W b1001000110100010101100111100000010010001101000101011001111101 }W b110 )X @@ -31547,6 +31543,7 @@ b10110 hY b110 sY b10110 tY b1000000110100 {Y +1'[ b110 *[ b1001000110100010101100111100000010010001101000101011001111101 +[ b110 5[ @@ -31557,7 +31554,9 @@ b11010 S[ b111 ^[ b11010 _[ b110 k[ +1w[ b111 }[ +1'\ 1?\ 0@\ 1A\ @@ -31570,6 +31569,7 @@ b111 G\ 1]\ b111 _\ b111 a\ +1b\ b111 h\ b111 m\ b11001 n\ @@ -31772,14 +31772,18 @@ b0 pi 04k 1! 1i" +b111 k" 1n" 1s" 1x" +b1000 z" 1!# 1(# +b111 *# 1-# 12# 17# +b1000 9# 1># 1E# 1J# @@ -31787,6 +31791,7 @@ b0 pi 1T# 1[# 1b# +b1000 d# 1i# 1p# 1u# @@ -31795,79 +31800,12 @@ b0 pi 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1gD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1(\ -1b\ -b111 k" -b1000 z" -b111 *# -b1000 9# -b1000 d# b1000 8$ +1?$ b111 R$ b1001000110100010101100111100000010010001101000101011001111110 S$ b111 ]$ +1P& b111 c& b1001000110100010101100111100000010010001101000101011001111110 d& b111 n& @@ -31902,8 +31840,14 @@ b11110 H( b1000 P( b1000 S( b111 V( +1_( b1000 a( +1f( +1m( +1t( +1{( b1000 }( +1$) b1000 0) b11101 1) b1000 <) @@ -31953,7 +31897,13 @@ b11101 _+ b1000 e+ b11101 f+ b111 w+ +1v, b1000 x, +1}, +1&- +1-- +14- +1;- b1000 =- b1000 G- b11110 H- @@ -32006,6 +31956,7 @@ b11110 }/ b111 /0 b1001000110100010101100111100000010010001101000101011001111110 00 b111 :0 +1H0 b111 K0 b1001000110100010101100111100000010010001101000101011001111110 L0 b111 V0 @@ -32017,6 +31968,7 @@ b1000 !1 b11101 "1 b111 .1 b1001000110100010101100111100000010010001101000101011001111110 01 +1:1 b111 =1 b1001000110100010101100111100000010010001101000101011001111110 >1 b111 H1 @@ -32039,15 +31991,33 @@ b1001000110100010101100111100000010010001101000101011001111101 O2 b111 l2 b1001000110100010101100111100000010010001101000101011001111110 n2 b111 w2 +1y2 +1}2 +1#3 b111 %3 +1'3 +1,3 b111 /3 +113 +153 +193 b111 ;3 +1=3 +1B3 b110 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111101 H3 +1S3 +1_3 b111 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111110 l3 b110 ~3 +1"4 +1.4 +1:4 b111 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -32195,6 +32165,7 @@ b11001 6@ b1000000111000 =@ b1001000110100010101100111100000010010001101000101011001111101 >@ b111 Y@ +1Z@ b111 ]@ b1001000110100010101100111100000010010001101000101011001111110 ^@ b111 h@ @@ -32230,6 +32201,7 @@ b1001000110100010101100111100000010010001101000101011001111110 )C b1001000110100010101100111100000010010001101000101011001111101 CC b1001000110100010101100111100000010010001101000101011001111110 EC b1001000110100010101100111100000010010001101000101011001111110 OC +1fC b111 iC b1001000110100010101100111100000010010001101000101011001111110 jC b111 tC @@ -32241,13 +32213,16 @@ b1000 ?D b11101 @D b111 LD b1001000110100010101100111100000010010001101000101011001111110 ND +1XD b1000 ^D +1gD 0~D 0#E 0&E 0>E b1000 @E b1000 BE +1CE b1000 IE b1000 NE b11101 OE @@ -32285,6 +32260,7 @@ b1000 QG b11110 RG b1000 ]G b11110 ^G +1gG b111 jG b1001000110100010101100111100000010010001101000101011001111110 kG b111 uG @@ -32295,6 +32271,7 @@ b11110 5H b1000 @H b11110 AH b111 MH +1YH b111 \H b1001000110100010101100111100000010010001101000101011001111110 ]H b111 gH @@ -32314,14 +32291,32 @@ b11010 fI b1000000111100 mI b111 -J b111 8J +1:J +1>J +1BJ b111 DJ +1FJ +1KJ b111 NJ +1PJ +1TJ +1XJ b111 ZJ +1\J +1aJ b110 dJ +1fJ +1rJ +1~J b111 *K +1,K b1001000110100010101100111100000010010001101000101011001111110 -K b110 ?K +1AK +1MK +1YK b111 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -32474,6 +32469,7 @@ b111 TW b11010 UW b1000000111100 \W b111 xW +1yW b111 |W b1001000110100010101100111100000010010001101000101011001111110 }W b111 )X @@ -32499,6 +32495,7 @@ b11010 hY b111 sY b11010 tY b1000000111100 {Y +1'[ b111 *[ b1001000110100010101100111100000010010001101000101011001111110 +[ b111 5[ @@ -32509,13 +32506,16 @@ b11110 S[ b1000 ^[ b11110 _[ b111 k[ +1w[ b1000 }[ +1(\ 0?\ 0B\ 0E\ 0]\ b1000 _\ b1000 a\ +1b\ b1000 h\ b1000 m\ b11101 n\ @@ -32718,14 +32718,18 @@ b0 qi 05k 1! 1i" +b1000 k" 1n" 1s" 1x" +b1001 z" 1!# 1(# +b1000 *# 1-# 12# 17# +b1001 9# 1># 1E# 1J# @@ -32733,6 +32737,7 @@ b0 qi 1T# 1[# 1b# +b1001 d# 1i# 1p# 1u# @@ -32741,79 +32746,12 @@ b0 qi 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1hD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1)\ -1b\ -b1000 k" -b1001 z" -b1000 *# -b1001 9# -b1001 d# b1001 8$ +1?$ b1000 R$ b1001000110100010101100111100000010010001101000101011001111111 S$ b1000 ]$ +1P& b1000 c& b1001000110100010101100111100000010010001101000101011001111111 d& b1000 n& @@ -32848,8 +32786,14 @@ b100010 H( b1001 P( b1001 S( b1000 V( +1_( b1001 a( +1f( +1m( +1t( +1{( b1001 }( +1$) b1001 0) b100001 1) b1001 <) @@ -32899,7 +32843,13 @@ b100001 _+ b1001 e+ b100001 f+ b1000 w+ +1v, b1001 x, +1}, +1&- +1-- +14- +1;- b1001 =- b1001 G- b100010 H- @@ -32952,6 +32902,7 @@ b100010 }/ b1000 /0 b1001000110100010101100111100000010010001101000101011001111111 00 b1000 :0 +1H0 b1000 K0 b1001000110100010101100111100000010010001101000101011001111111 L0 b1000 V0 @@ -32963,6 +32914,7 @@ b1001 !1 b100001 "1 b1000 .1 b1001000110100010101100111100000010010001101000101011001111111 01 +1:1 b1000 =1 b1001000110100010101100111100000010010001101000101011001111111 >1 b1000 H1 @@ -32985,15 +32937,33 @@ b1001000110100010101100111100000010010001101000101011001111110 O2 b1000 l2 b1001000110100010101100111100000010010001101000101011001111111 n2 b1000 w2 +1y2 +1}2 +1#3 b1000 %3 +1'3 +1,3 b1000 /3 +113 +153 +193 b1000 ;3 +1=3 +1B3 b111 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111110 H3 +1S3 +1_3 b1000 i3 +1k3 b1001000110100010101100111100000010010001101000101011001111111 l3 b111 ~3 +1"4 +1.4 +1:4 b1000 D4 +1F4 sHdlSome\x20(1) Y4 b1000 ]4 b11101 ^4 @@ -33141,6 +33111,7 @@ b11101 6@ b1000001000000 =@ b1001000110100010101100111100000010010001101000101011001111110 >@ b1000 Y@ +1Z@ b1000 ]@ b1001000110100010101100111100000010010001101000101011001111111 ^@ b1000 h@ @@ -33178,6 +33149,7 @@ b1001000110100010101100111100000010010001101000101011001111110 CC b1001000110100010101100111100000010010001101000101011001111111 EC b1001000110100010101100111100000010010001101000101011001111111 OC 0TC +1fC b1000 iC b1001000110100010101100111100000010010001101000101011001111111 jC b1000 tC @@ -33189,7 +33161,9 @@ b1001 ?D b100001 @D b1000 LD b1001000110100010101100111100000010010001101000101011001111111 ND +1XD b1001 ^D +1hD 1)E 0*E 1+E @@ -33200,6 +33174,7 @@ b1 =E 1>E b1001 @E b1001 BE +1CE b1001 IE b1001 NE b100001 OE @@ -33237,6 +33212,7 @@ b1001 QG b100010 RG b1001 ]G b100010 ^G +1gG b1000 jG b1001000110100010101100111100000010010001101000101011001111111 kG b1000 uG @@ -33247,6 +33223,7 @@ b100010 5H b1001 @H b100010 AH b1000 MH +1YH b1000 \H b1001000110100010101100111100000010010001101000101011001111111 ]H b1000 gH @@ -33266,14 +33243,32 @@ b11110 fI b1000001000100 mI b1000 -J b1000 8J +1:J +1>J +1BJ b1000 DJ +1FJ +1KJ b1000 NJ +1PJ +1TJ +1XJ b1000 ZJ +1\J +1aJ b111 dJ +1fJ +1rJ +1~J b1000 *K +1,K b1001000110100010101100111100000010010001101000101011001111111 -K b111 ?K +1AK +1MK +1YK b1000 cK +1eK sHdlSome\x20(1) xK sLogical\x20(2) zK b1000 |K @@ -33426,6 +33421,7 @@ b1000 TW b11110 UW b1000001000100 \W b1000 xW +1yW b1000 |W b1001000110100010101100111100000010010001101000101011001111111 }W b1000 )X @@ -33451,6 +33447,7 @@ b11110 hY b1000 sY b11110 tY b1000001000100 {Y +1'[ b1000 *[ b1001000110100010101100111100000010010001101000101011001111111 +[ b1000 5[ @@ -33461,7 +33458,9 @@ b100010 S[ b1001 ^[ b100010 _[ b1000 k[ +1w[ b1001 }[ +1)\ 1H\ 0I\ 1J\ @@ -33472,6 +33471,7 @@ b1 \\ 1]\ b1001 _\ b1001 a\ +1b\ b1001 h\ b1001 m\ b100001 n\ @@ -33674,14 +33674,18 @@ b0 ri 06k 1! 1i" +b1001 k" 1n" 1s" 1x" +b1010 z" 1!# 1(# +b1001 *# 1-# 12# 17# +b1010 9# 1># 1E# 1J# @@ -33689,6 +33693,7 @@ b0 ri 1T# 1[# 1b# +b1010 d# 1i# 1p# 1u# @@ -33697,79 +33702,12 @@ b0 ri 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1iD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1*\ -1b\ -b1001 k" -b1010 z" -b1001 *# -b1010 9# -b1010 d# b1010 8$ +1?$ b1001 R$ b1001000110100010101100111100000010010001101000101011010000000 S$ b1001 ]$ +1P& b1001 c& b1001000110100010101100111100000010010001101000101011010000000 d& b1001 n& @@ -33804,8 +33742,14 @@ b100110 H( b1010 P( b1010 S( b1001 V( +1_( b1010 a( +1f( +1m( +1t( +1{( b1010 }( +1$) b1010 0) b100101 1) b1010 <) @@ -33855,7 +33799,13 @@ b100101 _+ b1010 e+ b100101 f+ b1001 w+ +1v, b1010 x, +1}, +1&- +1-- +14- +1;- b1010 =- b1010 G- b100110 H- @@ -33908,6 +33858,7 @@ b100110 }/ b1001 /0 b1001000110100010101100111100000010010001101000101011010000000 00 b1001 :0 +1H0 b1001 K0 b1001000110100010101100111100000010010001101000101011010000000 L0 b1001 V0 @@ -33919,6 +33870,7 @@ b1010 !1 b100101 "1 b1001 .1 b1001000110100010101100111100000010010001101000101011010000000 01 +1:1 b1001 =1 b1001000110100010101100111100000010010001101000101011010000000 >1 b1001 H1 @@ -33941,15 +33893,33 @@ b1001000110100010101100111100000010010001101000101011001111111 O2 b1001 l2 b1001000110100010101100111100000010010001101000101011010000000 n2 b1001 w2 +1y2 +1}2 +1#3 b1001 %3 +1'3 +1,3 b1001 /3 +113 +153 +193 b1001 ;3 +1=3 +1B3 b1000 E3 +1G3 b1001000110100010101100111100000010010001101000101011001111111 H3 +1S3 +1_3 b1001 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000000 l3 b1000 ~3 +1"4 +1.4 +1:4 b1001 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -34097,6 +34067,7 @@ b100001 6@ b1000001001000 =@ b1001000110100010101100111100000010010001101000101011001111111 >@ b1001 Y@ +1Z@ b1001 ]@ b1001000110100010101100111100000010010001101000101011010000000 ^@ b1001 h@ @@ -34138,6 +34109,7 @@ b1001000110100010101100111100000010010001101000101011010000000 EC 1GC b1001000110100010101100111100000010010001101000101011010000000 OC 1QC +1fC b1001 iC b1001000110100010101100111100000010010001101000101011010000000 jC b1001 tC @@ -34149,7 +34121,9 @@ b1010 ?D b100101 @D b1001 LD b1001000110100010101100111100000010010001101000101011010000000 ND +1XD b1010 ^D +1iD 0)E 0/E b10 1E @@ -34158,6 +34132,7 @@ b10 =E 0>E b1010 @E b1010 BE +1CE b1010 IE b1010 NE b100101 OE @@ -34195,6 +34170,7 @@ b1010 QG b100110 RG b1010 ]G b100110 ^G +1gG b1001 jG b1001000110100010101100111100000010010001101000101011010000000 kG b1001 uG @@ -34205,6 +34181,7 @@ b100110 5H b1010 @H b100110 AH b1001 MH +1YH b1001 \H b1001000110100010101100111100000010010001101000101011010000000 ]H b1001 gH @@ -34224,14 +34201,32 @@ b100010 fI b1000001001100 mI b1001 -J b1001 8J +1:J +1>J +1BJ b1001 DJ +1FJ +1KJ b1001 NJ +1PJ +1TJ +1XJ b1001 ZJ +1\J +1aJ b1000 dJ +1fJ +1rJ +1~J b1001 *K +1,K b1001000110100010101100111100000010010001101000101011010000000 -K b1000 ?K +1AK +1MK +1YK b1001 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -34384,6 +34379,7 @@ b1001 TW b100010 UW b1000001001100 \W b1001 xW +1yW b1001 |W b1001000110100010101100111100000010010001101000101011010000000 }W b1001 )X @@ -34409,6 +34405,7 @@ b100010 hY b1001 sY b100010 tY b1000001001100 {Y +1'[ b1001 *[ b1001000110100010101100111100000010010001101000101011010000000 +[ b1001 5[ @@ -34419,7 +34416,9 @@ b100110 S[ b1010 ^[ b100110 _[ b1001 k[ +1w[ b1010 }[ +1*\ 0H\ 0N\ b10 P\ @@ -34428,6 +34427,7 @@ b10 \\ 0]\ b1010 _\ b1010 a\ +1b\ b1010 h\ b1010 m\ b100101 n\ @@ -34630,14 +34630,18 @@ b0 si 07k 1! 1i" +b1010 k" 1n" 1s" 1x" +b1011 z" 1!# 1(# +b1010 *# 1-# 12# 17# +b1011 9# 1># 1E# 1J# @@ -34645,6 +34649,7 @@ b0 si 1T# 1[# 1b# +b1011 d# 1i# 1p# 1u# @@ -34653,79 +34658,12 @@ b0 si 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1jD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1+\ -1b\ -b1010 k" -b1011 z" -b1010 *# -b1011 9# -b1011 d# b1011 8$ +1?$ b1010 R$ b1001000110100010101100111100000010010001101000101011010000001 S$ b1010 ]$ +1P& b1010 c& b1001000110100010101100111100000010010001101000101011010000001 d& b1010 n& @@ -34760,8 +34698,14 @@ b101010 H( b1011 P( b1011 S( b1010 V( +1_( b1011 a( +1f( +1m( +1t( +1{( b1011 }( +1$) b1011 0) b101001 1) b1011 <) @@ -34811,7 +34755,13 @@ b101001 _+ b1011 e+ b101001 f+ b1010 w+ +1v, b1011 x, +1}, +1&- +1-- +14- +1;- b1011 =- b1011 G- b101010 H- @@ -34864,6 +34814,7 @@ b101010 }/ b1010 /0 b1001000110100010101100111100000010010001101000101011010000001 00 b1010 :0 +1H0 b1010 K0 b1001000110100010101100111100000010010001101000101011010000001 L0 b1010 V0 @@ -34875,6 +34826,7 @@ b1011 !1 b101001 "1 b1010 .1 b1001000110100010101100111100000010010001101000101011010000001 01 +1:1 b1010 =1 b1001000110100010101100111100000010010001101000101011010000001 >1 b1010 H1 @@ -34897,15 +34849,33 @@ b1001000110100010101100111100000010010001101000101011010000000 O2 b1010 l2 b1001000110100010101100111100000010010001101000101011010000001 n2 b1010 w2 +1y2 +1}2 +1#3 b1010 %3 +1'3 +1,3 b1010 /3 +113 +153 +193 b1010 ;3 +1=3 +1B3 b1001 E3 +1G3 b1001000110100010101100111100000010010001101000101011010000000 H3 +1S3 +1_3 b1010 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000001 l3 b1001 ~3 +1"4 +1.4 +1:4 b1010 D4 +1F4 sHdlSome\x20(1) Y4 b1010 ]4 b100101 ^4 @@ -35053,6 +35023,7 @@ b100101 6@ b1000001010000 =@ b1001000110100010101100111100000010010001101000101011010000000 >@ b1010 Y@ +1Z@ b1010 ]@ b1001000110100010101100111100000010010001101000101011010000001 ^@ b1010 h@ @@ -35096,6 +35067,7 @@ b1001000110100010101100111100000010010001101000101011010000001 EC b1001000110100010101100111100000010010001101000101011010000001 OC 0QC 1TC +1fC b1010 iC b1001000110100010101100111100000010010001101000101011010000001 jC b1010 tC @@ -35107,7 +35079,9 @@ b1011 ?D b101001 @D b1010 LD b1001000110100010101100111100000010010001101000101011010000001 ND +1XD b1011 ^D +1jD 1,E 0-E 1.E @@ -35119,6 +35093,7 @@ b11 =E 1>E b1011 @E b1011 BE +1CE b1011 IE b1011 NE b101001 OE @@ -35156,6 +35131,7 @@ b1011 QG b101010 RG b1011 ]G b101010 ^G +1gG b1010 jG b1001000110100010101100111100000010010001101000101011010000001 kG b1010 uG @@ -35166,6 +35142,7 @@ b101010 5H b1011 @H b101010 AH b1010 MH +1YH b1010 \H b1001000110100010101100111100000010010001101000101011010000001 ]H b1010 gH @@ -35185,14 +35162,32 @@ b100110 fI b1000001010100 mI b1010 -J b1010 8J +1:J +1>J +1BJ b1010 DJ +1FJ +1KJ b1010 NJ +1PJ +1TJ +1XJ b1010 ZJ +1\J +1aJ b1001 dJ +1fJ +1rJ +1~J b1010 *K +1,K b1001000110100010101100111100000010010001101000101011010000001 -K b1001 ?K +1AK +1MK +1YK b1010 cK +1eK sHdlSome\x20(1) xK sLogical\x20(2) zK b1010 |K @@ -35345,6 +35340,7 @@ b1010 TW b100110 UW b1000001010100 \W b1010 xW +1yW b1010 |W b1001000110100010101100111100000010010001101000101011010000001 }W b1010 )X @@ -35370,6 +35366,7 @@ b100110 hY b1010 sY b100110 tY b1000001010100 {Y +1'[ b1010 *[ b1001000110100010101100111100000010010001101000101011010000001 +[ b1010 5[ @@ -35380,7 +35377,9 @@ b101010 S[ b1011 ^[ b101010 _[ b1010 k[ +1w[ b1011 }[ +1+\ 1K\ 0L\ 1M\ @@ -35392,6 +35391,7 @@ b11 \\ 1]\ b1011 _\ b1011 a\ +1b\ b1011 h\ b1011 m\ b101001 n\ @@ -35594,14 +35594,18 @@ b0 ti 08k 1! 1i" +b1011 k" 1n" 1s" 1x" +b1100 z" 1!# 1(# +b1011 *# 1-# 12# 17# +b1100 9# 1># 1E# 1J# @@ -35609,6 +35613,7 @@ b0 ti 1T# 1[# 1b# +b1100 d# 1i# 1p# 1u# @@ -35617,79 +35622,12 @@ b0 ti 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1kD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1,\ -1b\ -b1011 k" -b1100 z" -b1011 *# -b1100 9# -b1100 d# b1100 8$ +1?$ b1011 R$ b1001000110100010101100111100000010010001101000101011010000010 S$ b1011 ]$ +1P& b1011 c& b1001000110100010101100111100000010010001101000101011010000010 d& b1011 n& @@ -35724,8 +35662,14 @@ b101110 H( b1100 P( b1100 S( b1011 V( +1_( b1100 a( +1f( +1m( +1t( +1{( b1100 }( +1$) b1100 0) b101101 1) b1100 <) @@ -35775,7 +35719,13 @@ b101101 _+ b1100 e+ b101101 f+ b1011 w+ +1v, b1100 x, +1}, +1&- +1-- +14- +1;- b1100 =- b1100 G- b101110 H- @@ -35828,6 +35778,7 @@ b101110 }/ b1011 /0 b1001000110100010101100111100000010010001101000101011010000010 00 b1011 :0 +1H0 b1011 K0 b1001000110100010101100111100000010010001101000101011010000010 L0 b1011 V0 @@ -35839,6 +35790,7 @@ b1100 !1 b101101 "1 b1011 .1 b1001000110100010101100111100000010010001101000101011010000010 01 +1:1 b1011 =1 b1001000110100010101100111100000010010001101000101011010000010 >1 b1011 H1 @@ -35861,15 +35813,33 @@ b1001000110100010101100111100000010010001101000101011010000001 O2 b1011 l2 b1001000110100010101100111100000010010001101000101011010000010 n2 b1011 w2 +1y2 +1}2 +1#3 b1011 %3 +1'3 +1,3 b1011 /3 +113 +153 +193 b1011 ;3 +1=3 +1B3 b1010 E3 +1G3 b1001000110100010101100111100000010010001101000101011010000001 H3 +1S3 +1_3 b1011 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000010 l3 b1010 ~3 +1"4 +1.4 +1:4 b1011 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -36017,6 +35987,7 @@ b101001 6@ b1000001011000 =@ b1001000110100010101100111100000010010001101000101011010000001 >@ b1011 Y@ +1Z@ b1011 ]@ b1001000110100010101100111100000010010001101000101011010000010 ^@ b1011 h@ @@ -36052,6 +36023,7 @@ b1001000110100010101100111100000010010001101000101011010000010 )C b1001000110100010101100111100000010010001101000101011010000001 CC b1001000110100010101100111100000010010001101000101011010000010 EC b1001000110100010101100111100000010010001101000101011010000010 OC +1fC b1011 iC b1001000110100010101100111100000010010001101000101011010000010 jC b1011 tC @@ -36063,7 +36035,9 @@ b1100 ?D b101101 @D b1011 LD b1001000110100010101100111100000010010001101000101011010000010 ND +1XD b1100 ^D +1kD 0,E 0/E 0;E @@ -36071,6 +36045,7 @@ b100 =E 0>E b1100 @E b1100 BE +1CE b1100 IE b1100 NE b101101 OE @@ -36108,6 +36083,7 @@ b1100 QG b101110 RG b1100 ]G b101110 ^G +1gG b1011 jG b1001000110100010101100111100000010010001101000101011010000010 kG b1011 uG @@ -36118,6 +36094,7 @@ b101110 5H b1100 @H b101110 AH b1011 MH +1YH b1011 \H b1001000110100010101100111100000010010001101000101011010000010 ]H b1011 gH @@ -36137,14 +36114,32 @@ b101010 fI b1000001011100 mI b1011 -J b1011 8J +1:J +1>J +1BJ b1011 DJ +1FJ +1KJ b1011 NJ +1PJ +1TJ +1XJ b1011 ZJ +1\J +1aJ b1010 dJ +1fJ +1rJ +1~J b1011 *K +1,K b1001000110100010101100111100000010010001101000101011010000010 -K b1010 ?K +1AK +1MK +1YK b1011 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -36297,6 +36292,7 @@ b1011 TW b101010 UW b1000001011100 \W b1011 xW +1yW b1011 |W b1001000110100010101100111100000010010001101000101011010000010 }W b1011 )X @@ -36322,6 +36318,7 @@ b101010 hY b1011 sY b101010 tY b1000001011100 {Y +1'[ b1011 *[ b1001000110100010101100111100000010010001101000101011010000010 +[ b1011 5[ @@ -36332,7 +36329,9 @@ b101110 S[ b1100 ^[ b101110 _[ b1011 k[ +1w[ b1100 }[ +1,\ 0K\ 0N\ 0Z\ @@ -36340,6 +36339,7 @@ b100 \\ 0]\ b1100 _\ b1100 a\ +1b\ b1100 h\ b1100 m\ b101101 n\ @@ -36542,14 +36542,18 @@ b0 ui 09k 1! 1i" +b1100 k" 1n" 1s" 1x" +b1101 z" 1!# 1(# +b1100 *# 1-# 12# 17# +b1101 9# 1># 1E# 1J# @@ -36557,6 +36561,7 @@ b0 ui 1T# 1[# 1b# +b1101 d# 1i# 1p# 1u# @@ -36565,79 +36570,12 @@ b0 ui 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1lD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1-\ -1b\ -b1100 k" -b1101 z" -b1100 *# -b1101 9# -b1101 d# b1101 8$ +1?$ b1100 R$ b1001000110100010101100111100000010010001101000101011010000011 S$ b1100 ]$ +1P& b1100 c& b1001000110100010101100111100000010010001101000101011010000011 d& b1100 n& @@ -36672,8 +36610,14 @@ b110010 H( b1101 P( b1101 S( b1100 V( +1_( b1101 a( +1f( +1m( +1t( +1{( b1101 }( +1$) b1101 0) b110001 1) b1101 <) @@ -36723,7 +36667,13 @@ b110001 _+ b1101 e+ b110001 f+ b1100 w+ +1v, b1101 x, +1}, +1&- +1-- +14- +1;- b1101 =- b1101 G- b110010 H- @@ -36776,6 +36726,7 @@ b110010 }/ b1100 /0 b1001000110100010101100111100000010010001101000101011010000011 00 b1100 :0 +1H0 b1100 K0 b1001000110100010101100111100000010010001101000101011010000011 L0 b1100 V0 @@ -36787,6 +36738,7 @@ b1101 !1 b110001 "1 b1100 .1 b1001000110100010101100111100000010010001101000101011010000011 01 +1:1 b1100 =1 b1001000110100010101100111100000010010001101000101011010000011 >1 b1100 H1 @@ -36809,15 +36761,33 @@ b1001000110100010101100111100000010010001101000101011010000010 O2 b1100 l2 b1001000110100010101100111100000010010001101000101011010000011 n2 b1100 w2 +1y2 +1}2 +1#3 b1100 %3 +1'3 +1,3 b1100 /3 +113 +153 +193 b1100 ;3 +1=3 +1B3 b1011 E3 +1G3 b1001000110100010101100111100000010010001101000101011010000010 H3 +1S3 +1_3 b1100 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000011 l3 b1011 ~3 +1"4 +1.4 +1:4 b1100 D4 +1F4 sHdlSome\x20(1) Y4 b1100 ]4 b101101 ^4 @@ -36965,6 +36935,7 @@ b101101 6@ b1000001100000 =@ b1001000110100010101100111100000010010001101000101011010000010 >@ b1100 Y@ +1Z@ b1100 ]@ b1001000110100010101100111100000010010001101000101011010000011 ^@ b1100 h@ @@ -37002,6 +36973,7 @@ b1001000110100010101100111100000010010001101000101011010000010 CC b1001000110100010101100111100000010010001101000101011010000011 EC b1001000110100010101100111100000010010001101000101011010000011 OC 0TC +1fC b1100 iC b1001000110100010101100111100000010010001101000101011010000011 jC b1100 tC @@ -37013,7 +36985,9 @@ b1101 ?D b110001 @D b1100 LD b1001000110100010101100111100000010010001101000101011010000011 ND +1XD b1101 ^D +1lD 12E 03E 14E @@ -37024,6 +36998,7 @@ b101 =E 1>E b1101 @E b1101 BE +1CE b1101 IE b1101 NE b110001 OE @@ -37061,6 +37036,7 @@ b1101 QG b110010 RG b1101 ]G b110010 ^G +1gG b1100 jG b1001000110100010101100111100000010010001101000101011010000011 kG b1100 uG @@ -37071,6 +37047,7 @@ b110010 5H b1101 @H b110010 AH b1100 MH +1YH b1100 \H b1001000110100010101100111100000010010001101000101011010000011 ]H b1100 gH @@ -37090,14 +37067,32 @@ b101110 fI b1000001100100 mI b1100 -J b1100 8J +1:J +1>J +1BJ b1100 DJ +1FJ +1KJ b1100 NJ +1PJ +1TJ +1XJ b1100 ZJ +1\J +1aJ b1011 dJ +1fJ +1rJ +1~J b1100 *K +1,K b1001000110100010101100111100000010010001101000101011010000011 -K b1011 ?K +1AK +1MK +1YK b1100 cK +1eK sHdlSome\x20(1) xK sLogical\x20(2) zK b1100 |K @@ -37250,6 +37245,7 @@ b1100 TW b101110 UW b1000001100100 \W b1100 xW +1yW b1100 |W b1001000110100010101100111100000010010001101000101011010000011 }W b1100 )X @@ -37275,6 +37271,7 @@ b101110 hY b1100 sY b101110 tY b1000001100100 {Y +1'[ b1100 *[ b1001000110100010101100111100000010010001101000101011010000011 +[ b1100 5[ @@ -37285,7 +37282,9 @@ b110010 S[ b1101 ^[ b110010 _[ b1100 k[ +1w[ b1101 }[ +1-\ 1Q\ 0R\ 1S\ @@ -37296,6 +37295,7 @@ b101 \\ 1]\ b1101 _\ b1101 a\ +1b\ b1101 h\ b1101 m\ b110001 n\ @@ -37498,14 +37498,18 @@ b0 vi 0:k 1! 1i" +b1101 k" 1n" 1s" 1x" +b1110 z" 1!# 1(# +b1101 *# 1-# 12# 17# +b1110 9# 1># 1E# 1J# @@ -37513,6 +37517,7 @@ b0 vi 1T# 1[# 1b# +b1110 d# 1i# 1p# 1u# @@ -37521,79 +37526,12 @@ b0 vi 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1mD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1.\ -1b\ -b1101 k" -b1110 z" -b1101 *# -b1110 9# -b1110 d# b1110 8$ +1?$ b1101 R$ b1001000110100010101100111100000010010001101000101011010000100 S$ b1101 ]$ +1P& b1101 c& b1001000110100010101100111100000010010001101000101011010000100 d& b1101 n& @@ -37628,8 +37566,14 @@ b110110 H( b1110 P( b1110 S( b1101 V( +1_( b1110 a( +1f( +1m( +1t( +1{( b1110 }( +1$) b1110 0) b110101 1) b1110 <) @@ -37679,7 +37623,13 @@ b110101 _+ b1110 e+ b110101 f+ b1101 w+ +1v, b1110 x, +1}, +1&- +1-- +14- +1;- b1110 =- b1110 G- b110110 H- @@ -37732,6 +37682,7 @@ b110110 }/ b1101 /0 b1001000110100010101100111100000010010001101000101011010000100 00 b1101 :0 +1H0 b1101 K0 b1001000110100010101100111100000010010001101000101011010000100 L0 b1101 V0 @@ -37743,6 +37694,7 @@ b1110 !1 b110101 "1 b1101 .1 b1001000110100010101100111100000010010001101000101011010000100 01 +1:1 b1101 =1 b1001000110100010101100111100000010010001101000101011010000100 >1 b1101 H1 @@ -37765,15 +37717,33 @@ b1001000110100010101100111100000010010001101000101011010000011 O2 b1101 l2 b1001000110100010101100111100000010010001101000101011010000100 n2 b1101 w2 +1y2 +1}2 +1#3 b1101 %3 +1'3 +1,3 b1101 /3 +113 +153 +193 b1101 ;3 +1=3 +1B3 b1100 E3 +1G3 b1001000110100010101100111100000010010001101000101011010000011 H3 +1S3 +1_3 b1101 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000100 l3 b1100 ~3 +1"4 +1.4 +1:4 b1101 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -37921,6 +37891,7 @@ b110001 6@ b1000001101000 =@ b1001000110100010101100111100000010010001101000101011010000011 >@ b1101 Y@ +1Z@ b1101 ]@ b1001000110100010101100111100000010010001101000101011010000100 ^@ b1101 h@ @@ -37958,6 +37929,7 @@ b1001000110100010101100111100000010010001101000101011010000011 CC b1001000110100010101100111100000010010001101000101011010000100 EC b1001000110100010101100111100000010010001101000101011010000100 OC 1TC +1fC b1101 iC b1001000110100010101100111100000010010001101000101011010000100 jC b1101 tC @@ -37969,7 +37941,9 @@ b1110 ?D b110101 @D b1101 LD b1001000110100010101100111100000010010001101000101011010000100 ND +1XD b1110 ^D +1mD 02E 08E b10 :E @@ -37978,6 +37952,7 @@ b110 =E 0>E b1110 @E b1110 BE +1CE b1110 IE b1110 NE b110101 OE @@ -38015,6 +37990,7 @@ b1110 QG b110110 RG b1110 ]G b110110 ^G +1gG b1101 jG b1001000110100010101100111100000010010001101000101011010000100 kG b1101 uG @@ -38025,6 +38001,7 @@ b110110 5H b1110 @H b110110 AH b1101 MH +1YH b1101 \H b1001000110100010101100111100000010010001101000101011010000100 ]H b1101 gH @@ -38044,14 +38021,32 @@ b110010 fI b1000001101100 mI b1101 -J b1101 8J +1:J +1>J +1BJ b1101 DJ +1FJ +1KJ b1101 NJ +1PJ +1TJ +1XJ b1101 ZJ +1\J +1aJ b1100 dJ +1fJ +1rJ +1~J b1101 *K +1,K b1001000110100010101100111100000010010001101000101011010000100 -K b1100 ?K +1AK +1MK +1YK b1101 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -38204,6 +38199,7 @@ b1101 TW b110010 UW b1000001101100 \W b1101 xW +1yW b1101 |W b1001000110100010101100111100000010010001101000101011010000100 }W b1101 )X @@ -38229,6 +38225,7 @@ b110010 hY b1101 sY b110010 tY b1000001101100 {Y +1'[ b1101 *[ b1001000110100010101100111100000010010001101000101011010000100 +[ b1101 5[ @@ -38239,7 +38236,9 @@ b110110 S[ b1110 ^[ b110110 _[ b1101 k[ +1w[ b1110 }[ +1.\ 0Q\ 0W\ b10 Y\ @@ -38248,6 +38247,7 @@ b110 \\ 0]\ b1110 _\ b1110 a\ +1b\ b1110 h\ b1110 m\ b110101 n\ @@ -38450,14 +38450,18 @@ b0 wi 0;k 1! 1i" +b1110 k" 1n" 1s" 1x" +b1111 z" 1!# 1(# +b1110 *# 1-# 12# 17# +b1111 9# 1># 1E# 1J# @@ -38465,6 +38469,7 @@ b0 wi 1T# 1[# 1b# +b1111 d# 1i# 1p# 1u# @@ -38473,79 +38478,12 @@ b0 wi 1($ 1/$ 16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1nD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1/\ -1b\ -b1110 k" -b1111 z" -b1110 *# -b1111 9# -b1111 d# b1111 8$ +1?$ b1110 R$ b1001000110100010101100111100000010010001101000101011010000101 S$ b1110 ]$ +1P& b1110 c& b1001000110100010101100111100000010010001101000101011010000101 d& b1110 n& @@ -38580,8 +38518,14 @@ b111010 H( b1111 P( b1111 S( b1110 V( +1_( b1111 a( +1f( +1m( +1t( +1{( b1111 }( +1$) b1111 0) b111001 1) b1111 <) @@ -38631,7 +38575,13 @@ b111001 _+ b1111 e+ b111001 f+ b1110 w+ +1v, b1111 x, +1}, +1&- +1-- +14- +1;- b1111 =- b1111 G- b111010 H- @@ -38684,6 +38634,7 @@ b111010 }/ b1110 /0 b1001000110100010101100111100000010010001101000101011010000101 00 b1110 :0 +1H0 b1110 K0 b1001000110100010101100111100000010010001101000101011010000101 L0 b1110 V0 @@ -38695,6 +38646,7 @@ b1111 !1 b111001 "1 b1110 .1 b1001000110100010101100111100000010010001101000101011010000101 01 +1:1 b1110 =1 b1001000110100010101100111100000010010001101000101011010000101 >1 b1110 H1 @@ -38717,15 +38669,33 @@ b1001000110100010101100111100000010010001101000101011010000100 O2 b1110 l2 b1001000110100010101100111100000010010001101000101011010000101 n2 b1110 w2 +1y2 +1}2 +1#3 b1110 %3 +1'3 +1,3 b1110 /3 +113 +153 +193 b1110 ;3 +1=3 +1B3 b1101 E3 +1G3 b1001000110100010101100111100000010010001101000101011010000100 H3 +1S3 +1_3 b1110 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000101 l3 b1101 ~3 +1"4 +1.4 +1:4 b1110 D4 +1F4 sHdlSome\x20(1) Y4 b1110 ]4 b110101 ^4 @@ -38873,6 +38843,7 @@ b110101 6@ b1000001110000 =@ b1001000110100010101100111100000010010001101000101011010000100 >@ b1110 Y@ +1Z@ b1110 ]@ b1001000110100010101100111100000010010001101000101011010000101 ^@ b1110 h@ @@ -38910,6 +38881,7 @@ b1001000110100010101100111100000010010001101000101011010000100 CC b1001000110100010101100111100000010010001101000101011010000101 EC b1001000110100010101100111100000010010001101000101011010000101 OC 0TC +1fC b1110 iC b1001000110100010101100111100000010010001101000101011010000101 jC b1110 tC @@ -38921,7 +38893,9 @@ b1111 ?D b111001 @D b1110 LD b1001000110100010101100111100000010010001101000101011010000101 ND +1XD b1111 ^D +1nD 15E 06E 17E @@ -38935,6 +38909,7 @@ b111 =E 0?E b1111 @E b1111 BE +1CE b1111 IE b1111 NE b111001 OE @@ -38972,6 +38947,7 @@ b1111 QG b111010 RG b1111 ]G b111010 ^G +1gG b1110 jG b1001000110100010101100111100000010010001101000101011010000101 kG b1110 uG @@ -38982,6 +38958,7 @@ b111010 5H b1111 @H b111010 AH b1110 MH +1YH b1110 \H b1001000110100010101100111100000010010001101000101011010000101 ]H b1110 gH @@ -39001,14 +38978,32 @@ b110110 fI b1000001110100 mI b1110 -J b1110 8J +1:J +1>J +1BJ b1110 DJ +1FJ +1KJ b1110 NJ +1PJ +1TJ +1XJ b1110 ZJ +1\J +1aJ b1101 dJ +1fJ +1rJ +1~J b1110 *K +1,K b1001000110100010101100111100000010010001101000101011010000101 -K b1101 ?K +1AK +1MK +1YK b1110 cK +1eK sHdlSome\x20(1) xK sLogical\x20(2) zK b1110 |K @@ -39161,6 +39156,7 @@ b1110 TW b110110 UW b1000001110100 \W b1110 xW +1yW b1110 |W b1001000110100010101100111100000010010001101000101011010000101 }W b1110 )X @@ -39186,6 +39182,7 @@ b110110 hY b1110 sY b110110 tY b1000001110100 {Y +1'[ b1110 *[ b1001000110100010101100111100000010010001101000101011010000101 +[ b1110 5[ @@ -39196,7 +39193,9 @@ b111010 S[ b1111 ^[ b111010 _[ b1110 k[ +1w[ b1111 }[ +1/\ 1T\ 0U\ 1V\ @@ -39210,6 +39209,7 @@ b111 \\ 0^\ b1111 _\ b1111 a\ +1b\ b1111 h\ b1111 m\ b111001 n\ @@ -39411,22 +39411,43 @@ b0 xi 0,k 0# 1E# 1J# 1O# 1T# 1[# +0a# 1b# +b0 c# +b0 d# 1i# 1p# 1u# @@ -39434,99 +39455,16 @@ b0 xi 1!$ 1($ 1/$ -16$ -1?$ -1P& -1_( -1f( -1m( -1t( -1{( -1$) -1v, -1}, -1&- -1-- -14- -1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1oD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -10\ -1b\ -0h" -b0 j" -b0 k" -0w" -b0 y" -b0 z" -b0 &# -0'# -b0 )# -b0 *# -b0 +# -0,# -b0 .# -b0 /# -b0 5# -06# -b0 8# -b0 9# -0a# -b0 c# -b0 d# 04$ 05$ +16$ b0 7$ b0 8$ +1?$ b1111 R$ b1001000110100010101100111100000010010001101000101011010000110 S$ b1111 ]$ +1P& b1111 c& b1001000110100010101100111100000010010001101000101011010000110 d& b1111 n& @@ -39602,11 +39540,17 @@ b0 T( b0 U( b0 V( 0^( +1_( b0 `( b0 a( +1f( +1m( +1t( 0z( +1{( b0 |( b0 }( +1$) b0 0) b0 1) b0 <) @@ -39667,10 +39611,16 @@ b0 7, b0 8, b0 t, 0u, +1v, b0 w, b0 x, +1}, +1&- +1-- +14- 09- 0:- +1;- b0 <- b0 =- b0 G- @@ -39751,6 +39701,7 @@ b0 -0 b1111 /0 b1001000110100010101100111100000010010001101000101011010000110 00 b1111 :0 +1H0 b1111 K0 b1001000110100010101100111100000010010001101000101011010000110 L0 b1111 V0 @@ -39767,6 +39718,7 @@ b0 %1 b0 )1 b1111 .1 b1001000110100010101100111100000010010001101000101011010000110 01 +1:1 b1111 =1 b1001000110100010101100111100000010010001101000101011010000110 >1 b1111 H1 @@ -39795,15 +39747,33 @@ b1111 l2 b1001000110100010101100111100000010010001101000101011010000110 n2 b0 w2 0x2 +1y2 +1}2 +1#3 b1111 %3 +1'3 +1,3 b0 /3 +113 +153 +193 b1111 ;3 +1=3 +1B3 b1110 E3 +1G3 b1001000110100010101100111100000010010001101000101011010000101 H3 +1S3 +1_3 b1111 i3 +1k3 b1001000110100010101100111100000010010001101000101011010000110 l3 b1110 ~3 +1"4 +1.4 +1:4 b1111 D4 +1F4 sHdlNone\x20(0) Y4 b0 ]4 b0 ^4 @@ -39964,6 +39934,7 @@ b111001 6@ b1000001111000 =@ b1001000110100010101100111100000010010001101000101011010000101 >@ b1111 Y@ +1Z@ b1111 ]@ b1001000110100010101100111100000010010001101000101011010000110 ^@ b1111 h@ @@ -40004,6 +39975,7 @@ b1001000110100010101100111100000010010001101000101011010000110 )C b1001000110100010101100111100000010010001101000101011010000101 CC b1001000110100010101100111100000010010001101000101011010000110 EC b1001000110100010101100111100000010010001101000101011010000110 OC +1fC b1111 iC b1001000110100010101100111100000010010001101000101011010000110 jC b1111 tC @@ -40020,15 +39992,18 @@ b0 CD b0 GD b1111 LD b1001000110100010101100111100000010010001101000101011010000110 ND +1XD sHdlNone\x20(0) ]D b0 ^D 0_D +1oD 05E 08E 0;E 0>E sHdlNone\x20(0) AE b0 BE +1CE sHdlNone\x20(0) HE b0 IE 0JE @@ -40110,6 +40085,7 @@ b0 ]G b0 ^G b0 _G b0 dG +1gG b1111 jG b1001000110100010101100111100000010010001101000101011010000110 kG b1111 uG @@ -40131,6 +40107,7 @@ b0 BH b0 GH b0 HH b1111 MH +1YH b1111 \H b1001000110100010101100111100000010010001101000101011010000110 ]H b1111 gH @@ -40161,19 +40138,37 @@ b111010 fI b1000001111100 mI b1111 -J b0 8J +1:J b0 J +1BJ b1111 DJ +1FJ +1KJ b0 NJ 0OJ +1PJ b0 RJ 0SJ +1TJ 0UJ +1XJ b1111 ZJ +1\J +1aJ b1110 dJ +1fJ +1rJ +1~J b1111 *K +1,K b1001000110100010101100111100000010010001101000101011010000110 -K b1110 ?K +1AK +1MK +1YK b1111 cK +1eK sHdlNone\x20(0) xK sAddSub\x20(0) zK b0 |K @@ -40353,6 +40348,7 @@ b1111 TW b111010 UW b1000001111100 \W b1111 xW +1yW b1111 |W b1001000110100010101100111100000010010001101000101011010000110 }W b1111 )X @@ -40389,6 +40385,7 @@ b111010 hY b1111 sY b111010 tY b1000001111100 {Y +1'[ b1111 *[ b1001000110100010101100111100000010010001101000101011010000110 +[ b1111 5[ @@ -40410,15 +40407,18 @@ b0 `[ b0 e[ b0 f[ b1111 k[ +1w[ sHdlNone\x20(0) |[ b0 }[ 0~[ +10\ 0T\ 0W\ 0Z\ 0]\ sHdlNone\x20(0) `\ b0 a\ +1b\ sHdlNone\x20(0) g\ b0 h\ 0i\ @@ -40659,7 +40659,19 @@ b0 yi 1/$ 16$ 1?$ +sHdlNone\x20(0) Q$ +b0 R$ +b0 S$ +0Y$ +sHdlNone\x20(0) \$ +b0 ]$ 1P& +sHdlNone\x20(0) b& +b0 c& +b0 d& +0j& +sHdlNone\x20(0) m& +b0 n& 1_( 1f( 1m( @@ -40672,72 +40684,13 @@ b0 yi 1-- 14- 1;- -1H0 -1:1 -1y2 -1}2 -1#3 -1'3 -1,3 -113 -153 -193 -1=3 -1B3 -1G3 -1S3 -1_3 -1k3 -1"4 -1.4 -1:4 -1F4 -1Z@ -1fC -1XD -1CE -1gG -1YH -1:J -1>J -1BJ -1FJ -1KJ -1PJ -1TJ -1XJ -1\J -1aJ -1fJ -1rJ -1~J -1,K -1AK -1MK -1YK -1eK -1yW -1'[ -1w[ -1b\ -sHdlNone\x20(0) Q$ -b0 R$ -b0 S$ -0Y$ -sHdlNone\x20(0) \$ -b0 ]$ -sHdlNone\x20(0) b& -b0 c& -b0 d& -0j& -sHdlNone\x20(0) m& -b0 n& sHdlNone\x20(0) .0 b0 /0 b0 00 060 sHdlNone\x20(0) 90 b0 :0 +1H0 sHdlNone\x20(0) J0 b0 K0 b0 L0 @@ -40748,6 +40701,7 @@ sHdlNone\x20(0) -1 b0 .1 b0 01 061 +1:1 sHdlNone\x20(0) <1 b0 =1 b0 >1 @@ -40775,21 +40729,39 @@ sHdlNone\x20(0) k2 b0 l2 b0 n2 0t2 +1y2 +1}2 +1#3 b0 %3 0&3 +1'3 +1,3 +113 +153 +193 b0 ;3 0<3 +1=3 +1B3 b0 E3 0F3 +1G3 b0 H3 0N3 +1S3 +1_3 b0 i3 0j3 +1k3 b0 l3 0r3 b0 ~3 +1"4 +1.4 +1:4 b0 D4 0E4 +1F4 sHdlNone\x20(0) #5 b0 '5 b0 (5 @@ -40939,6 +40911,7 @@ b0 =@ b0 >@ 0D@ b0 Y@ +1Z@ sHdlNone\x20(0) \@ b0 ]@ b0 ^@ @@ -40997,6 +40970,7 @@ b0 OC 0\C 0cC 1dC +1fC sHdlNone\x20(0) hC b0 iC b0 jC @@ -41007,6 +40981,9 @@ sHdlNone\x20(0) KD b0 LD b0 ND 0TD +1XD +1CE +1gG sHdlNone\x20(0) iG b0 jG b0 kG @@ -41015,6 +40992,7 @@ sHdlNone\x20(0) tG b0 uG sHdlNone\x20(0) LH b0 MH +1YH sHdlNone\x20(0) [H b0 \H b0 ]H @@ -41044,24 +41022,42 @@ b0 wI 0}I sHdlNone\x20(0) ,J b0 -J +1:J +1>J +1BJ b0 DJ 0EJ +1FJ +1KJ +1PJ +1TJ +1XJ b0 ZJ 0[J +1\J +1aJ b0 dJ +1fJ b0 pJ +1rJ +1~J b0 *K 0+K +1,K b0 -K 03K b0 ?K 0@K +1AK b0 KK 0LK +1MK b0 NK 0TK +1YK b0 cK 0dK +1eK sHdlNone\x20(0) BL sAddSub\x20(0) DL b0 FL @@ -41267,6 +41263,7 @@ b0 \W b0 fW 0lW b0 xW +1yW sHdlNone\x20(0) {W b0 |W b0 }W @@ -41317,6 +41314,7 @@ b0 'Z 0-Z 0;Z 0aZ +1'[ sHdlNone\x20(0) )[ b0 *[ b0 +[ @@ -41325,6 +41323,8 @@ sHdlNone\x20(0) 4[ b0 5[ sHdlNone\x20(0) j[ b0 k[ +1w[ +1b\ #18000000 0! b1000010001000 p diff --git a/crates/cpu/tests/next_pc.rs b/crates/cpu/tests/next_pc.rs new file mode 100644 index 0000000..9af026d --- /dev/null +++ b/crates/cpu/tests/next_pc.rs @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use cpu::{ + config::{CpuConfig, UnitConfig}, + next_pc::{ + DecodeToPostDecodeInterface, DecodeToPostDecodeInterfaceInner, FETCH_BLOCK_ID_WIDTH, + NextPcToFetchInterface, NextPcToFetchInterfaceInner, WipDecodedInsn, WipDecodedInsnKind, + next_pc, + }, + unit::UnitKind, + util::array_vec::ArrayVec, +}; +use fayalite::{prelude::*, sim::vcd::VcdWriterDecls, util::RcWriter}; +use std::{ + cell::Cell, + collections::{BTreeMap, VecDeque}, + num::NonZeroUsize, +}; + +#[derive(Copy, Clone, Debug)] +enum MockInsn { + Nop4, + Jump { target: u64 }, + CondBranch { target: u64 }, + Call { target: u64 }, + Ret, +} + +impl MockInsn { + fn byte_len(self) -> u64 { + match self { + MockInsn::Nop4 => 4, + MockInsn::Jump { .. } => 4, + MockInsn::CondBranch { .. } => 4, + MockInsn::Call { .. } => 4, + MockInsn::Ret => 4, + } + } +} + +#[derive(Debug)] +struct MockInsns { + insns: BTreeMap, +} + +impl MockInsns { + fn new() -> Self { + Self { + insns: BTreeMap::from_iter([ + (0x0, MockInsn::Nop4), + (0x4, MockInsn::Nop4), + (0x8, MockInsn::CondBranch { target: 0x4 }), + (0xC, MockInsn::Call { target: 0x18 }), + (0x10, MockInsn::Jump { target: 0x10 }), + (0x14, MockInsn::Jump { target: 0x10 }), + (0x18, MockInsn::Jump { target: 0x1C }), + (0x1C, MockInsn::Ret), + ]), + } + } + fn fetch_block(&self, pc_range: std::ops::Range) -> impl Iterator { + self.insns + .range(pc_range.clone()) + .filter_map(move |(&pc, &insn)| { + if pc_range.end >= pc + insn.byte_len() { + Some((pc, insn)) + } else { + None + } + }) + } +} + +const FETCH_PIPE_QUEUE_SIZE: usize = 5; + +const DEMO_ILLEGAL_INSN_TRAP: u64 = 0xFF000000u64; + +#[hdl] +struct FetchPipeQueueEntry { + fetch_pc: UInt<64>, + cycles_left: UInt<8>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, +} + +impl FetchPipeQueueEntry { + #[hdl] + fn default_sim(self) -> SimValue { + #[hdl(sim)] + FetchPipeQueueEntry { + fetch_pc: 0u64, + cycles_left: 0u8, + fetch_block_id: 0u8, + } + } + fn get_next_delay(delay_sequence_index: &Cell) -> u8 { + let index = delay_sequence_index.get(); + delay_sequence_index.set(delay_sequence_index.get().wrapping_add(1)); + // make a pseudo-random number deterministically based on index + let random = index + .wrapping_add(1) + .wrapping_mul(0x18C49126EABE7A0D) // random prime + .rotate_left(32) + .wrapping_mul(0x92B38C197608A6B) // random prime + .rotate_right(60); + (random % 8) as u8 + } +} + +#[hdl_module(extern)] +fn mock_fetch_pipe(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let from_fetch: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_post_decode: DecodeToPostDecodeInterface> = + m.output(DecodeToPostDecodeInterface[config]); + #[hdl] + let queue_debug: ArrayVec> = + m.output(); + m.register_clock_for_past(cd.clk); + m.extern_module_simulation_fn( + (cd, from_fetch, to_post_decode, queue_debug), + |(cd, from_fetch, to_post_decode, queue_debug), mut sim| async move { + // intentionally have a different sequence each time we're reset + let delay_sequence_index = Cell::new(0); + sim.resettable( + cd, + async |mut sim| { + sim.write(from_fetch.inner.ready, false).await; + sim.write( + to_post_decode.inner.data, + to_post_decode.ty().inner.data.HdlNone(), + ) + .await; + sim.write( + queue_debug, + queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim()), + ) + .await; + }, + |sim, ()| { + run_fn( + cd, + from_fetch, + to_post_decode, + queue_debug, + &delay_sequence_index, + sim, + ) + }, + ) + .await; + }, + ); + #[hdl] + async fn run_fn( + cd: Expr, + from_fetch: Expr>>, + to_post_decode: Expr>>, + queue_debug: Expr>>, + delay_sequence_index: &Cell, + mut sim: ExternModuleSimulationState, + ) { + let config = from_fetch.config.ty(); + let mock_insns = MockInsns::new(); + let mut queue: VecDeque> = VecDeque::new(); + let mut next_id = 0u32; + loop { + let mut sim_queue = queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim()); + for entry in &queue { + ArrayVec::try_push_sim(&mut sim_queue, entry) + .ok() + .expect("queue is known to be small enough"); + } + sim.write(queue_debug, sim_queue).await; + if let Some(front) = queue.front().filter(|v| v.cycles_left.as_int() == 0) { + #[hdl(sim)] + let FetchPipeQueueEntry { + fetch_pc, + cycles_left: _, + fetch_block_id, + } = front; + let fetch_pc = fetch_pc.as_int(); + let fetch_end = + (fetch_pc + 1).next_multiple_of(config.get().fetch_width_in_bytes() as u64); + let insns = to_post_decode.ty().inner.data.HdlSome.insns; + let zeroed_insn = UInt[insns.element().canonical().bit_width()] + .zero() + .cast_bits_to(insns.element()); + let mut insns = insns.new_sim(zeroed_insn); + let mut expected_pc = fetch_pc; + // TODO: handle instructions that go past the end of a fetch block + for (pc, insn) in mock_insns.fetch_block(fetch_pc..fetch_end) { + let next_pc = pc + insn.byte_len(); + if pc != expected_pc { + break; + } + expected_pc = next_pc; + let kind = match insn { + MockInsn::Nop4 => WipDecodedInsnKind.NonBranch(), + MockInsn::Jump { target } => WipDecodedInsnKind.Branch(target), + MockInsn::CondBranch { target } => WipDecodedInsnKind.BranchCond(target), + MockInsn::Call { target } => WipDecodedInsnKind.Call(target), + MockInsn::Ret => WipDecodedInsnKind.Ret(), + }; + let insn = #[hdl(sim)] + WipDecodedInsn { + fetch_block_id, + id: next_id.cast_to_static::>(), + pc, + size_in_bytes: insn.byte_len().cast_to_static::>(), + kind, + }; + match ArrayVec::try_push_sim(&mut insns, insn) { + Ok(()) => next_id = next_id.wrapping_add(1), + Err(_) => break, + } + } + if **ArrayVec::len_sim(&insns) == 0 { + let Ok(()) = ArrayVec::try_push_sim( + &mut insns, + #[hdl(sim)] + WipDecodedInsn { + fetch_block_id, + id: next_id.cast_to_static::>(), + pc: fetch_pc, + size_in_bytes: 0u8.cast_to_static::>(), + kind: WipDecodedInsnKind.Interrupt(DEMO_ILLEGAL_INSN_TRAP), + }, + ) else { + unreachable!(); + }; + next_id = next_id.wrapping_add(1); + } + sim.write( + to_post_decode.inner.data, + HdlSome( + #[hdl(sim)] + DecodeToPostDecodeInterfaceInner::<_> { insns, config }, + ), + ) + .await; + } else { + sim.write( + to_post_decode.inner.data, + to_post_decode.ty().inner.data.HdlNone(), + ) + .await; + } + sim.write(from_fetch.inner.ready, queue.len() < FETCH_PIPE_QUEUE_SIZE) + .await; + sim.wait_for_clock_edge(cd.clk).await; + if sim.read_past_bool(to_post_decode.inner.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(_) = sim.read_past(to_post_decode.inner.data, cd.clk).await { + queue.pop_front(); + } + } + for entry in &mut queue { + if entry.cycles_left.as_int() > 0 { + entry.cycles_left = (entry.cycles_left.as_int() - 1u8).to_sim_value(); + } + } + if !sim.read_past_bool(from_fetch.inner.ready, cd.clk).await { + continue; + } + #[hdl(sim)] + if let HdlSome(inner) = sim.read_past(from_fetch.inner.data, cd.clk).await { + #[hdl(sim)] + let NextPcToFetchInterfaceInner { + next_fetch_pc, + fetch_block_id, + in_progress_fetches_to_cancel, + } = &inner; + // cancel in-progress fetches from newest to oldest + for _ in 0..in_progress_fetches_to_cancel.as_int() { + let _ = queue.pop_back(); + } + queue.push_back( + #[hdl(sim)] + FetchPipeQueueEntry { + fetch_pc: next_fetch_pc, + cycles_left: FetchPipeQueueEntry::get_next_delay(delay_sequence_index), + fetch_block_id, + }, + ); + } + } + } +} + +#[hdl_module] +fn dut(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let next_pc = instance(next_pc(config)); + connect(next_pc.cd, cd); + #[hdl] + let mock_fetch_pipe = instance(mock_fetch_pipe(config)); + connect(mock_fetch_pipe.cd, cd); + connect(mock_fetch_pipe.from_fetch, next_pc.to_fetch); + connect(next_pc.from_decode, mock_fetch_pipe.to_post_decode); +} + +#[hdl] +#[test] +fn test_next_pc() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut config = CpuConfig::new( + vec![ + UnitConfig::new(UnitKind::AluBranch), + UnitConfig::new(UnitKind::AluBranch), + ], + NonZeroUsize::new(20).unwrap(), + ); + config.fetch_width = NonZeroUsize::new(2).unwrap(); + let m = dut(PhantomConst::new_sized(config)); + let mut sim = Simulation::new(m); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + for _cycle in 0..300 { + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + // FIXME: vcd is just whatever next_pc does now, which isn't known to be correct + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("expected/next_pc.vcd") { + panic!(); + } +} diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs index f9a292c..18c84f4 100644 --- a/crates/cpu/tests/reg_alloc.rs +++ b/crates/cpu/tests/reg_alloc.rs @@ -59,7 +59,7 @@ fn test_reg_alloc() { [HdlSome(()), HdlNone()], }, [0u8; 2], - 0x12345678u32.cast_to_static(), + 0x12345678u32.cast_to_static::>(), OutputIntegerMode.DupLow32(), false, false, @@ -81,7 +81,7 @@ fn test_reg_alloc() { [HdlSome(()), HdlNone()], }, [1u8, 0, 0], - 1.cast_to_static(), + 1.cast_to_static::>(), OutputIntegerMode.Full64(), false, false, @@ -99,7 +99,7 @@ fn test_reg_alloc() { flag_regs: [HdlNone(), HdlSome(())], }, [2u8, 4u8], - 0.cast_to_static(), + 0.cast_to_static::>(), OutputIntegerMode.Full64(), 0b0110_hdl_u4, ),