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Author	SHA1	Message	Date
Jacob Lifshay	bf2cb688c7	implement register fences and use for L2 reg file writes and when running out of L2 reg file output regs ... fixes deadlock when running rename_execute_retire_save_restore_gprs	2026-05-21 17:23:57 -07:00
Jacob Lifshay	3e08a282ec	add test_rename_execute_retire_save_restore_gprs ... currently it fails due to the L2 reg file running out of output registers	2026-05-20 19:44:20 -07:00
Jacob Lifshay	6026df8d7a	rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput	2026-05-20 17:02:34 -07:00
Jacob Lifshay	e502dfe574	rename_execute_retire: don't include completed instructions in space used by a unit	2026-05-20 16:56:58 -07:00
Jacob Lifshay	0d69666b00	tests/rename_execute_retire: add and use mock_combinational_unit	2026-05-19 19:33:09 -07:00
Jacob Lifshay	2363e65564	tests/rename_execute_retire: make loads/stores take more than one cycle to execute	2026-05-19 18:08:07 -07:00
Jacob Lifshay	79ac190093	rename_execute_retire: add a head -n1 test	2026-05-18 22:22:31 -07:00
Jacob Lifshay	0d3c41fa14	add TraceAsString around instructions and stuff to make the .vcd files much smaller and easier to read	2026-05-14 22:38:50 -07:00
Jacob Lifshay	8bee576a2a	update fayalite to get TraceAsString	2026-05-14 22:28:25 -07:00
Jacob Lifshay	3fbdab0862	rename_execute_retire: implement generating L2 reg file writes	2026-05-10 23:39:02 -07:00
Jacob Lifshay	33b5d59507	improve debug formatting of PRegValue and PRegFlags	2026-05-07 21:40:23 -07:00
Jacob Lifshay	559e2967a2	improve debug formatting of MOpRegNum/MOpDestReg	2026-05-07 21:25:27 -07:00
Jacob Lifshay	5e6041a97c	change MOp to use SrcReg: Type instead of UIntType<SrcRegWidth>	2026-05-07 19:56:56 -07:00
Jacob Lifshay	409ca7bf97	update decode_one_insn.vcd for modified instruction data structures	2026-05-05 21:52:02 -07:00
Jacob Lifshay	9308e5d195	update fayalite to fix bug in VCD generation	2026-05-05 21:28:46 -07:00
Jacob Lifshay	09c8c194e0	group micro ops by the instruction they come from when retiring	2026-05-05 19:33:25 -07:00
Jacob Lifshay	83b3f7bac9	use custom debug	2026-05-03 23:35:19 -07:00
Jacob Lifshay	ba9ec3bd29	adapt code for new fayalite features	2026-05-03 23:35:19 -07:00
Jacob Lifshay	1229d9c758	update fayalite for optimizations and new features	2026-05-03 23:35:19 -07:00
Jacob Lifshay	283117d8df	add support for speculative loads	2026-04-30 17:51:33 -07:00
Jacob Lifshay	4d21ca622b	add initial impl of rename_execute_retire; running a recursive fibonacci gives the correct output	2026-04-24 18:13:27 -07:00
Jacob Lifshay	6ed04c809e	update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name	2026-03-26 19:21:52 -07:00
Jacob Lifshay	a1147f0f05	add sram and main_memory_and_io modules	2026-03-26 02:03:06 -07:00
Jacob Lifshay	5bdc71acc3	add memory_interface_adapter_no_split	2026-03-26 02:03:06 -07:00
Jacob Lifshay	a15367c37e	add address_range to MemoryInterfaceConfig and add support to simple_uart	2026-03-24 23:46:46 -07:00
Jacob Lifshay	0d451e4e95	change MemoryInterface types to have their own config	2026-03-24 23:46:46 -07:00
Jacob Lifshay	689b4ef65a	implement simple_uart::simple_uart	2026-03-24 23:46:46 -07:00
Jacob Lifshay	79eac8929a	add test for simple_uart::receiver	2026-03-24 23:46:46 -07:00
Jacob Lifshay	f372190b68	add main_memory_and_io::simple_uart::receiver* and test for receiver_no_queue	2026-03-24 23:46:46 -07:00
Jacob Lifshay	e31375b9ce	add main_memory_and_io::simple_uart::{transmitter, uart_clock_gen} and tests	2026-03-24 23:46:46 -07:00
Jacob Lifshay	4ffaba8840	add MemoryOperationStart.rw_mask	2026-03-24 23:46:46 -07:00
Jacob Lifshay	4de29dd16e	move MemoryInterface and related types to crate::main_memory_and_io	2026-03-24 23:46:46 -07:00
Jacob Lifshay	245b872cf7	update to latest fayalite	2026-03-24 23:46:46 -07:00
Jacob Lifshay	e69c92c8da	add fetch::fetch and fetch::l1_i_cache with some testing	2026-02-21 18:32:01 -08:00
Jacob Lifshay	c62d33048c	update fayalite to c632e5d570 to speed up simulation	2026-02-04 16:33:46 -08:00
Jacob Lifshay	596440755c	update fayalite to include 1bc835803b for a major speedup of the decoder tests	2026-02-03 18:17:31 -08:00
Jacob Lifshay	68a4373bbd	update rust version to 1.93.0	2026-02-03 18:17:18 -08:00
Jacob Lifshay	f88346ea37	implement decoding mtspr/mfspr/mftb	2026-01-28 17:35:09 -08:00
Jacob Lifshay	a42b76b468	implement decoding all rotate instructions	2026-01-27 19:18:27 -08:00
Jacob Lifshay	130c1b2892	change CommonMOp to directly contain a generic immediate type	2026-01-27 17:03:14 -08:00
Jacob Lifshay	167bc4b6a6	implement decoding extswsli[.]	2026-01-26 19:18:44 -08:00
Jacob Lifshay	faa8dde774	reduce the number of wires to have one per form/field pair instead of one per insn/field pair	2026-01-26 16:11:03 -08:00
Jacob Lifshay	1db65ae753	implement decoding shifts: s[lr][wd][.] and sra[wd][i][.]	2026-01-26 15:14:26 -08:00
Jacob Lifshay	59874b9b29	add shift/rotate MOp definition	2026-01-25 20:34:38 -08:00
Jacob Lifshay	2ad469e331	simplify getting IMM_WIDTH for LogicalFlagsMOpImm	2026-01-25 20:25:25 -08:00
Jacob Lifshay	0824b63d31	implement decoding 8/16/32/64-bit store instructions -- all of Power ISA v3.1c Book I 3.3.3	2026-01-25 15:06:14 -08:00
Jacob Lifshay	706d54ae0d	implement decoding 8/16/32/64-bit load instructions -- all of Power ISA v3.1C Book I 3.3.2	2026-01-23 16:06:16 -08:00
Jacob Lifshay	d361a2b578	make LogicalFlagsMOp also copy the dest PRegValue.flags into PRegValue.int_fp	2026-01-23 12:13:06 -08:00
Jacob Lifshay	aa07e24c78	make check-copyright.sh also handle other tests/.../expected/... files	2026-01-23 12:13:06 -08:00
Jacob Lifshay	29757a568c	implement decoding mcrf	2026-01-23 11:47:06 -08:00