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yosys/passes/techmap
Akash Levy 1cba744712 Update
2024-11-04 17:01:41 -08:00
..
abc.cc
abc9.cc
abc9_exe.cc
abc9_ops.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
abc_new.cc
aigmap.cc
alumacc.cc
attrmap.cc
attrmvcp.cc
bmuxmap.cc Bmux unq 2024-11-04 12:03:53 -08:00
booth.cc
bufnorm.cc
bwmuxmap.cc
cellmatch.cc cellmatch: Visit whiteboxes for -derive_luts 2024-11-04 14:28:46 +01:00
clkbufmap.cc
clockgate.cc
deminout.cc
demuxmap.cc
dffinit.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
dfflegalize.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
dfflibmap.cc
dffunmap.cc
extract.cc
extract_counter.cc
extract_fa.cc
extract_reduce.cc
extractinv.cc
filterlib.cc
flatten.cc
flowmap.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
hilomap.cc
insbuf.cc
iopadmap.cc
libparse.cc Fix colon issue 2024-11-01 17:49:29 -07:00
libparse.h
lut2mux.cc
maccmap.cc
Makefile.inc Add abc, some techmap passes, make opt_balance_tree only balance add/mul 2024-10-30 00:38:05 -07:00
muxcover.cc
nlutmap.cc
pmuxtree.cc
shregmap.cc
simplemap.cc
simplemap.h
techmap.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
tribuf.cc
zinit.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00