Emil J. Tywoniak eb32507cb5 tests: exclude signorm marker cells from cell-count assertions ... $input_port, $output_port and $public are signorm bookkeeping rather than mapped logic, so assertions counting "every cell" or "every $ cell" have to subtract them -- as tests/opt/opt_expr_*.ys already do with `t:$*_port %d t:$public %d`. The memlib assertions are generated, so the fix goes in generate_mk.py rather than the generated scripts. These only differ once a design can still be in signorm mode when the assertion runs; the subtraction is a no-op otherwise. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo		2026-07-21 14:05:18 +02:00
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bug2619.ys
bug2656.ys
bug2962.ys	Remove references to ilang	2024-11-05 12:36:31 +13:00
bug4712.ys	tests/proc: add proc_dff bug 4712 as testcase	2024-11-07 00:10:17 +01:00
bug5572.ys	Test empty switches	2026-01-07 13:21:33 +13:00
bug_1268.v
bug_1268.ys
case_attr.ys	tests: add cases covering full_case and parallel_case semantics	2025-05-29 20:45:57 -06:00
clean_undef_case.ys
generate_mk.py	Converted some more	2026-04-16 11:00:44 +02:00
proc_dff.ys	proc_dff: add tests	2024-08-28 16:24:47 +01:00
proc_dlatch.ys	Fixup issue test.	2026-06-15 16:23:44 +02:00
proc_latches.ys	Fixup level policy.	2026-06-18 18:00:51 +02:00
proc_mux_src.v	proc_mux, genrtlil: make use of case_src for better case condition vs block tracking	2026-07-20 15:01:30 +02:00
proc_mux_src.ys	proc_mux: include switch expression location in $eq src	2026-07-20 15:01:30 +02:00
proc_rom.ys	Remove references to ilang	2024-11-05 12:36:31 +13:00
rmdead.v
rmdead.ys
rmdead_case_x.ys	Add tests.	2026-06-25 11:14:54 +02:00
yosys_latch.sv	Add tests.	2026-06-15 15:46:13 +02:00
yosys_latch.ys	tests: exclude signorm marker cells from cell-count assertions	2026-07-21 14:05:18 +02:00