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Add tests.

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nella 2026-06-15 15:46:13 +02:00
parent a5bdb29d7f
commit eb4703808a
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89
tests/proc/proc_dlatch.ys Normal file
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read_verilog -formal <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
always @* begin
if (~rn) assert(q == 0);
else if (g) assert(q == d);
end
endmodule
EOT
proc
select -assert-count 1 t:$adlatch
select -assert-count 0 t:$dlatch
select -assert-count 0 t:$dlatchsr
simplemap
select -assert-count 1 t:$_DLATCH_PN0_
clk2fflogic
sat -tempinduct -verify -prove-asserts
design -reset
read_verilog -formal <<EOT
module top(input gn, rn, d, output reg q);
always @* if (rn==0) q <= 0; else if (gn==0) q <= d;
always @* begin
if (rn==0) assert(q == 0);
else if (gn==0) assert(q == d);
end
endmodule
EOT
proc
select -assert-count 1 t:$adlatch
simplemap
select -assert-count 1 t:$_DLATCH_NN0_
clk2fflogic
sat -tempinduct -verify -prove-asserts
design -reset
read_verilog -formal <<EOT
module top(input g, sn, d, output reg q);
always @* if (~sn) q <= 1; else if (g) q <= d;
always @* begin
if (~sn) assert(q == 1);
else if (g) assert(q == d);
end
endmodule
EOT
proc
select -assert-count 1 t:$adlatch
simplemap
select -assert-count 1 t:$_DLATCH_PN1_
clk2fflogic
sat -tempinduct -verify -prove-asserts
design -reset
read_verilog -formal <<EOT
module top(input g, sn, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (~sn) q <= 1; else if (g) q <= d;
always @* begin
if (~rn) assert(q == 0);
else if (~sn) assert(q == 1);
else if (g) assert(q == d);
end
endmodule
EOT
proc
select -assert-count 0 t:$adlatch
select -assert-count 0 t:$dlatchsr
select -assert-count 1 t:$dlatch
clk2fflogic
sat -tempinduct -verify -prove-asserts
design -reset
read_verilog <<EOT
module top(input g, d, output reg q);
always @* if (g) q <= d;
endmodule
EOT
proc
select -assert-count 1 t:$dlatch
select -assert-count 0 t:$adlatch

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tests/proc/yosys_latch.sv Normal file
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module yosys_latch (
input logic dlatch_p_d, input logic dlatch_p_g, output logic dlatch_p_q,
input logic dlatch_n_d, input logic dlatch_n_gn, output logic dlatch_n_q,
input logic dlatch_pn0_d, input logic dlatch_pn0_rn, input logic dlatch_pn0_g, output logic dlatch_pn0_q,
input logic dlatch_nn0_d, input logic dlatch_nn0_rn, input logic dlatch_nn0_gn, output logic dlatch_nn0_q
);
always_latch if (dlatch_p_g) dlatch_p_q <= dlatch_p_d;
always_latch if (~dlatch_n_gn) dlatch_n_q <= dlatch_n_d;
always_latch if (~dlatch_pn0_rn) dlatch_pn0_q <= 1'b0; else if (dlatch_pn0_g) dlatch_pn0_q <= dlatch_pn0_d;
always @* if (dlatch_nn0_rn == 1'b0) dlatch_nn0_q <= 1'b0; else if (dlatch_nn0_gn == 1'b0) dlatch_nn0_q <= dlatch_nn0_d;
endmodule

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tests/proc/yosys_latch.ys Normal file
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# https://github.com/YosysHQ/yosys/issues/5910
read_verilog -sv yosys_latch.sv
hierarchy -check -top yosys_latch
proc
design -save gold
opt
select -assert-count 2 t:$adlatch
select -assert-count 2 t:$dlatch
simplemap
opt_clean
select -assert-count 1 t:$_DLATCH_P_
select -assert-count 1 t:$_DLATCH_N_
select -assert-count 1 t:$_DLATCH_PN0_
select -assert-count 1 t:$_DLATCH_NN0_
select -assert-count 4 t:*
design -load gold
equiv_opt -assert -multiclock simplemap
design -reset

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tests/techmap/dfflegalize_dlatch_emu.ys Normal file
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read_verilog -icells <<EOT
module top(input E, S, R, D, output [5:0] Q);
$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
$_DLATCH_PP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
$_DLATCH_PN1_ ff3 (.E(E), .R(R), .D(D), .Q(Q[3]));
$_DLATCHSR_PPP_ ff4 (.E(E), .S(S), .R(R), .D(D), .Q(Q[4]));
$_DLATCHSR_PNP_ ff5 (.E(E), .S(S), .R(R), .D(D), .Q(Q[5]));
endmodule
EOT
design -save orig
logger -expect warning "Emulating async reset latch with a plain D latch" 4
logger -expect warning "Emulating async set \+ reset latch with a plain D latch" 2
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
logger -check-expected
design -load orig
dfflegalize -cell $_DLATCH_P_ x
select -assert-count 6 t:$_DLATCH_P_
select -assert-count 0 t:$_DLATCHSR_???_
select -assert-count 0 t:$_DLATCH_??0_
select -assert-count 0 t:$_DLATCH_??1_