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yosys/frontends/verilog
2025-07-31 15:08:41 +02:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
Makefile.inc Add state_dependent_path_declaration so that ifnone can be parsed 2025-05-14 21:13:47 +02:00
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc Update verilog_frontend.cc 2025-05-08 10:37:04 +12:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l Merge bb4dd595ed into 262b00d5e5 2025-07-31 15:08:41 +02:00
verilog_parser.y Merge bb4dd595ed into 262b00d5e5 2025-07-31 15:08:41 +02:00