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eb5da87d52
Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block. Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section. Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading). Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.
48 lines
2.3 KiB
Plaintext
48 lines
2.3 KiB
Plaintext
read_verilog fifo.v
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synth_ice40 -top fifo -run begin:map_ram
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# this point should be the same as rdata_coarse
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# ========================================================
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synth_ice40 -top fifo -run map_ram:map_ffram
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select -set mem t:SB_RAM40_4K
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select -set remap @mem %ci:+SB_RAM40_4K[RADDR] @mem %co %%
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 @mem -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffram:map_gates
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select -set mem t:SB_RAM40_4K
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select -set remap @mem %co @mem %d
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 @mem -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ffram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_gates:map_ffs
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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select -set multibit t:$_MUX_ t:$_DFFE_*_
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select -set alu t:$_OR_ t:$_NOT_ t:$lut %% %ci %% w:fifo_reader.addr %d i:* %d
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show -color maroon3 @multibit -color cornflowerblue @alu -notitle -format dot -prefix rdata_map_gates @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffs:map_luts
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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select -set dff t:SB_DFFER
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select -set primitives t:$_AND_ %ci i:* %d
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show -color maroon3 @dff -color cornflowerblue @primitives -notitle -format dot -prefix rdata_map_ffs @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_luts:map_cells
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 t:SB_CARRY -color cornflowerblue t:$lut -notitle -format dot -prefix rdata_map_luts @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_cells:
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 t:SB_LUT* -notitle -format dot -prefix rdata_map_cells @rdata_path
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