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example_synth: hardware mapping
Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block. Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section. Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading). Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.
This commit is contained in:
Krystine Sherwin
parent
e6f8804e6a
commit
eb5da87d52
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@ -374,56 +374,9 @@ yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc
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Writing dot description to `rdata_alumacc.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> memory -nomap
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23. Executing MEMORY pass.
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yosys> opt_mem
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23.1. Executing OPT_MEM pass (optimize memories).
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Performed a total of 0 transformations.
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yosys> opt_mem_priority
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23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
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Performed a total of 0 transformations.
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yosys> opt_mem_feedback
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23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
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yosys> memory_bmux2rom
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23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
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yosys> memory_dff
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23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
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yosys> opt_clean
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23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \fifo..
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Removed 1 unused cells and 9 unused wires.
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<suppressed ~2 debug messages>
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yosys> memory_share
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23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
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yosys> opt_mem_widen
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23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
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Performed a total of 0 transformations.
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yosys> opt_clean
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23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \fifo..
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yosys> memory_collect
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23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
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23. Executing MEMORY_COLLECT pass (generating $mem cells).
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yosys> select -set new_cells t:$mem_v2
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@ -65,7 +65,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdat
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# ========================================================
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memory -nomap
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memory_collect
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# or use the following commands:
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# design -reset
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# read_verilog fifo.v
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@ -5,41 +5,43 @@ synth_ice40 -top fifo -run begin:map_ram
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# ========================================================
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synth_ice40 -top fifo -run map_ram:map_ffram
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ram @rdata_path
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select -set mem t:SB_RAM40_4K
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select -set remap @mem %ci:+SB_RAM40_4K[RADDR] @mem %co %%
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 @mem -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffram:map_gates
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffram @rdata_path
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select -set mem t:SB_RAM40_4K
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select -set remap @mem %co @mem %d
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 @mem -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ffram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_gates:map_ffs
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_gates @rdata_path
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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select -set multibit t:$_MUX_ t:$_DFFE_*_
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select -set alu t:$_OR_ t:$_NOT_ t:$lut %% %ci %% w:fifo_reader.addr %d i:* %d
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show -color maroon3 @multibit -color cornflowerblue @alu -notitle -format dot -prefix rdata_map_gates @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffs:map_luts
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffs @rdata_path
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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select -set dff t:SB_DFFER
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select -set primitives t:$_AND_ %ci i:* %d
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show -color maroon3 @dff -color cornflowerblue @primitives -notitle -format dot -prefix rdata_map_ffs @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_luts:map_cells
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_luts @rdata_path
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 t:SB_CARRY -color cornflowerblue t:$lut -notitle -format dot -prefix rdata_map_luts @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_cells:
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_cells @rdata_path
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select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
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show -color maroon3 t:SB_LUT* -notitle -format dot -prefix rdata_map_cells @rdata_path
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@ -508,20 +508,39 @@ see produce the following changes in our example design:
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``rdata`` output after :cmd:ref:`alumacc`
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.. TODO:: discuss :cmd:ref:`memory_collect` and ``$mem_v2``
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The other new command in this part is :doc:`/cmd/memory`. :cmd:ref:`memory` is
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another macro command which we examine in more detail in
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:doc:`/using_yosys/synthesis/memory`. For this document, let us focus just on
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the step most relevant to our example: :cmd:ref:`memory_collect`. Up until this
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point, our memory reads and our memory writes have been totally disjoint cells;
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operating on the same memory only in the abstract. :cmd:ref:`memory_collect`
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combines all of the reads and writes for a memory block into a single cell.
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.. figure:: /_images/code_examples/fifo/rdata_coarse.*
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:class: width-helper
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:name: rdata_coarse
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``rdata`` output after :yoscrypt:`memory -nomap`
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``rdata`` output after :cmd:ref:`memory_collect`
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We could also have gotten here by running :yoscrypt:`synth_ice40 -top fifo -run
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begin:map_ram` after loading the design.
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Looking at the schematic after running :cmd:ref:`memory_collect` we see that our
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``$memrd_v2`` cell has been replaced with a ``$mem_v2`` cell named ``data``, the
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same name that we used in :ref:`fifo-v`. Where before we had a single set of
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signals for address and enable, we now have one set for reading (``RD_*``) and
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one for writing (``WR_*``), as well as both ``WR_DATA`` input and ``RD_DATA``
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output.
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.. seealso:: Advanced usage docs for
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:doc:`/using_yosys/synthesis/memory`
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Final note
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^^^^^^^^^^
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Having now reached the end of the the coarse-grain representation, we could also
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have gotten here by running :yoscrypt:`synth_ice40 -top fifo -run :map_ram`
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after loading the design. The :yoscrypt:`-run <from_label>:<to_label>` option
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with an empty ``<from_label>`` starts from the :ref:`synth_begin`, while the
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``<to_label>`` runs up to but including the :ref:`map_ram`.
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Hardware mapping
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~~~~~~~~~~~~~~~~
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@ -535,8 +554,6 @@ Memory blocks
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Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap`,
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:cmd:ref:`memory_map`, and :cmd:ref:`techmap`.
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.. TODO:: ``$mem_v2`` -> ``SB_RAM40_4K``
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_ram:
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@ -551,6 +568,16 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap`,
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``rdata`` output after :ref:`map_ram`
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:ref:`map_ram` converts the generic ``$mem_v2`` into the iCE40 ``SB_RAM40_4K``
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(highlighted). We can also see the memory address has been remapped, and the
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data bits have been reordered (or swizzled). There is also now a ``$mux`` cell
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controlling the value of ``rdata``. In :ref:`fifo-v` we wrote our memory as
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read-before-write, however the ``SB_RAM40_4K`` has undefined behaviour when
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reading from and writing to the same address in the same cycle. As a result,
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extra logic is added so that the generated circuit matches the behaviour of the
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verilog. :ref:`no_rw_check` describes how we could change our verilog to match
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our hardware instead.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_ffram:
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@ -565,6 +592,8 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap`,
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``rdata`` output after :ref:`map_ffram`
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.. TODO:: what even is this opt output
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.. seealso:: Advanced usage docs for
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- :doc:`/using_yosys/synthesis/techmap_synth`
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@ -573,9 +602,11 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap`,
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Arithmetic
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^^^^^^^^^^
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Uses :cmd:ref:`techmap`.
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.. TODO:: example_synth/Arithmetic
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Uses :cmd:ref:`techmap` to map basic arithmetic logic to hardware. This sees
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somewhat of an explosion in cells as multi-bit ``$mux`` and ``$adffe`` are
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replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the
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``$alu`` is replaced with primitive ``$_OR_`` and ``$_NOT_`` gates and a
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``$lut`` cell.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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@ -598,9 +629,13 @@ Flip-flops
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^^^^^^^^^^
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Convert FFs to the types supported in hardware with :cmd:ref:`dfflegalize`, and
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then use :cmd:ref:`techmap` to map them. We also run :cmd:ref:`simplemap` here
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to convert any remaining cells which could not be mapped to hardware into
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gate-level primitives.
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then use :cmd:ref:`techmap` to map them. In our example, this converts the
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``$_DFFE_PP0P_`` cells to ``SB_DFFER``.
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We also run :cmd:ref:`simplemap` here to convert any remaining cells which could
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not be mapped to hardware into gate-level primitives. This includes optimizing
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``$_MUX_`` cells where one of the inputs is a constant ``1'0``, replacing it
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instead with an ``$_AND_`` cell.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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@ -622,9 +657,10 @@ gate-level primitives.
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LUTs
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^^^^
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:cmd:ref:`abc` and :cmd:ref:`techmap` are used to map LUTs. Note that the iCE40
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flow uses :cmd:ref:`abc` rather than :cmd:ref:`abc9`. For more on what these
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do, and what the difference between these two commands are, refer to
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:cmd:ref:`abc` and :cmd:ref:`techmap` are used to map LUTs; converting primitive
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cell types to use ``$lut`` and ``SB_CARRY`` cells. Note that the iCE40 flow
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uses :cmd:ref:`abc9` rather than :cmd:ref:`abc`. For more on what these do, and
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what the difference between these two commands are, refer to
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:doc:`/using_yosys/synthesis/abc`.
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.. literalinclude:: /cmd/synth_ice40.rst
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@ -641,15 +677,8 @@ do, and what the difference between these two commands are, refer to
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``rdata`` output after :ref:`map_luts`
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.. seealso:: Advanced usage docs for
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- :doc:`/using_yosys/synthesis/techmap_synth`
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- :doc:`/using_yosys/synthesis/abc`
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Other cells
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^^^^^^^^^^^
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Seems to be wide LUTs into individual LUTs using :cmd:ref:`techmap`.
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Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40
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``SB_LUT4`` cells.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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@ -665,7 +694,15 @@ Seems to be wide LUTs into individual LUTs using :cmd:ref:`techmap`.
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``rdata`` output after :ref:`map_cells`
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.. TODO:: example_synth other cells
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.. seealso:: Advanced usage docs for
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- :doc:`/using_yosys/synthesis/techmap_synth`
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- :doc:`/using_yosys/synthesis/abc`
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Other cells
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^^^^^^^^^^^
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The following commands may also be used for mapping other cells:
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:cmd:ref:`hilomap`
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Some architectures require special driver cells for driving a constant hi or
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@ -676,8 +713,8 @@ Seems to be wide LUTs into individual LUTs using :cmd:ref:`techmap`.
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Top-level input/outputs must usually be implemented using special I/O-pad
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cells. This command inserts such cells to the design.
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.. seealso:: Advanced usage docs for
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:doc:`/yosys_internals/techmap`
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These commands tend to either be in the :ref:`map_cells` or after the
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:ref:`check` depending on the flow.
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Final steps
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~~~~~~~~~~~~
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@ -253,6 +253,8 @@ Synchronous SDP read first
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read_data <= mem[read_addr];
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end
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.. _no_rw_check:
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Synchronous SDP with undefined collision behavior
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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