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yosys/techlibs/anlogic
History
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:09:37 +02:00
..
anlogic_eqn.cc Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
anlogic_fixcarry.cc Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
arith_map.v Fix missing newline at end of file 2019-08-22 18:09:37 +02:00
cells_map.v Merge pull request #750 from Icenowy/anlogic-ff-init 2019-01-02 15:52:22 +01:00
cells_sim.v Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
dram_init_16x4.vh anlogic: implement DRAM initialization 2018-12-20 07:56:15 +08:00
drams.txt anlogic: implement DRAM initialization 2018-12-20 07:56:15 +08:00
drams_map.v anlogic: implement DRAM initialization 2018-12-20 07:56:15 +08:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
Makefile.inc Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
synth_anlogic.cc Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00