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.gitignore
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tests: add a quick plugin test
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2020-04-09 09:45:20 -07:00 |
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abc9.v
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abc9.ys
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write_xaiger: fix for (* keep *) on flop output
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2020-01-21 09:43:04 -08:00 |
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async.sh
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async.v
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attrib05_port_conn.v
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attrib05_port_conn.ys
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attrib07_func_call.v
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attrib07_func_call.ys
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autoname.ys
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bug1496.ys
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bug1531.ys
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bug1614.ys
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add testcase for #1614
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2020-02-03 21:29:54 +01:00 |
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bug1710.ys
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
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2020-02-27 16:55:55 -08:00 |
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bug1745.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
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bug1781.ys
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fsm_extract: Initialize celltypes with full design.
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2020-03-19 18:51:21 +01:00 |
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bug1876.ys
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tests: add testcases from #1876
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2020-04-14 12:39:10 -07:00 |
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chparam.sh
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constcomment.ys
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Add regression tests for new handling of comments in constants
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2020-03-14 11:41:09 +01:00 |
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constmsk_test.v
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constmsk_test.ys
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constmsk_testmap.v
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deminout_unused.ys
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deminout: Don't demote inouts with unused bits
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2020-03-04 18:44:38 +00:00 |
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elab_sys_tasks.sv
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elab_sys_tasks.ys
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equiv_opt_multiclock.ys
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exec.ys
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Add test for exec command.
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2020-03-16 07:52:58 +00:00 |
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gzip_verilog.v.gz
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gzip_verilog.ys
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help.ys
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Add "help -all" and "help -celltypes" sanity test
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2020-01-28 18:11:34 -08:00 |
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hierarchy.sh
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hierarchy_defer.ys
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ice40_mince_abc9.ys
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Add test for abc9+mince issue
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2020-03-20 20:35:28 +00:00 |
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logger_error.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_nowarning.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_warn.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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logger_warning.ys
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Added back tests for logger
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2020-03-13 15:00:18 +01:00 |
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mem2reg.ys
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Change attribute search value to specify precise location instead of simple line number.
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2020-02-24 01:39:36 +00:00 |
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muxcover.ys
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muxpack.v
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muxpack.ys
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peepopt.ys
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plugin.cc
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tests: add a quick plugin test
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2020-04-09 09:45:20 -07:00 |
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plugin.sh
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tests: add a quick plugin test
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2020-04-09 09:45:20 -07:00 |
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pmgen_reduce.ys
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pmux2shiftx.v
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
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pmux2shiftx.ys
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reg_wire_error.sv
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reg_wire_error.ys
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run-test.sh
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scratchpad.ys
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script.ys
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sformatf.ys
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shregmap.v
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shregmap.ys
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signext.ys
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specify.v
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verilog: ignore ranges too without -specify
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2020-02-13 17:58:43 -08:00 |
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specify.ys
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clean: ignore specify-s inside cells when determining whether to keep
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2020-02-19 10:45:10 -08:00 |
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src.ys
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verilog: add test
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2020-03-11 06:51:03 -07:00 |
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submod.ys
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submod_extract.ys
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sv_defines.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_dup.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_mismatch.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_defines_too_few.ys
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Add support for SystemVerilog-style `define to Verilog frontend
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2020-03-27 16:08:26 +00:00 |
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sv_implicit_ports.sh
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sv: More tests for wildcard port connections
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2020-02-02 16:12:33 +00:00 |
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svalways.sh
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wreduce.ys
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write_gzip.ys
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