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yosys/tests/verific/README.md
2024-10-02 23:09:36 -07:00

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# Verific Test Cases
## Disabled
- `bounds`: checks top and bottom bound attributes, which are removed to avoid OpenSTA issues
- `memory_semantics`: relies on initial values being retained, which we do not want
- `rom_case`: relies on using Verific's VHDL frontend rather than GHDL