mirror of
https://github.com/YosysHQ/yosys
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100 lines
No EOL
2.2 KiB
Text
100 lines
No EOL
2.2 KiB
Text
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library(supergate) {
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technology (cmos);
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revision : 1.0;
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time_unit : "1ps";
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pulling_resistance_unit : "1kohm";
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voltage_unit : "1V";
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current_unit : "1uA";
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capacitive_load_unit(1,ff);
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default_inout_pin_cap : 7.0;
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default_input_pin_cap : 7.0;
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default_output_pin_cap : 0.0;
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default_fanout_load : 1.0;
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default_wire_load_capacitance : 0.1;
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default_wire_load_resistance : 1.0e-3;
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default_wire_load_area : 0.0;
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input_threshold_pct_rise : 50;
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input_threshold_pct_fall : 50;
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output_threshold_pct_rise : 50;
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output_threshold_pct_fall : 50;
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slew_lower_threshold_pct_rise : 30;
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slew_lower_threshold_pct_fall : 30;
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slew_upper_threshold_pct_rise : 70;
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slew_upper_threshold_pct_fall : 70;
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nom_process : 1.0;
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nom_temperature : 25.0;
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nom_voltage : 1.2;
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delay_model : generic_cmos;
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/* Latch */
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cell(latch) {
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area : 5;
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latch ("IQ","IQN") {
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enable : (G);
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data_in : "D";
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}
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pin(D) {
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direction : input;
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}
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pin(G) {
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direction : input;
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}
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pin(Q) {
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direction : output;
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function : "IQ";
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internal_node : "Q";
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timing() {
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timing_type : rising_edge;
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intrinsic_rise : 65;
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intrinsic_fall : 65;
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rise_resistance : 0;
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fall_resistance : 0;
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related_pin : "G";
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}
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timing() {
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timing_sense : positive_unate;
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intrinsic_rise : 65;
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intrinsic_fall : 65;
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rise_resistance : 0;
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fall_resistance : 0;
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related_pin : "D";
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}
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}
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pin(QN) {
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direction : output;
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function : "IQN";
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internal_node : "QN";
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timing() {
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timing_type : rising_edge;
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intrinsic_rise : 65;
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intrinsic_fall : 65;
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rise_resistance : 0;
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fall_resistance : 0;
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related_pin : "G";
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}
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timing() {
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timing_sense : negative_unate;
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intrinsic_rise : 65;
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intrinsic_fall : 65;
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rise_resistance : 0;
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fall_resistance : 0;
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related_pin : "D";
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}
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}
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}
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} |