library(supergate) { technology (cmos); revision : 1.0; time_unit : "1ps"; pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; current_unit : "1uA"; capacitive_load_unit(1,ff); default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; default_fanout_load : 1.0; default_wire_load_capacitance : 0.1; default_wire_load_resistance : 1.0e-3; default_wire_load_area : 0.0; input_threshold_pct_rise : 50; input_threshold_pct_fall : 50; output_threshold_pct_rise : 50; output_threshold_pct_fall : 50; slew_lower_threshold_pct_rise : 30; slew_lower_threshold_pct_fall : 30; slew_upper_threshold_pct_rise : 70; slew_upper_threshold_pct_fall : 70; nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; delay_model : generic_cmos; /* Latch */ cell(latch) { area : 5; latch ("IQ","IQN") { enable : (G); data_in : "D"; } pin(D) { direction : input; } pin(G) { direction : input; } pin(Q) { direction : output; function : "IQ"; internal_node : "Q"; timing() { timing_type : rising_edge; intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; fall_resistance : 0; related_pin : "G"; } timing() { timing_sense : positive_unate; intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; fall_resistance : 0; related_pin : "D"; } } pin(QN) { direction : output; function : "IQN"; internal_node : "QN"; timing() { timing_type : rising_edge; intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; fall_resistance : 0; related_pin : "G"; } timing() { timing_sense : negative_unate; intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; fall_resistance : 0; related_pin : "D"; } } } }