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.gitignore
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write_verilog: don't assign to a reg .
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2024-04-03 13:06:45 +02:00 |
aes_kexp128.v
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always01.v
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always02.v
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always03.v
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arraycells.v
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arrays01.v
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arrays02.sv
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arrays03.sv
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Added test for multidimensional packed arrays
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2024-02-11 11:26:52 -05:00 |
asgn_binop.sv
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sv: support remaining assignment operators
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2021-05-25 16:15:57 -04:00 |
attrib01_module.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
attrib02_port_decl.v
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attrib03_parameter.v
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attrib04_net_var.v
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attrib05_port_conn.v.DISABLED
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attrib06_operator_suffix.v
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attrib07_func_call.v.DISABLED
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
attrib08_mod_inst.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
attrib09_case.v
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carryadd.v
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case_expr_const.v
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case_expr_extend.sv
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fix iverilog compatibility for new case expr tests
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2022-01-03 12:11:41 -07:00 |
case_expr_non_const.v
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case_expr_query.sv
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case_large.v
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const_branch_finish.v
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const_fold_func.v
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const_func_shadow.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
constmuldivmod.v
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Expand tests/simple/constmuldivmod.v
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2020-05-28 22:59:04 +02:00 |
constpower.v
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
defvalue.sv
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dff_different_styles.v
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dff_init.v
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dynslice.v
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fiedler-cooley.v
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initial import
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2013-01-05 11:13:26 +01:00 |
forgen01.v
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forgen02.v
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forloops.v
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Add additional test cases for for-loops
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2019-05-01 09:32:07 +02:00 |
fsm.v
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func_block.v
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func_recurse.v
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func_width_scope.v
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genblk_collide.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
genblk_dive.v
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genblk_order.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
genblk_port_shadow.v
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generate.v
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graphtest.v
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hierarchy.v
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hierdefparam.v
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i2c_master_tests.v
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ifdef_1.v
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ifdef_2.v
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implicit_ports.sv
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Fix valgrind tests when using verific
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2022-03-30 17:25:53 +02:00 |
lesser_size_cast.sv
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local_loop_var.sv
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
localparam_attr.v
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loop_prefix_case.v
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loop_var_shadow.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
loops.v
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
macro_arg_spaces.sv
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macro_arg_surrounding_spaces.v
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macros.v
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matching_end_labels.sv
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
mem2reg.v
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mem2reg_bounds_tern.v
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Fix "make vgtest" so it runs to the end (but now it fails ;)
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2021-09-23 14:54:28 +02:00 |
mem_arst.v
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Make SV2017 compliant courtesy of @wsnyder
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2019-12-12 07:34:07 -08:00 |
memory.v
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Fix test of memory vs. memory converted to registers
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2024-02-11 11:26:52 -05:00 |
memwr_port_connection.sv
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verilog: use derived module info to elaborate cell connections
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2021-10-25 18:25:50 -07:00 |
module_scope.v
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Fix valgrind tests when using verific
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2022-03-30 17:25:53 +02:00 |
module_scope_case.v
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module_scope_func.v
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multiplier.v
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muxtree.v
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named_genblk.v
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nested_genblk_resolve.v
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omsp_dbg_uart.v
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operators.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
param_attr.v
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paramods.v
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partsel.v
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process.v
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
realexpr.v
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repwhile.v
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retime.v
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Add retime test
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2019-04-05 16:28:46 -07:00 |
rotate.v
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run-test.sh
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tests: use /usr/bin/env for bash.
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2023-08-12 11:59:39 +10:00 |
scopes.v
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sign_part_assign.v
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Add test for rhs sign extension in array slice assignment
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2024-01-10 21:15:00 +01:00 |
signed_full_slice.v
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signedexpr.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
sincos.v
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specify.v
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string_format.v
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subbytes.v
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task_func.v
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undef_eqx_nex.v
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unnamed_block_decl.sv
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usb_phy_tests.v
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values.v
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verilog_primitives.v
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vloghammer.v
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wandwor.v
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wreduce.v
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xfirrtl
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