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32 lines
978 B
Text
32 lines
978 B
Text
# Issue #4402: read_verilog doesn't respect signed keyword
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#
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# write_verilog was not emitting the signed keyword for port declarations.
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# Uses the original reproduction module from the issue (var2/var3 given
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# initial values of 0, which were uninitialized/assumed-zero in the report).
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#
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# Pre-synthesis simulation: wire0=1'b1 (signed -1), -1<=0 true -> y=0
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# Post-synthesis (unfixed): wire0 loses signed, 1<=0 false -> y=1 (BUG)
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# Post-synthesis (fixed): wire0 retains signed, -1<=0 true -> y=0
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! mkdir -p temp
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read_verilog <<EOT
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module top (y, clk, wire0);
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output wire y;
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input wire clk;
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input wire signed wire0;
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reg reg1;
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reg var2 = 0;
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reg var3 = 0;
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assign y = reg1;
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always @(posedge clk) begin
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reg1 = ($signed(wire0 <= 0) ? $unsigned(-var3) : (^~$signed(var2)));
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end
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endmodule
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EOT
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hierarchy -top top
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proc
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write_verilog temp/issue4402_syn.v
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# Port declaration must include the signed keyword.
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! grep -q "input signed wire0" temp/issue4402_syn.v
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